From nobody Tue Nov 26 16:33:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1706660973; cv=none; d=zohomail.com; s=zohoarc; b=UemmN9n9rGhkGSW3Jdp2jfM54nbO7LPyV5EJ2bIHkPP/L2n/HTGlEXdcI2RmqDXTxOPUdO7MGm/E1ptHNpZYV6CRmZM7xKpeiVnxnlYbQCbIvgAZeQbVNoqB2jiuPr1L+MKeOezeUw20KLb8Mq1Np6CrZB0w9KQod/pDk6gopR0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706660973; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Q+4P83mYjYL0Kd0M/QZdVfGXCvzl3BzBTC85cdFIryk=; b=FdvARk/YKrBPVCDOSeFCDBu/ucFbQSQpnUJuh5YxAuRTMkH68OaYh0nVvPEKzoUIDxLI7hCAHwfoq6tJO6I8F5lDUs2XT0DvM+2ieQKYLUc1BlHmIFy6OTzsHPLLM9vno4Dc7puZtz8CdTV4cpqhron7kgHaOYr1/1HXX0X41Co= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706660973600712.5123774187847; Tue, 30 Jan 2024 16:29:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUySt-0007JI-Ro; Tue, 30 Jan 2024 19:28:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3HJS5ZQwKCl8K78FEBPQBC7KDLLDIB.9LJNBJR-ABSBIKLKDKR.LOD@flex--nabihestefan.bounces.google.com>) id 1rUySq-0007Fu-VR for qemu-devel@nongnu.org; Tue, 30 Jan 2024 19:28:28 -0500 Received: from mail-yb1-xb49.google.com ([2607:f8b0:4864:20::b49]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3HJS5ZQwKCl8K78FEBPQBC7KDLLDIB.9LJNBJR-ABSBIKLKDKR.LOD@flex--nabihestefan.bounces.google.com>) id 1rUySc-0004Kx-Jk for qemu-devel@nongnu.org; Tue, 30 Jan 2024 19:28:28 -0500 Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-dc6ae0f615eso1057189276.0 for ; Tue, 30 Jan 2024 16:28:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1706660893; x=1707265693; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=Q+4P83mYjYL0Kd0M/QZdVfGXCvzl3BzBTC85cdFIryk=; b=AHR8JemZXM/0PciCsgsvP/Re9+DtKZ4mqN8mlPEyWOdLsyjijzcT9HIVmRM+FxObPb faxnek7vJ2nE1pL9EqCH0AYmbALZSa+JFsHC3ILHGaDvH7X8HqonDJWAfy40qPHOk0Vr rgBe/2yiKrEeXyzjfswbvkLM4KYryz/yIFEkiD7w7kPB41gxpfEXlRTYuz1qY+XxkiU+ DJfrV+he7Wn4N+8vPsnIiTzjmzwmpi+geSXVY2hKX1AhYw7PS1e55NZF8NYa4EqgnDUz o0fmAjJxpVYiGyh1OK6rytzZsLmkLoe/Af8FQT+PhVbK/i67uPF47E4YZ4nIS8G2NSZd +K/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706660893; x=1707265693; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Q+4P83mYjYL0Kd0M/QZdVfGXCvzl3BzBTC85cdFIryk=; b=oafD+5W2illN7t6ilHpkPxCrNm3Y1Di60Xew9whTe1eas21i4mBhR5R1yQ2/KQvByf UsskvTYb5G5bZ0kjDgb6YmSN/Eyu56+GZwqQBSMOatistWg08cTPlSptYnB3/5xUin2d 2IFIjLqCRtYCLF1vhiO3+m7Z+MF8q0zYdUAN/nMr+oL5f9pMFUPuDgHI57G5qiFL/w2Z i1EOPMj6hdbqYS3uZakpIXkGBJmrcCBZsp2pH5adnpuUGXZRXmOfJx1Rr2qmvs+b12+Q zlil6iUpUZ206QYV1ZUtSsXYbWs8o7gslTehPqCyEcFnQmxql9xRZII5hZu8lMthLLbT q9Aw== X-Gm-Message-State: AOJu0YwpsV2jKqeE17YuSBdYJOKUdPxp4L6Daxn9e+FI6mUEYHCRDtmN BKEWYixgnqNuCFOus7x/g5K82DlkBDuIAoU4wkIwa/dr+vezAVkUxwXtKXmqf5If2qOMkj/zSXV BYka2505Dkc2kugyDI2aoh7TOtg== X-Google-Smtp-Source: AGHT+IHW1U/sMI6hc6cTY3X2Kasf4IyMBYBuEKO9cCRarVxzOcaIxwzbARzD58FQ//CZgFLJw16Ua0lH/Amo6bRLp8Q= X-Received: from nabihestefan.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:2737]) (user=nabihestefan job=sendgmr) by 2002:a05:6902:218e:b0:dc2:1f34:fac4 with SMTP id dl14-20020a056902218e00b00dc21f34fac4mr49506ybb.2.1706660892942; Tue, 30 Jan 2024 16:28:12 -0800 (PST) Date: Wed, 31 Jan 2024 00:27:59 +0000 In-Reply-To: <20240131002800.989285-1-nabihestefan@google.com> Mime-Version: 1.0 References: <20240131002800.989285-1-nabihestefan@google.com> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog Message-ID: <20240131002800.989285-7-nabihestefan@google.com> Subject: [PATCH v16 6/6] tests/qtest: Adding PCS Module test to GMAC Qtest From: Nabih Estefan To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kfting@nuvoton.com, wuhaotsh@google.com, jasowang@redhat.com, avi.fishman@nuvoton.com, nabihestefan@google.com, kwliu@nuvoton.com, tomer.maimon@nuvoton.com, Hila.Miranda-Kuzi@nuvoton.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::b49; envelope-from=3HJS5ZQwKCl8K78FEBPQBC7KDLLDIB.9LJNBJR-ABSBIKLKDKR.LOD@flex--nabihestefan.bounces.google.com; helo=mail-yb1-xb49.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008, USER_IN_DEF_DKIM_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1706660974334100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nabih Estefan Diaz - Add PCS Register check to npcm_gmac-test Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12 Signed-off-by: Nabih Estefan Reviewed-by: Tyrone Ting --- tests/qtest/npcm_gmac-test.c | 132 +++++++++++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c index 72c68874df..9e58b15ca1 100644 --- a/tests/qtest/npcm_gmac-test.c +++ b/tests/qtest/npcm_gmac-test.c @@ -23,6 +23,10 @@ /* Name of the GMAC Device */ #define TYPE_NPCM_GMAC "npcm-gmac" =20 +/* Address of the PCS Module */ +#define PCS_BASE_ADDRESS 0xf0780000 +#define NPCM_PCS_IND_AC_BA 0x1fe + typedef struct GMACModule { int irq; uint64_t base_addr; @@ -114,6 +118,62 @@ typedef enum NPCMRegister { NPCM_GMAC_PTP_STNSUR =3D 0x714, NPCM_GMAC_PTP_TAR =3D 0x718, NPCM_GMAC_PTP_TTSR =3D 0x71c, + + /* PCS Registers */ + NPCM_PCS_SR_CTL_ID1 =3D 0x3c0008, + NPCM_PCS_SR_CTL_ID2 =3D 0x3c000a, + NPCM_PCS_SR_CTL_STS =3D 0x3c0010, + + NPCM_PCS_SR_MII_CTRL =3D 0x3e0000, + NPCM_PCS_SR_MII_STS =3D 0x3e0002, + NPCM_PCS_SR_MII_DEV_ID1 =3D 0x3e0004, + NPCM_PCS_SR_MII_DEV_ID2 =3D 0x3e0006, + NPCM_PCS_SR_MII_AN_ADV =3D 0x3e0008, + NPCM_PCS_SR_MII_LP_BABL =3D 0x3e000a, + NPCM_PCS_SR_MII_AN_EXPN =3D 0x3e000c, + NPCM_PCS_SR_MII_EXT_STS =3D 0x3e001e, + + NPCM_PCS_SR_TIM_SYNC_ABL =3D 0x3e0e10, + NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR =3D 0x3e0e12, + NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR =3D 0x3e0e14, + NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR =3D 0x3e0e16, + NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR =3D 0x3e0e18, + NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR =3D 0x3e0e1a, + NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR =3D 0x3e0e1c, + NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR =3D 0x3e0e1e, + NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR =3D 0x3e0e20, + + NPCM_PCS_VR_MII_MMD_DIG_CTRL1 =3D 0x3f0000, + NPCM_PCS_VR_MII_AN_CTRL =3D 0x3f0002, + NPCM_PCS_VR_MII_AN_INTR_STS =3D 0x3f0004, + NPCM_PCS_VR_MII_TC =3D 0x3f0006, + NPCM_PCS_VR_MII_DBG_CTRL =3D 0x3f000a, + NPCM_PCS_VR_MII_EEE_MCTRL0 =3D 0x3f000c, + NPCM_PCS_VR_MII_EEE_TXTIMER =3D 0x3f0010, + NPCM_PCS_VR_MII_EEE_RXTIMER =3D 0x3f0012, + NPCM_PCS_VR_MII_LINK_TIMER_CTRL =3D 0x3f0014, + NPCM_PCS_VR_MII_EEE_MCTRL1 =3D 0x3f0016, + NPCM_PCS_VR_MII_DIG_STS =3D 0x3f0020, + NPCM_PCS_VR_MII_ICG_ERRCNT1 =3D 0x3f0022, + NPCM_PCS_VR_MII_MISC_STS =3D 0x3f0030, + NPCM_PCS_VR_MII_RX_LSTS =3D 0x3f0040, + NPCM_PCS_VR_MII_MP_TX_BSTCTRL0 =3D 0x3f0070, + NPCM_PCS_VR_MII_MP_TX_LVLCTRL0 =3D 0x3f0074, + NPCM_PCS_VR_MII_MP_TX_GENCTRL0 =3D 0x3f007a, + NPCM_PCS_VR_MII_MP_TX_GENCTRL1 =3D 0x3f007c, + NPCM_PCS_VR_MII_MP_TX_STS =3D 0x3f0090, + NPCM_PCS_VR_MII_MP_RX_GENCTRL0 =3D 0x3f00b0, + NPCM_PCS_VR_MII_MP_RX_GENCTRL1 =3D 0x3f00b2, + NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0 =3D 0x3f00ba, + NPCM_PCS_VR_MII_MP_MPLL_CTRL0 =3D 0x3f00f0, + NPCM_PCS_VR_MII_MP_MPLL_CTRL1 =3D 0x3f00f2, + NPCM_PCS_VR_MII_MP_MPLL_STS =3D 0x3f0110, + NPCM_PCS_VR_MII_MP_MISC_CTRL2 =3D 0x3f0126, + NPCM_PCS_VR_MII_MP_LVL_CTRL =3D 0x3f0130, + NPCM_PCS_VR_MII_MP_MISC_CTRL0 =3D 0x3f0132, + NPCM_PCS_VR_MII_MP_MISC_CTRL1 =3D 0x3f0134, + NPCM_PCS_VR_MII_DIG_CTRL2 =3D 0x3f01c2, + NPCM_PCS_VR_MII_DIG_ERRCNT_SEL =3D 0x3f01c4, } NPCMRegister; =20 static uint32_t gmac_read(QTestState *qts, const GMACModule *mod, @@ -122,6 +182,15 @@ static uint32_t gmac_read(QTestState *qts, const GMACM= odule *mod, return qtest_readl(qts, mod->base_addr + regno); } =20 +static uint16_t pcs_read(QTestState *qts, const GMACModule *mod, + NPCMRegister regno) +{ + uint32_t write_value =3D (regno & 0x3ffe00) >> 9; + qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value); + uint32_t read_offset =3D regno & 0x1ff; + return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset); +} + /* Check that GMAC registers are reset to default value */ static void test_init(gconstpointer test_data) { @@ -134,6 +203,11 @@ static void test_init(gconstpointer test_data) g_assert_cmphex(gmac_read(qts, mod, (regno)), =3D=3D, (value)); \ } while (0) =20 +#define CHECK_REG_PCS(regno, value) \ + do { \ + g_assert_cmphex(pcs_read(qts, mod, (regno)), =3D=3D, (value)); \ + } while (0) + CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100); CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0); CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0); @@ -183,6 +257,64 @@ static void test_init(gconstpointer test_data) CHECK_REG32(NPCM_GMAC_PTP_TAR, 0); CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0); =20 + /* TODO Add registers PCS */ + if (mod->base_addr =3D=3D 0xf0802000) { + CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e); + CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0); + CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000); + + CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140); + CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109); + CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e); + CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0); + CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020); + CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0); + CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0); + CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000); + + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003); + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038); + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0); + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038); + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0); + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058); + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0); + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048); + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0); + + CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400); + CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a); + CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c); + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010); + CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0); + CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0); + } + qtest_quit(qts); } =20 --=20 2.43.0.429.g432eaa2c6b-goog