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charset="utf-8" From: Nabih Estefan Diaz - Created qtest to check initialization of registers in GMAC Module. - Implemented test into Build File. Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d Signed-off-by: Nabih Estefan Reviewed-by: Tyrone Ting --- tests/qtest/meson.build | 1 + tests/qtest/npcm_gmac-test.c | 212 +++++++++++++++++++++++++++++++++++ 2 files changed, 213 insertions(+) create mode 100644 tests/qtest/npcm_gmac-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 84a055a7d9..016cd77d20 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -230,6 +230,7 @@ qtests_aarch64 =3D \ (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : [])= + \ (config_all_accel.has_key('CONFIG_TCG') and = \ config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test']= : []) + \ + (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c new file mode 100644 index 0000000000..72c68874df --- /dev/null +++ b/tests/qtest/npcm_gmac-test.c @@ -0,0 +1,212 @@ +/* + * QTests for Nuvoton NPCM7xx/8xx GMAC Modules. + * + * Copyright 2024 Google LLC + * Authors: + * Hao Wu + * Nabih Estefan + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqos/libqos.h" + +/* Name of the GMAC Device */ +#define TYPE_NPCM_GMAC "npcm-gmac" + +typedef struct GMACModule { + int irq; + uint64_t base_addr; +} GMACModule; + +typedef struct TestData { + const GMACModule *module; +} TestData; + +/* Values extracted from hw/arm/npcm8xx.c */ +static const GMACModule gmac_module_list[] =3D { + { + .irq =3D 14, + .base_addr =3D 0xf0802000 + }, + { + .irq =3D 15, + .base_addr =3D 0xf0804000 + }, + { + .irq =3D 16, + .base_addr =3D 0xf0806000 + }, + { + .irq =3D 17, + .base_addr =3D 0xf0808000 + } +}; + +/* Returns the index of the GMAC module. */ +static int gmac_module_index(const GMACModule *mod) +{ + ptrdiff_t diff =3D mod - gmac_module_list; + + g_assert_true(diff >=3D 0 && diff < ARRAY_SIZE(gmac_module_list)); + + return diff; +} + +/* 32-bit register indices. Taken from npcm_gmac.c */ +typedef enum NPCMRegister { + /* DMA Registers */ + NPCM_DMA_BUS_MODE =3D 0x1000, + NPCM_DMA_XMT_POLL_DEMAND =3D 0x1004, + NPCM_DMA_RCV_POLL_DEMAND =3D 0x1008, + NPCM_DMA_RCV_BASE_ADDR =3D 0x100c, + NPCM_DMA_TX_BASE_ADDR =3D 0x1010, + NPCM_DMA_STATUS =3D 0x1014, + NPCM_DMA_CONTROL =3D 0x1018, + NPCM_DMA_INTR_ENA =3D 0x101c, + NPCM_DMA_MISSED_FRAME_CTR =3D 0x1020, + NPCM_DMA_HOST_TX_DESC =3D 0x1048, + NPCM_DMA_HOST_RX_DESC =3D 0x104c, + NPCM_DMA_CUR_TX_BUF_ADDR =3D 0x1050, + NPCM_DMA_CUR_RX_BUF_ADDR =3D 0x1054, + NPCM_DMA_HW_FEATURE =3D 0x1058, + + /* GMAC Registers */ + NPCM_GMAC_MAC_CONFIG =3D 0x0, + NPCM_GMAC_FRAME_FILTER =3D 0x4, + NPCM_GMAC_HASH_HIGH =3D 0x8, + NPCM_GMAC_HASH_LOW =3D 0xc, + NPCM_GMAC_MII_ADDR =3D 0x10, + NPCM_GMAC_MII_DATA =3D 0x14, + NPCM_GMAC_FLOW_CTRL =3D 0x18, + NPCM_GMAC_VLAN_FLAG =3D 0x1c, + NPCM_GMAC_VERSION =3D 0x20, + NPCM_GMAC_WAKEUP_FILTER =3D 0x28, + NPCM_GMAC_PMT =3D 0x2c, + NPCM_GMAC_LPI_CTRL =3D 0x30, + NPCM_GMAC_TIMER_CTRL =3D 0x34, + NPCM_GMAC_INT_STATUS =3D 0x38, + NPCM_GMAC_INT_MASK =3D 0x3c, + NPCM_GMAC_MAC0_ADDR_HI =3D 0x40, + NPCM_GMAC_MAC0_ADDR_LO =3D 0x44, + NPCM_GMAC_MAC1_ADDR_HI =3D 0x48, + NPCM_GMAC_MAC1_ADDR_LO =3D 0x4c, + NPCM_GMAC_MAC2_ADDR_HI =3D 0x50, + NPCM_GMAC_MAC2_ADDR_LO =3D 0x54, + NPCM_GMAC_MAC3_ADDR_HI =3D 0x58, + NPCM_GMAC_MAC3_ADDR_LO =3D 0x5c, + NPCM_GMAC_RGMII_STATUS =3D 0xd8, + NPCM_GMAC_WATCHDOG =3D 0xdc, + NPCM_GMAC_PTP_TCR =3D 0x700, + NPCM_GMAC_PTP_SSIR =3D 0x704, + NPCM_GMAC_PTP_STSR =3D 0x708, + NPCM_GMAC_PTP_STNSR =3D 0x70c, + NPCM_GMAC_PTP_STSUR =3D 0x710, + NPCM_GMAC_PTP_STNSUR =3D 0x714, + NPCM_GMAC_PTP_TAR =3D 0x718, + NPCM_GMAC_PTP_TTSR =3D 0x71c, +} NPCMRegister; + +static uint32_t gmac_read(QTestState *qts, const GMACModule *mod, + NPCMRegister regno) +{ + return qtest_readl(qts, mod->base_addr + regno); +} + +/* Check that GMAC registers are reset to default value */ +static void test_init(gconstpointer test_data) +{ + const TestData *td =3D test_data; + const GMACModule *mod =3D td->module; + QTestState *qts =3D qtest_init("-machine npcm845-evb"); + +#define CHECK_REG32(regno, value) \ + do { \ + g_assert_cmphex(gmac_read(qts, mod, (regno)), =3D=3D, (value)); \ + } while (0) + + CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100); + CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0); + CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0); + CHECK_REG32(NPCM_DMA_RCV_BASE_ADDR, 0); + CHECK_REG32(NPCM_DMA_TX_BASE_ADDR, 0); + CHECK_REG32(NPCM_DMA_STATUS, 0); + CHECK_REG32(NPCM_DMA_CONTROL, 0); + CHECK_REG32(NPCM_DMA_INTR_ENA, 0); + CHECK_REG32(NPCM_DMA_MISSED_FRAME_CTR, 0); + CHECK_REG32(NPCM_DMA_HOST_TX_DESC, 0); + CHECK_REG32(NPCM_DMA_HOST_RX_DESC, 0); + CHECK_REG32(NPCM_DMA_CUR_TX_BUF_ADDR, 0); + CHECK_REG32(NPCM_DMA_CUR_RX_BUF_ADDR, 0); + CHECK_REG32(NPCM_DMA_HW_FEATURE, 0x100d4f37); + + CHECK_REG32(NPCM_GMAC_MAC_CONFIG, 0); + CHECK_REG32(NPCM_GMAC_FRAME_FILTER, 0); + CHECK_REG32(NPCM_GMAC_HASH_HIGH, 0); + CHECK_REG32(NPCM_GMAC_HASH_LOW, 0); + CHECK_REG32(NPCM_GMAC_MII_ADDR, 0); + CHECK_REG32(NPCM_GMAC_MII_DATA, 0); + CHECK_REG32(NPCM_GMAC_FLOW_CTRL, 0); + CHECK_REG32(NPCM_GMAC_VLAN_FLAG, 0); + CHECK_REG32(NPCM_GMAC_VERSION, 0x00001032); + CHECK_REG32(NPCM_GMAC_WAKEUP_FILTER, 0); + CHECK_REG32(NPCM_GMAC_PMT, 0); + CHECK_REG32(NPCM_GMAC_LPI_CTRL, 0); + CHECK_REG32(NPCM_GMAC_TIMER_CTRL, 0x03e80000); + CHECK_REG32(NPCM_GMAC_INT_STATUS, 0); + CHECK_REG32(NPCM_GMAC_INT_MASK, 0); + CHECK_REG32(NPCM_GMAC_MAC0_ADDR_HI, 0x8000ffff); + CHECK_REG32(NPCM_GMAC_MAC0_ADDR_LO, 0xffffffff); + CHECK_REG32(NPCM_GMAC_MAC1_ADDR_HI, 0x0000ffff); + CHECK_REG32(NPCM_GMAC_MAC1_ADDR_LO, 0xffffffff); + CHECK_REG32(NPCM_GMAC_MAC2_ADDR_HI, 0x0000ffff); + CHECK_REG32(NPCM_GMAC_MAC2_ADDR_LO, 0xffffffff); + CHECK_REG32(NPCM_GMAC_MAC3_ADDR_HI, 0x0000ffff); + CHECK_REG32(NPCM_GMAC_MAC3_ADDR_LO, 0xffffffff); + CHECK_REG32(NPCM_GMAC_RGMII_STATUS, 0); + CHECK_REG32(NPCM_GMAC_WATCHDOG, 0); + CHECK_REG32(NPCM_GMAC_PTP_TCR, 0x00002000); + CHECK_REG32(NPCM_GMAC_PTP_SSIR, 0); + CHECK_REG32(NPCM_GMAC_PTP_STSR, 0); + CHECK_REG32(NPCM_GMAC_PTP_STNSR, 0); + CHECK_REG32(NPCM_GMAC_PTP_STSUR, 0); + CHECK_REG32(NPCM_GMAC_PTP_STNSUR, 0); + CHECK_REG32(NPCM_GMAC_PTP_TAR, 0); + CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0); + + qtest_quit(qts); +} + +static void gmac_add_test(const char *name, const TestData* td, + GTestDataFunc fn) +{ + g_autofree char *full_name =3D g_strdup_printf( + "npcm7xx_gmac/gmac[%d]/%s", gmac_module_index(td->module), nam= e); + qtest_add_data_func(full_name, td, fn); +} + +int main(int argc, char **argv) +{ + TestData test_data_list[ARRAY_SIZE(gmac_module_list)]; + + g_test_init(&argc, &argv, NULL); + + for (int i =3D 0; i < ARRAY_SIZE(gmac_module_list); ++i) { + TestData *td =3D &test_data_list[i]; + + td->module =3D &gmac_module_list[i]; + + gmac_add_test("init", td, test_init); + } + + return g_test_run(); +} --=20 2.43.0.429.g432eaa2c6b-goog