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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571098; x=1707175898; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w0VyFnxuloTGEbgz18a76FD3rClrdXq5QXu0ykcKSCs=; b=dDu5Fzmg1m1j4TMzpFO5oBgSfAeYER55EUWsAP6AISz4GNTuOXsNLEQOpxBOjxfVeh OFKxHY1Dg9jM8v15c6yBNB4TqCnWHfZOAbkqsu3vQanHP7dydAWjulusS7ejuuEXj+fE tNMwJdjjIEzFzc1lzGc8M9N1tOlOuMLKvj2DNy2U53ahCPvDMiKJ9V0c70/bV3JXH8Hw lQ5hiurd1PYyXBZ0g7sx3HUeW3HlSU34NvcI6OIFnyeadNpNeeWBt3kvFBxBvWP3lkWr cr1kFYBK8mNfHm7+DkL5lR9iP3/rAuOeLaOhyCR04qt2IL1YePOFxEyhWnQXLqWu8Kpl faQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571098; x=1707175898; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w0VyFnxuloTGEbgz18a76FD3rClrdXq5QXu0ykcKSCs=; b=cg5nFdDobEIhj72E4H9kAOnOyrYHog9rQxh8NjowidbtGZKDtQpUfpjGG1Aiamk4fK DoK6lTFFSR9nq11sNGNNvfqWJgYcnsZGFYYGKaIvTSXIW8n9hU/i+vcNCXJpnhZxc9hb l5QyDCcl9k3p2XAEsdLyOabt+BF6Stmp+/Sw+ye3gFX6muvM3Ao1Piizyf5Q1twkAuQ5 Wthmb1R4eVqSvNrLuhqK961JKaPE2Bf4/Yw1s8poBIA5KkfOfebszP8ifEBoXOWY+NXp Q4Ezi1T9Lq/E80lFLDnkucqrbMv23uqvxoiP7gGdGKr3f6lmDNaa7ctl72c4no6sojYg dmMw== X-Gm-Message-State: AOJu0YzhbFPMEF0QYYWVhD6nI8Gw2jutirZQqxoZymkeAjmwHSwhCc/a 2wb2rCuKsblDL4PA44HnclfWkEFwRopt5D1iDlDBX5xy5m0TQMrV7pXfDErgwEa74Vdb9Jg73cP 2+A8= X-Google-Smtp-Source: AGHT+IGw/8CG5ZBjwIZcWvlYi4Oa4Q3VTp3fsYs80/zzCxy2X/R2NxoC0sTGvcNQ4Ui7N9tQnWA/bw== X-Received: by 2002:a17:90a:a512:b0:290:6c4:ad45 with SMTP id a18-20020a17090aa51200b0029006c4ad45mr4216647pjq.39.1706571098448; Mon, 29 Jan 2024 15:31:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 22/33] target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index Date: Tue, 30 Jan 2024 09:30:32 +1000 Message-Id: <20240129233043.34558-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571237868100003 Content-Type: text/plain; charset="utf-8" Free up the riscv_cpu_mmu_index name for other usage; emphasize that the argument is 'env'. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 4 ++-- target/riscv/cpu_helper.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5f3955c38d..9c825c7b51 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -498,7 +498,7 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); +int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t reta= ddr); @@ -507,7 +507,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); =20 -#define cpu_mmu_index riscv_cpu_mmu_index +#define cpu_mmu_index riscv_env_mmu_index =20 #ifndef CONFIG_USER_ONLY void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c7cc7eb423..15f87ecdb0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -33,7 +33,7 @@ #include "debug.h" #include "tcg/oversized-guest.h" =20 -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) +int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return 0; --=20 2.34.1