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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571091; x=1707175891; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KeckyFuoEvdgwHDKZRRirlX+WDs+LbKrZFrG7XL0TJk=; b=xnik9OU4u37UwQV2jLj+YnG19G2k9IPAh46scxUfAa0icHDEO5vpdue/MCjYKBSCXn RUM7KflzOP513Wn1gSJgGhSxE/ylNYpaf4lDIwEKVG1tDkrWhP/X8h155kWWlhVm8hwA +KwMHctcnMHzidDKN/eU7sbuny+Sc4L5Y0wZuoIF38QAdhrnl41XuP8lPfnz+cvKg3ko P6Ab8bGJQ40toNpFoOH/hxPiMdWCSw08Uyphb+wurcCJCPGBjzzgvCTtjIcCTOHNmsI5 K2mQ7+H8NyabT0O+FVe+/ku3DQ1UGkCHspgIs4UwB8nNX74We9ebXibb4RaErsvRDfb3 TEgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571091; x=1707175891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KeckyFuoEvdgwHDKZRRirlX+WDs+LbKrZFrG7XL0TJk=; b=FipGBuKZmN6KyHhw3EkdEAAptfyJ6qM/OBxEnTmDY18iyeaaAovGyFKwVqo7vwnY1+ 2oJ5248LSQHNgzkInDoEgUdbAtp0P+CVjdl7lMxLNWT/lCne+hZiO7PtagqcktbdZYey oCtCIBcWCGiMETnb0WN0gp2CXZ8KtydiCQ3WjzzLvwt1Xvqs1Qn7VUNVGCRpQWqho5Fy JKseqxklZzxASL+SLtmtuX9NxkwQrtesxXr6XP8DEXM854oi0OGyYDaxrmdd2vASodm2 453ji/eAg0ywpNcWE3y/W7rTqqtBDpD9+TaYOvIZp2+KyEW0JS8MzkqQiEpJVPOePGj0 keDA== X-Gm-Message-State: AOJu0Yzu9fBPnVbM7fT6Nb4CDFypilLRPYxXyu4RlHTl32z2mfaQL21G tbjEW8v1NHDTdaz9YPfvEAGyxIzTmAHDK2u6j06wm0ukSIgdLiPxMnQmp0nIvkDd1O1PqfsoWfK hzqc= X-Google-Smtp-Source: AGHT+IEcf1hxchPld14Dmkd+CXvljYK7qCOR8zD6SErI6SzjI8olt+mXscuftIKFNsYUFYzd7qXnZA== X-Received: by 2002:a17:902:6b46:b0:1d7:5601:9fb2 with SMTP id g6-20020a1709026b4600b001d756019fb2mr5324087plt.21.1706571091631; Mon, 29 Jan 2024 15:31:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 19/33] target/openrisc: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:29 +1000 Message-Id: <20240129233043.34558-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571205748100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 10 ++-------- target/openrisc/cpu.c | 13 +++++++++++++ 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b454014ddd..7dbed8d8be 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -361,16 +361,10 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCSt= ate *env, vaddr *pc, | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); } =20 +int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) { - int ret =3D MMU_NOMMU_IDX; /* mmu is disabled */ - - if (env->sr & (ifetch ? SR_IME : SR_DME)) { - /* The mmu is enabled; test supervisor state. */ - ret =3D env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; - } - - return ret; + return openrisc_cpu_mmu_index(env_cpu(env), ifetch); } =20 static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 477d49d4bc..8670152c84 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -68,6 +68,18 @@ static bool openrisc_cpu_has_work(CPUState *cs) CPU_INTERRUPT_TIMER); } =20 +int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUOpenRISCState *env =3D cpu_env(cs); + + if (env->sr & (ifetch ? SR_IME : SR_DME)) { + /* The mmu is enabled; test supervisor state. */ + return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; + } + + return MMU_NOMMU_IDX; /* mmu is disabled */ +} + static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) { info->print_insn =3D print_insn_or1k; @@ -239,6 +251,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) =20 cc->class_by_name =3D openrisc_cpu_class_by_name; cc->has_work =3D openrisc_cpu_has_work; + cc->mmu_index =3D openrisc_cpu_mmu_index; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; cc->get_pc =3D openrisc_cpu_get_pc; --=20 2.34.1