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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.30.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:30:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571050; x=1707175850; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bMktE+uuI7KYrw4qy5OMTFd9gSBzokEqXN4YH9Doa28=; b=ulsLexn3B/5d3a8Xp39zbXVqYdQgHD5Tij3M3hEdNGa5oDKQfzpXESKjVcekJsXltE Y0jXw2eMG8qhl047OwZP07HBEsgRDpxcjO/199YPruHkikBkiX9dAiMm4ry2mkFhCJ9W oaAwkVd9sJqCyoQVxkiZ2H4Clqt3NYNw5iQX+n0qMPE+sDkpx58CtXK2yP8VpUE9eX6N J1SdD89Aqt9d46SpKBWFkVZueTOhrPpUyfvw41vtSiCZpi4+F3bD3dPxBZKq/EX1akoz hAM3oJqm61u4crRFuDvJ0XYHS14y2xniDSw2doqGiOg+IqjtG48Ufirbd1EehQZTRmsj Npxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571050; x=1707175850; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bMktE+uuI7KYrw4qy5OMTFd9gSBzokEqXN4YH9Doa28=; b=tdMwufN9NXQdVJjYkrMLBk/q9btK8UjUkvEShNm3Ezdhdf+8xtDQFWgvH9Of8JcK3u /Dlx4QNSNrtxstRAf5vCVDn8HJJgkOWOUR4+T9M18EiJ93+7FpvQ22WfaeeG+5OuMs7V aRFT70ZFl+sgZngMQ0/j06hfRlQ0yxeX04WJffKOM3wsUcBMpJhmAkWgcsQ292t0GuPZ Q24s5c/E7cwZppyji3fy4cgMZcjoqmZ0JWSqdO5TEy4M/ku9qC7/wiH+3Mft7TPCM6hZ IAsToEw8OqNNNkK+aOS77lG5akILWYcv+xA55+gZPh7Xo41iQG5ZCc61manzbEiLc6ph CFag== X-Gm-Message-State: AOJu0Yw2HENhipB11RNIjG865CFrypszYgIiluRg47/xTlxi4eXe5Bad 3PBlXitvfnDuO9Tu07f/f0YeIwe/NoGl1GpmaZCBPinRZJtJi1pbfllkEvCG9q/R5gKfviUmsbC F2I0= X-Google-Smtp-Source: AGHT+IF2OEHim5J36DDZTsSThCAeoJ3CorTTzEaa4zfC80fIH4p56KINqeDtOAORv82gksqUj2jK6Q== X-Received: by 2002:a17:902:7681:b0:1d6:ea58:f593 with SMTP id m1-20020a170902768100b001d6ea58f593mr3157454pll.9.1706571050282; Mon, 29 Jan 2024 15:30:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 01/33] include/hw/core: Add mmu_index to CPUClass Date: Tue, 30 Jan 2024 09:30:11 +1000 Message-Id: <20240129233043.34558-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571119523100009 Content-Type: text/plain; charset="utf-8" To be used after all targets have populated the hook. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 2c284d6397..4385ce54c9 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -103,6 +103,8 @@ struct SysemuCPUOps; * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. + * @mmu_index: Callback for choosing softmmu mmu index; + * may be used internally by memory_rw_debug without TCG. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @query_cpu_fast: @@ -150,6 +152,7 @@ struct CPUClass { void (*parse_features)(const char *typename, char *str, Error **errp); =20 bool (*has_work)(CPUState *cpu); + int (*mmu_index)(CPUState *cpu, bool ifetch); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571115; cv=none; d=zohomail.com; s=zohoarc; b=V3p6fD4GjHcvSW4OdPdft1Hy74vmrAamSNisJyKQpIKvWHq3KA/WzUIPr7b6QFkCgkSLoD/smMYBSq4qkj4uxA9m07DGGALqMksXmolLEplKAE1sCr18ghxur7F7vqMZg7QUckWFSoZoDPDMZ8bSTE9ToPzGPWzJuUvjOKu5eqY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571115; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=GuLjJD6Uv7AUoT7v/CmrWdMUNxFVKqK7N1yrIDiYHSI=; b=eldSg8tWsEJ0CiuFAuHmVJD2nV26moKDFFbBAjQECqDhkusl1OicKHPHsO5aE4AXDB13vNy3lJTCELixKfv7sgvnx7qPoU5Wn3cQ5jvZ/zP2iF9tTOB57G4GcqomUdQFKBWP6WiRjKlji2Gjr7U104McTcE4/jTBJQ/jHuCWnqc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706571115753834.0907909229674; Mon, 29 Jan 2024 15:31:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUb62-0005SE-NC; Mon, 29 Jan 2024 18:31:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUb5b-0005P6-JV for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:30:56 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUb5Z-000508-UW for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:30:55 -0500 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1d8e7ebbbadso8416195ad.3 for ; Mon, 29 Jan 2024 15:30:53 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.30.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:30:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571052; x=1707175852; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GuLjJD6Uv7AUoT7v/CmrWdMUNxFVKqK7N1yrIDiYHSI=; b=Mjp+ErrdOjwvT1r7yE+NwAS617+jGXodN1iq92arzoP+Dj1D144MGeJTcZc4YWirAr VOmXpwEdrrsHCo/n84Km2n5Zl3/k970dQEs0PAGD8FGnhnV4bz5ya7ONSdPznNNxWODc yJG9rO9CrRovnH8FMafz87OjC2TwXNQOAae6c7rWCBGK652lYmXAOZlvaXlNXA0m9YiY /Rt6F36fqaG2izT5LxTWnEcT36iDwtFiv5Nm16wjRoDB6izKkeifOIonr+dMp9/ASp1W K+jIEkOlHMO4nnjudx6v31zgP6Vgj4nB9gSInYnuI01YO/b5Ie5JPs+SjH7aqi000O4K TEbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571052; x=1707175852; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GuLjJD6Uv7AUoT7v/CmrWdMUNxFVKqK7N1yrIDiYHSI=; b=BhiPrjxSthQhEK8tIXr58yaXbp3wzZmVnbh2dBbxBIhVotM1KpiMlJ6RFHPFiddgkB 8ItXr/s6fRdsZdVY38LlZfArHnwjH0J7rsMQ0LeeS+7OhevrcjU5/eIUtIExGuKFaGzg ldah/dh7ZO3aY4uaeO0GUkpkehhtYtMdVFEm302QUqhly3VXSP/JoUgw71WF4PwVKIlW 3RjGSZw9v+fdzuB8DagsK5iJbqf1m4OxHh9aViR88Bn1P6/X9n59DsUe7Zq4e03H8E7i itg+Jcv3m8SWyzTpYfIr+H1rGvrvFiRxuwLMYXCE7RxExpAg4paminFAwhlUJKAmONen XHXA== X-Gm-Message-State: AOJu0Ywq1L0VRtikR4oj/LhsrDGNNeccuCxQxSmZVNTT6dNyTYL1U9hM kEwwrs8hgfDtlUtoSrxYDjtlbP+ZpWyiM9+ahNXb3ZiDXkkNhHXGk8AQgA9r7dUQc77hk7AE6It ICVc= X-Google-Smtp-Source: AGHT+IEktvo2+X+OHpoDfnI6CRxmWwjdpQaddSl7mclrMTwuxda8uAaYjYqpnDDWb3/HM698h6y/gA== X-Received: by 2002:a17:902:bc44:b0:1d8:fe1e:7c8a with SMTP id t4-20020a170902bc4400b001d8fe1e7c8amr1370350plz.106.1706571052578; Mon, 29 Jan 2024 15:30:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 02/33] target/alpha: Split out alpha_env_mmu_index Date: Tue, 30 Jan 2024 09:30:12 +1000 Message-Id: <20240129233043.34558-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571117542100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/cpu.h | 7 ++++++- target/alpha/translate.c | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index ce806587ca..3beff2738a 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -389,7 +389,7 @@ enum { =20 #define TB_FLAG_UNALIGN (1u << 1) =20 -static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) +static inline int alpha_env_mmu_index(CPUAlphaState *env) { int ret =3D env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_= IDX; if (env->flags & ENV_FLAG_PAL_MODE) { @@ -398,6 +398,11 @@ static inline int cpu_mmu_index(CPUAlphaState *env, bo= ol ifetch) return ret; } =20 +static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) +{ + return alpha_env_mmu_index(env); +} + enum { IR_V0 =3D 0, IR_T0 =3D 1, diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 134eb7225b..4b464f8651 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2875,7 +2875,7 @@ static void alpha_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cpu) int64_t bound; =20 ctx->tbflags =3D ctx->base.tb->flags; - ctx->mem_idx =3D cpu_mmu_index(env, false); + ctx->mem_idx =3D alpha_env_mmu_index(env); ctx->implver =3D env->implver; ctx->amask =3D env->amask; =20 --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571269; cv=none; d=zohomail.com; s=zohoarc; b=NMPZOkvegSZY98kIWhkbGU31aCbgw1i6XDfDm12yBQJl2j0t8uCCbSMfh1NT6cN+WCkj4w3k6WMoa+e8srOb4E15b8llkcsubCOVTcOGhjk4l/cLBRPeG4VoaF2IUewpqAKUrQiqwX/u7qvX7CJ/l8V+tqmdKlc+E5R7osmVfBg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571269; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rY4TKU6Y4tdsleFZysMCIHaTnyMqTWQ/l8+rNabU+ew=; b=HOLNKDkcc+aPINpB/NJQFlYlFmdCmzEto4D4hfPHldtcO4D2ImyD0ykGI4Ax61M+i7grL8rkCg+djc5b/lxxYI18vVhSejLMjb+6o+T3Wc7mxiKWeIgbtkv34MSd1DdCvgY1l04bYB7i8tMpqorjPrnbrmLXq7oW7KitZcxOKAk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170657126888888.43460453062482; Mon, 29 Jan 2024 15:34:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUb64-0005aT-41; Mon, 29 Jan 2024 18:31:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUb5d-0005Qh-UK for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:30:57 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUb5c-00050j-Aj for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:30:57 -0500 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6ddd19552e6so1586018b3a.1 for ; Mon, 29 Jan 2024 15:30:55 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571269955100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index de705c3703..bf70173a25 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -64,6 +64,11 @@ static bool alpha_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_MCHK); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571141566100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 5 +++++ target/arm/helper.c | 2 +- target/arm/tcg/helper-a64.c | 4 ++-- target/arm/tcg/mte_helper.c | 18 +++++++++--------- target/arm/tcg/sve_helper.c | 8 ++++---- target/arm/tcg/tlb_helper.c | 2 +- 6 files changed, 22 insertions(+), 17 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 71d6c70bf3..fc337fe40e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -40,6 +40,11 @@ #define BANK_HYP 6 #define BANK_MON 7 =20 +static inline int arm_env_mmu_index(CPUARMState *env) +{ + return EX_TBFLAG_ANY(env->hflags, MMUIDX); +} + static inline bool excp_is_internal(int excp) { /* Return true if this exception number represents a QEMU-internal diff --git a/target/arm/helper.c b/target/arm/helper.c index 945d8571a6..b0488caf40 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7841,7 +7841,7 @@ static void dccvap_writefn(CPUARMState *env, const AR= MCPRegInfo *opaque, uint64_t vaddr_in =3D (uint64_t) value; uint64_t vaddr =3D vaddr_in & ~(dline_size - 1); void *haddr; - int mem_idx =3D cpu_mmu_index(env, false); + int mem_idx =3D arm_env_mmu_index(env); =20 /* This won't be crossing page boundaries */ haddr =3D probe_read(env, vaddr, dline_size, mem_idx, GETPC()); diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 198b975f20..ebaa7f00df 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -856,7 +856,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_= t new_pc) tbii =3D EX_TBFLAG_A64(env->hflags, TBII); if ((tbii >> extract64(new_pc, 55, 1)) & 1) { /* TBI is enabled. */ - int core_mmu_idx =3D cpu_mmu_index(env, false); + int core_mmu_idx =3D arm_env_mmu_index(env); if (regime_has_2_ranges(core_to_aa64_mmu_idx(core_mmu_idx))) { new_pc =3D sextract64(new_pc, 0, 56); } else { @@ -925,7 +925,7 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) */ int blocklen =3D 4 << env_archcpu(env)->dcz_blocksize; uint64_t vaddr =3D vaddr_in & ~(blocklen - 1); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); void *mem; =20 /* diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index ffb8ea1c34..d971b81370 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -291,7 +291,7 @@ static int load_tag1(uint64_t ptr, uint8_t *mem) =20 uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); uint8_t *mem; int rtag =3D 0; =20 @@ -311,7 +311,7 @@ static void check_tag_aligned(CPUARMState *env, uint64_= t ptr, uintptr_t ra) { if (unlikely(!QEMU_IS_ALIGNED(ptr, TAG_GRANULE))) { arm_cpu_do_unaligned_access(env_cpu(env), ptr, MMU_DATA_STORE, - cpu_mmu_index(env, false), ra); + arm_env_mmu_index(env), ra); g_assert_not_reached(); } } @@ -344,7 +344,7 @@ typedef void stg_store1(uint64_t, uint8_t *, int); static inline void do_stg(CPUARMState *env, uint64_t ptr, uint64_t xt, uintptr_t ra, stg_store1 store1) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); uint8_t *mem; =20 check_tag_aligned(env, ptr, ra); @@ -371,7 +371,7 @@ void HELPER(stg_parallel)(CPUARMState *env, uint64_t pt= r, uint64_t xt) =20 void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); uintptr_t ra =3D GETPC(); =20 check_tag_aligned(env, ptr, ra); @@ -381,7 +381,7 @@ void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr) static inline void do_st2g(CPUARMState *env, uint64_t ptr, uint64_t xt, uintptr_t ra, stg_store1 store1) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); int tag =3D allocation_tag_from_addr(xt); uint8_t *mem1, *mem2; =20 @@ -429,7 +429,7 @@ void HELPER(st2g_parallel)(CPUARMState *env, uint64_t p= tr, uint64_t xt) =20 void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); uintptr_t ra =3D GETPC(); int in_page =3D -(ptr | TARGET_PAGE_MASK); =20 @@ -445,7 +445,7 @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) =20 uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); uintptr_t ra =3D GETPC(); int gm_bs =3D env_archcpu(env)->gm_blocksize; int gm_bs_bytes =3D 4 << gm_bs; @@ -505,7 +505,7 @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) =20 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); uintptr_t ra =3D GETPC(); int gm_bs =3D env_archcpu(env)->gm_blocksize; int gm_bs_bytes =3D 4 << gm_bs; @@ -555,7 +555,7 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint6= 4_t val) void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) { uintptr_t ra =3D GETPC(); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); int log2_dcz_bytes, log2_tag_bytes; intptr_t dcz_bytes, tag_bytes; uint8_t *mem; diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index f006d152cc..bce4295d28 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -5481,7 +5481,7 @@ bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFa= ult fault, CPUARMState *env, target_ulong addr, MMUAccessType access_type, uintptr_t retaddr) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); int mem_off =3D info->mem_off_first[0]; bool nofault =3D fault =3D=3D FAULT_NO; bool have_work =3D true; @@ -6529,7 +6529,7 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D arm_env_mmu_index(env); const intptr_t reg_max =3D simd_oprsz(desc); const int scale =3D simd_data(desc); ARMVectorReg scratch; @@ -6715,7 +6715,7 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t= *vg, void *vm, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D arm_env_mmu_index(env); const intptr_t reg_max =3D simd_oprsz(desc); const int scale =3D simd_data(desc); const int esize =3D 1 << esz; @@ -6920,7 +6920,7 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D arm_env_mmu_index(env); const intptr_t reg_max =3D simd_oprsz(desc); const int scale =3D simd_data(desc); void *host[ARM_MAX_VQ * 4]; diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 5477c7fb7d..885bf4ec14 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -281,7 +281,7 @@ void helper_exception_pc_alignment(CPUARMState *env, ta= rget_ulong pc) { ARMMMUFaultInfo fi =3D { .type =3D ARMFault_Alignment }; int target_el =3D exception_target_el(env); - int mmu_idx =3D cpu_mmu_index(env, true); + int mmu_idx =3D arm_env_mmu_index(env); uint32_t fsc; =20 env->exception.vaddress =3D pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571404; cv=none; d=zohomail.com; s=zohoarc; b=klbIVprqn6UlvR8AF5ONpD92wFOSylNxrSekQZ2xQ3YpNo4Lbzwho+bptNLDiNd7ZgI05alP4DQXZ0dpFOBYyOB3edsN2mOpz3QB+Svy4t+8ezQWkjySHWnTounlmbPEL0Uu6nSIa5KsAe+U/YcFFlSgv7rjO3p6DSEyFlkPvI8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571404; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.30.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:30:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571059; x=1707175859; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1XwFQU82n2x7rtRbW4qoRnV77APVvN1DWq124XDZ74k=; b=KCAlCo+uJJJB1y9wJIAh+Q4PHltIEYY4YuHigpmmYujRKlWPl5USb9tc6nr0O0eg4U sKH81+DT1ZCxrP23Jdk6n/k3MctumCHCvbQSa6dsvavqjIEWc10ymKtndRMzSMqFtdRI IDdVam/0Rq7BCVS2N8mctE7g/Lvr8e69xHMcmJcVhz9XjXDiEkYx3S531TqN5LCO8/aB 2It6wnw1BrRK3jeoBG7uuB1zuldZsTEFXLJqMqrp5uqhVIvdCX2erMVu2I7x3kQ0TQtx AdXT2EHl8sQF7/P7y/bJPdo7GbkxoXJQrAIUxRkyJNWYgLL7mhnwswnxne7C+3B49I5a WGQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571059; x=1707175859; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571406171100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6a96b245f2..1f9ea622bd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -133,6 +133,11 @@ static bool arm_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_EXITTB); } =20 +static int arm_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return arm_env_mmu_index(cpu_env(cs)); +} + void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque) { @@ -2497,6 +2502,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D arm_cpu_class_by_name; cc->has_work =3D arm_cpu_has_work; + cc->mmu_index =3D arm_cpu_mmu_index; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; cc->get_pc =3D arm_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571458; cv=none; d=zohomail.com; s=zohoarc; b=nL6SlBk8CzKua06yG4IuBGDPuKVdInKaGGcU1VY4lF7FNWHxJm5+0vBAuZi5KmIhN89u2IK1T6/fku++YHl8uRe0wxHbub0SZ2cDnGnlfQci/pik5uhz87copoNqxiOTYDTGhadP+oxpVHSuCvZhPsvqIXxux1CBBN1+0yY5yTc= ARC-Message-Signature: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.30.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571062; x=1707175862; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P5Fsq2RX8/y2x9aiQTk6UToPX5ZjmTnnnnUS2+II2G4=; b=SeNa/NMfzeruYW+HVQUkavTTiKAuX4/52RZT3dQC3bqQ3kwe9gjkeZW8+STgZ/VnAU yfT4fYHu4IrS4qVO4t0lQW3qsZdvwlStsBhnnJ61omX2sweiBfJnQLoEaVGrDY2whEnH /jfmPWEYOt550d9VPg6tZHBxi14XCer+B3tDu0ZP4E52S2leIrDOSdM/3ZSi2lNAXk5j 38RSFNN6AtK+W2ywL9KqoZZqURtEx3giLfsMHUuf4pcnQsOA4JMDYjYp8v9RQiB0Mbul /6AohlMuoTyEGSFwb2nRp76P3Vgw2JK6fNEysHxkfad5T0+6c1p16gB441attqCwGHHm wfQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571062; x=1707175862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P5Fsq2RX8/y2x9aiQTk6UToPX5ZjmTnnnnUS2+II2G4=; b=jeYZZSrXZ6uKdNgtVZiEB9IaCYfaGf/5D3OcuaJ6AuiDpoRUv3S2Lf8BKctjd49KmL wy85U1QMIZCAFC0xY4fnxtEqekVStMwk1/pUUY41o9FeG42Bkk2cGDByI2H28iYb0lEF Fk/k4IPt21QHLRzCAAx8U6g0dpLTWM4lr2wvs67OfnQ1bUivW/pirgzCSCMm70Vqxnf4 mEISmQpFg9whQ+jPfQsiuz2bTuPV3QJZp7VwPTb/dPWh776rhedj2DlCaNuNbacyX4NN 2BE/Jg4Mt8le0A/l6n1dBBKWgxcdk6vmhPx0wYreVKZgnc2MrWpoOyc89QdUp1c2d32G w1aQ== X-Gm-Message-State: AOJu0Yw1ID0vBaJYX4X9QvpYjmwRW+QzSnq0qYiYaoUWtIx+Le7d/0ty RZ7CwxBpTCPW52IOeSOwQwd2QFsB0bCO+jXJDQz/cAl07eC+45MTW6VBIMOC/neKNPl47p3HUJX e9VY= X-Google-Smtp-Source: AGHT+IFKvBwYZeNrXgyA6nQwPCuY+mjtHM79d8nnDUa7Zys/jNQGXgjayCwAev94250A6amC8zblLA== X-Received: by 2002:a17:902:f691:b0:1d7:5c60:f4f5 with SMTP id l17-20020a170902f69100b001d75c60f4f5mr72001plg.16.1706571061697; Mon, 29 Jan 2024 15:31:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 06/33] target/avr: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:16 +1000 Message-Id: <20240129233043.34558-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571460375100015 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/avr/cpu.h | 4 +--- target/avr/cpu.c | 6 ++++++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 7d5dd42575..4595c6bb18 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -184,9 +184,7 @@ static inline void set_avr_feature(CPUAVRState *env, in= t feature) env->features |=3D (1U << feature); } =20 -#define cpu_mmu_index avr_cpu_mmu_index - -static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) +static inline int cpu_mmu_index(CPUAVRState *env, bool ifetch) { return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 1c68748b24..a40f445af2 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -50,6 +50,11 @@ static bool avr_cpu_has_work(CPUState *cs) && cpu_interrupts_enabled(env); } =20 +static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; +} + static void avr_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -236,6 +241,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->class_by_name =3D avr_cpu_class_by_name; =20 cc->has_work =3D avr_cpu_has_work; + cc->mmu_index =3D avr_cpu_mmu_index; cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->get_pc =3D avr_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571119; cv=none; d=zohomail.com; s=zohoarc; b=AMWhIgGMwHo0QqnafoFrVWZ9n/bLfKg0pyfz71f4RaPGNtAd9f3p7yVdJ1nAxm8briNRkiKOFyRnMpNFsCag1dEt/QC1SUidN898jEEX+Vat5k7IBxAMOSI0JbJFxqxkO+kuULOUcDSGCjlDK4eYKSRZhfUKKs4RKpyrvXpQqmA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571119; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3/S1vigBU1gXfX4oI3MWHNHDSQjD4iR9o36lTMrKyJs=; b=CGrsLCjaFfptO8ftlTDngpIClV1rwlmwf3JwhQ2ExRM/0HLAMCVxZweMozLitS2FFZLk3e9pMy9XQ/wRukg3ZQPHTl7/kzhfbBu9O9/J90kp9CNAcB8JrHCJrm7w8GjWG9kBD6Ug/552gwxw8i7kXq20e9fDAFHMLpazIaabWZ8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170657111921037.10399165342005; Mon, 29 Jan 2024 15:31:59 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUb68-0005iW-DO; Mon, 29 Jan 2024 18:31:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUb5o-0005Sk-94 for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:22 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUb5l-00051m-VV for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:07 -0500 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-6de2e24ea87so869034b3a.3 for ; Mon, 29 Jan 2024 15:31:04 -0800 (PST) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/cris/translate.c | 14 +++++--------- target/cris/translate_v10.c.inc | 6 ++---- 2 files changed, 7 insertions(+), 13 deletions(-) diff --git a/target/cris/translate.c b/target/cris/translate.c index ee1402a9a3..7acea29a01 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -94,6 +94,7 @@ typedef struct DisasContext { =20 CRISCPU *cpu; target_ulong pc, ppc; + int mem_index; =20 /* Decoder. */ unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc= ); @@ -1008,37 +1009,31 @@ static inline void cris_prepare_jmp (DisasContext *= dc, unsigned int type) =20 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr) { - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); - /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ if (dc->delayed_branch =3D=3D 1) { cris_store_direct_jmp(dc); } =20 - tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEUQ); + tcg_gen_qemu_ld_i64(dst, addr, dc->mem_index, MO_TEUQ); } =20 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,=20 unsigned int size, int sign) { - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); - /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ if (dc->delayed_branch =3D=3D 1) { cris_store_direct_jmp(dc); } =20 - tcg_gen_qemu_ld_tl(dst, addr, mem_index, + tcg_gen_qemu_ld_tl(dst, addr, dc->mem_index, MO_TE + ctz32(size) + (sign ? MO_SIGN : 0)); } =20 static void gen_store (DisasContext *dc, TCGv addr, TCGv val, unsigned int size) { - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); - /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ if (dc->delayed_branch =3D=3D 1) { @@ -1055,7 +1050,7 @@ static void gen_store (DisasContext *dc, TCGv addr, T= CGv val, return; } =20 - tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size)); + tcg_gen_qemu_st_tl(val, addr, dc->mem_index, MO_TE + ctz32(size)); =20 if (dc->flags_x) { cris_evaluate_flags(dc); @@ -2971,6 +2966,7 @@ static void cris_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) dc->cpu =3D env_archcpu(env); dc->ppc =3D pc_start; dc->pc =3D pc_start; + dc->mem_index =3D cpu_mmu_index(env, false); dc->flags_uptodate =3D 1; dc->flags_x =3D tb_flags & X_FLAG; dc->cc_x_uptodate =3D 0; diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.= inc index 6df599fdce..73fc27c15d 100644 --- a/target/cris/translate_v10.c.inc +++ b/target/cris/translate_v10.c.inc @@ -91,8 +91,6 @@ static void gen_store_v10_conditional(DisasContext *dc, T= CGv addr, TCGv val, static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val, unsigned int size) { - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); - /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ if (dc->delayed_branch =3D=3D 1) { @@ -101,11 +99,11 @@ static void gen_store_v10(DisasContext *dc, TCGv addr,= TCGv val, =20 /* Conditional writes. */ if (dc->flags_x) { - gen_store_v10_conditional(dc, addr, val, size, mem_index); + gen_store_v10_conditional(dc, addr, val, size, dc->mem_index); return; } =20 - tcg_gen_qemu_st_tl(val, addr, mem_index, ctz32(size) | MO_TE); + tcg_gen_qemu_st_tl(val, addr, dc->mem_index, ctz32(size) | MO_TE); } =20 =20 --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571204; cv=none; d=zohomail.com; s=zohoarc; b=OKTKolj6BExit3FpD5RN6A6C4fobbtDA05gCfujISIXa3bqOp8q1fER27w/r1Qq8F/B5gVTClv4fW0ccSEcdHvVf8EYUO7M9G9kFetI83qKljI46yoYmUqdmZBAAkfJRMfRC2SEYANge+J3UZTKamATwv6EhozW50RDEDAgWC/o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571204; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2DGeNqrAocEQBW3s9u83YvGPr3pag37tdDcMnd/na+Q=; b=CkWtNWERfAayBP4ISdtxe4YIumoFvlANUtlQo4yDygyySv3OqSxPsXX/U3QlQZrOJamV64aBcKLnWPhTmweo1ftqxvl7O8aJ9c7sQRRUQ4vctcnoqmhcuipuNi6TI4zAs9+coDuKtCtrEh9aKN/H8u1i+F8VqAxQm78sptmhpug= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706571204878754.173044149489; Mon, 29 Jan 2024 15:33:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUb65-0005cR-Al; Mon, 29 Jan 2024 18:31:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUb5p-0005Sl-Gp for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:17 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUb5o-00051w-0y for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:09 -0500 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1d74045c463so17491895ad.3 for ; Mon, 29 Jan 2024 15:31:07 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571205786100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/cris/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 6349148b65..163fb05d58 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -56,6 +56,11 @@ static bool cris_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); } =20 +static int cris_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return !!(cpu_env(cs)->pregs[PR_CCS] & U_FLAG); +} + static void cris_cpu_reset_hold(Object *obj) { CPUState *s =3D CPU(obj); @@ -274,6 +279,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D cris_cpu_class_by_name; cc->has_work =3D cris_cpu_has_work; + cc->mmu_index =3D cris_cpu_mmu_index; cc->dump_state =3D cris_cpu_dump_state; cc->set_pc =3D cris_cpu_set_pc; cc->get_pc =3D cris_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571458; cv=none; d=zohomail.com; s=zohoarc; b=nGfUJcUqtbrX595V5e/LS0Snf3+BcXebBJaz1OJg1me2stfsOKDCxnaj9xJmICal720tZjM02M4pUMVQnWqY2NCaX3S2/5b8MDM1DG/L7vOMY+aOpeJk7+xjGA23CoDYK2NLuGGc66+F2YYnUNf8v5XcE71Dl2OhGyVbjSXRtvk= ARC-Message-Signature: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571068; x=1707175868; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZpWWy5vO/pXMstRanLNjNwO63iDqbDF9cuw2FeN4mjg=; b=LbLWACt3f7PeEdqa69AC7wFVT/2MrOjH3h5RlEtsZur7Eyi1n3Gzr1CnlCKwDw+QjP xX3Y0qElRTKViQPHTV1PulLSmPFD+crH/Gom1zhfs3DBVg2kXOoISecz9tq8ZpKaFZFU 2Yb0dW+likUOarWFLJer5GwZzKShVAtuzuWyH7LJv6wDGgRaQvlJglb8Wr1oO5LkyEb/ NSEuXkvnmEcHjornW+yL8wb6ew2joH4mwGT6Bt9SkuzOzdUiESReSY1UyVNFL9qfWbzn aUj8623yOfIT7pAr6sI0ncj0i7NgWAYzBYAQTLrN31wT0+7fVJaZdYnk6evIo4kP98QE VybQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571068; x=1707175868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZpWWy5vO/pXMstRanLNjNwO63iDqbDF9cuw2FeN4mjg=; b=pWgWnnFO3bezoEEgTBGA6E0e1Zwv8dj+WzFYIMcmBfclCBCitw/7PRJ7PUV3uFLdN+ 46inqlUq7JHkNOgFRIkmeyXqgwTY1R2lY58h19KgNsLLsjoeY9SdCVs6DvpVAD2VwcTU FW1OaGdQEXM79dl87jbOsJKQaC6tsjWGNnIaVTb6bRcLf19mpGjixOolHd4qOIvctOgM OC/7Dc5h0Wpn4osshcm3rztKmBDUmPBk8BE8/NLeKXiRRCEgdyL4EHdnamIBmPoWex3B HPccnWpwZjAnmSc14e3z1dMauGD0X+ZwDsoaTF2qPGYZac1yJSMFvb+Q8XBdpmC4+hjJ zxXQ== X-Gm-Message-State: AOJu0Yx39nRS+UfW06KZWdez5wrMU4HS6pY1pqLjoR+YDLyxiy2W5iav 54KCbiq7OJy7C/fOVApLdnVYlHeJTu+ElDj9MI7qnMDryWmdABm95NI7JJ9Y5/aHVL3f//F+HnM LeBE= X-Google-Smtp-Source: AGHT+IGQ4Pbqe896uKMR+Qwx6VCHa3hiugDB9DqJDidghEGTVRHbvarISi1sPusAgbBAbb3xZaxgWQ== X-Received: by 2002:a17:902:650f:b0:1d8:c767:d82d with SMTP id b15-20020a170902650f00b001d8c767d82dmr62066plk.17.1706571068579; Mon, 29 Jan 2024 15:31:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 09/33] target/hppa: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:19 +1000 Message-Id: <20240129233043.34558-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571460346100011 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/cpu.h | 7 ++----- target/hppa/cpu.c | 12 ++++++++++++ 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6a153405d2..04439f247d 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -281,16 +281,13 @@ static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE; } =20 +int hppa_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return MMU_USER_IDX; #else - if (env->psw & (ifetch ? PSW_C : PSW_D)) { - return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P); - } - /* mmu disabled */ - return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; + return hppa_cpu_mmu_index(env_cpu(env), ifetch); #endif } =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 3c019855b4..fbb37e541e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -94,6 +94,17 @@ static bool hppa_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); } =20 +int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUHPPAState *env =3D cpu_env(cs); + + if (env->psw & (ifetch ? PSW_C : PSW_D)) { + return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P); + } + /* mmu disabled */ + return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; +} + static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) { info->mach =3D bfd_mach_hppa20; @@ -194,6 +205,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D hppa_cpu_class_by_name; cc->has_work =3D hppa_cpu_has_work; + cc->mmu_index =3D hppa_cpu_mmu_index; cc->dump_state =3D hppa_cpu_dump_state; cc->set_pc =3D hppa_cpu_set_pc; cc->get_pc =3D hppa_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571186; cv=none; d=zohomail.com; s=zohoarc; b=DYq/2Hnm5C0u8x9uLsrR2qO3cGTSu6uy2Zvne2cw0BkxEKVhESYxzO98zCSp+mG0ne2GjrYJVd6lQEIlaV4mam7JARVwS1Fab+p7m3QIn1cfnd/VvPdJtOuSpQ5KdEmzA6qRwURJvXjJyQS1P8hAM18OfOAr0BCLjTo3ST3jzL4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571186; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7WexDgLCM7IRsjNLi1wAJoGpQCSOk7DFJRsVIQhRYNU=; b=TcYzv1vck3YZooyHEfgaJzFqEUJtZ09nieuwg3eYwFloFMtZ9ookORA61q06AfZfR5pDzkTD+Ld3iQWLpqEMDzw+m9qSiTXxiAjHDYV99DQeiDI6E5J+ld9//Gey2jSSkee/Y/tb2yA+Vc954jgbPgx1bP2xrYY4PX+fHG/rlHA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706571186097156.59843573449643; Mon, 29 Jan 2024 15:33:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUb69-0005k4-G2; Mon, 29 Jan 2024 18:31:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUb5t-0005UC-L9 for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:22 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUb5s-00052S-34 for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:13 -0500 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1d750660a0aso14296275ad.0 for ; Mon, 29 Jan 2024 15:31:11 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571071; x=1707175871; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7WexDgLCM7IRsjNLi1wAJoGpQCSOk7DFJRsVIQhRYNU=; b=V4X37UqiYFgQMacj6ZogKkU/PG/YvQMsBdg7ZZ+rWOXNrrwpYXbdRoRiRoWUOlsZdd Uj9LdFeFPv5f8dfUboX9qVbdelotfsbqjyRKFpsJOZ7jVDuX9HcYDo4i8L8rzrj/9Vog wMviTUsHWBo2Kaih4EO+Yxv05iU0RXqbi/QqYXqVrvl7saRdsyIPpGiyi3fWyKg+4i67 xDwdlX646ZgZ38sXGstYrkSVlXMCMkJDVlbTbLoG60dc+Dj26UkW4xA+gfOtXInvA3x5 0yV24hS56+hOzt0m3OYzlUbgwnoXjAqsOKgRmONvg7ZuwQrrvevKSZ2jaI0HGbhnxH4i Je7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571071; x=1707175871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7WexDgLCM7IRsjNLi1wAJoGpQCSOk7DFJRsVIQhRYNU=; b=CwZZLlS4hhHTqnfRgOQivlP/JOprKfWOmqqqzstdLlByiu6gY1CpUN3jX2gB9XWlvJ D0lp48iJJKW3RvbY69LA61Dqjgxaiu31chG7xVnTue+8p11MIT44u+IUY137J6XAsASP Nw9gi8JPkMxyThx71KIaYD6A4QAeViWZW/4Y/7eA7rJxBkTeo5K08LuYcRoew3ByIWDm BS+Q82pgcLs6b2yWRNI7vb9M8kpKd9Z8Ax3Vm8RhYBqSr/w6/lbjppBhSTU9BPrK2IjQ XZcFCJ6Dwj/ZaRHUUdsHXiM69GlecM9KlOzjMUTSwFuolri6jsRLfzaMMmG2IUJseKqQ 3aNg== X-Gm-Message-State: AOJu0YxF+3fd8+gr5klOeLHWLKPWf5Lw6ylsjnLtMbHrAcxjyGlG2QzT wNm9s4CVtxLv/XEtErCLDIsW57Y/ADLli/lW+EUGZfL+/hH984WkQ8r1Qclz8Sizd6wVEuzZbdy zVgA= X-Google-Smtp-Source: AGHT+IGX4KunhRdM2W849kKN4U/oIfTk9Rslx/McIR9jCzUmlzGLmpW6+Ib5cr2rSDw1vcO2OU8IrQ== X-Received: by 2002:a17:903:2449:b0:1d6:9bad:ff88 with SMTP id l9-20020a170903244900b001d69badff88mr5100660pls.110.1706571070891; Mon, 29 Jan 2024 15:31:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 10/33] target/i386: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:20 +1000 Message-Id: <20240129233043.34558-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571187855100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/cpu.h | 13 ++++++------- target/i386/cpu.c | 10 ++++++++++ 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7f0786e8b9..62bdb02378 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2296,13 +2296,6 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define MMU_NESTED_IDX 3 #define MMU_PHYS_IDX 4 =20 -static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) -{ - return (env->hflags & HF_CPL_MASK) =3D=3D 3 ? MMU_USER_IDX : - (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) - ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; -} - static inline int cpu_mmu_index_kernel(CPUX86State *env) { return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : @@ -2322,6 +2315,12 @@ static inline int cpu_mmu_index_kernel(CPUX86State *= env) #include "hw/i386/apic.h" #endif =20 +int x86_cpu_mmu_index(CPUState *cs, bool ifetch); +static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) +{ + return x86_cpu_mmu_index(env_cpu(env), ifetch); +} + static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 03822d9ba8..280bcb7d00 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7720,6 +7720,15 @@ static bool x86_cpu_has_work(CPUState *cs) return x86_cpu_pending_interrupt(cs, cs->interrupt_request) !=3D 0; } =20 +int x86_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUX86State *env =3D cpu_env(cs); + + return (env->hflags & HF_CPL_MASK) =3D=3D 3 ? MMU_USER_IDX : + (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) + ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; +} + static void x86_disas_set_info(CPUState *cs, disassemble_info *info) { X86CPU *cpu =3D X86_CPU(cs); @@ -7954,6 +7963,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->class_by_name =3D x86_cpu_class_by_name; cc->parse_features =3D x86_cpu_parse_featurestr; cc->has_work =3D x86_cpu_has_work; + cc->mmu_index =3D x86_cpu_mmu_index; cc->dump_state =3D x86_cpu_dump_state; cc->set_pc =3D x86_cpu_set_pc; cc->get_pc =3D x86_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571399; cv=none; d=zohomail.com; s=zohoarc; b=B+D6ws4dq7MQQJBU7Jk7Q7kljaCRuIdez9A9IrQCgw3o2YjFvbxqMZcL+eyT53pg6mh2tJjxU09KL+Fa2aoqxqYBDvhS7UCO6GyTGlRmRI2pdD0v9tp9PlNEcDkKA2KwArEVzFbODx4yMI6yj09cz/8GBXM5LicwO48vOlh5RU0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571399; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=O5n462vNeMjlBZwwraV55qst2NUkc1xnzZuaJY63KTM=; b=TmI57FREJplrNN9QPC02NEyebCPlFt6oGiTMvs36qIrcsSgDS4RSmarfF+luWJ/7AHqU7FQMhmp97LpjwcAGfq8sDRxqnF6+QEV5GFmt8r+AvCfIBOVPIOTGu/oCwYQfa8ZrGYFaBPBuKA5OkopjQbrOCMSbL2eLjeSdMp4Jun0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706571399622996.675477896145; Mon, 29 Jan 2024 15:36:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUb68-0005hT-A9; Mon, 29 Jan 2024 18:31:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUb5w-0005Uo-Dl for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:22 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUb5u-00054B-RB for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:16 -0500 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-29036dc3a63so1642227a91.3 for ; Mon, 29 Jan 2024 15:31:14 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571073; x=1707175873; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=O5n462vNeMjlBZwwraV55qst2NUkc1xnzZuaJY63KTM=; b=RkQ5cQuyy56crGo4k22EZvL1meEcWr52uSbq4/yI5URm1hu2uYo6RemwldGemnFzOb V7R9WrqgeEFKpVwNyUTKD/d06/bGob3H/4wmUEQyL/mnvZa06rPgAh/520uS1F2c8rWn Ll0D0ayrriAGP14lyD4u25FdJAdN2dsxaaptQvSsZO59gu1kb5KHt3UOjj/DDebYSwD8 P1yYbO17wjmPD3aXjvNyVT3IcJU1lwbT6Mm2cx9TKvDR7mR/dLygvQ7563BUokk8DfUx tfXOzQ4kkSCmR/wURFKKO17UUHnTFjUJI/XT9rqz2qrGCv1Y7vrj3EWKbO4FlIVLUfhY o/Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571073; x=1707175873; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571400183100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/loongarch/cpu.h | 6 ++---- target/loongarch/cpu.c | 11 +++++++++++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 0fa5e0ca93..5dfcfeb3a4 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -408,15 +408,13 @@ struct LoongArchCPUClass { #define MMU_IDX_USER MMU_PLV_USER #define MMU_IDX_DA 4 =20 +int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return MMU_IDX_USER; #else - if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { - return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); - } - return MMU_IDX_DA; + return loongarch_cpu_mmu_index(env_cpu(env), ifetch); #endif } =20 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index fb8dde7def..cbecc63213 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -375,6 +375,16 @@ static bool loongarch_cpu_has_work(CPUState *cs) #endif } =20 +int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPULoongArchState *env =3D cpu_env(cs); + + if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { + return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); + } + return MMU_IDX_DA; +} + static void loongarch_la464_initfn(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); @@ -779,6 +789,7 @@ static void loongarch_cpu_class_init(ObjectClass *c, vo= id *data) =20 cc->class_by_name =3D loongarch_cpu_class_by_name; cc->has_work =3D loongarch_cpu_has_work; + cc->mmu_index =3D loongarch_cpu_mmu_index; cc->dump_state =3D loongarch_cpu_dump_state; cc->set_pc =3D loongarch_cpu_set_pc; cc->get_pc =3D loongarch_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571125; cv=none; d=zohomail.com; s=zohoarc; b=fi3bg5yhVzZB2rOFi4+WlzaQASfMMAl4cu3nLApkQjxWNQIvryair961JbeOI03xM7rls1WDu374Lgblww5M9pV8KmkYCBCkpQzQ/jwPQP86IwnLEkazBDny2sSx0LaXzvhbe6PaljcyNC8vym31sUMuIu0SHf2hlEXcgGPXhdA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571125; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571075; x=1707175875; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i4Nk7Fr5V+E+EQgUKIfA2DtzakJRYTC/OjGjeS9cqxs=; b=ChLcQ+therHAPTHU8q1T/a/OQWcNjDVN/jyIfLb/dpEIPf+7Cd9ngCoArM/8Zs/lbg 6NakEccwXyBaY6lpZACklkapZGPBpLuwqtAhUozbIUif/HAoGpyGLB2FNK+E/JTL1nKe 21TumR4sd5u/H1w+17XSLj2ybccYffoyJNiPItXOvae9kMDQ9EzQWkksd4hwuuwtkFLZ Pp6PKU+nZP2JptQVkuacP/SPh+Qt6vHw7laRDXYXxpBCNfmvh4tqDWiy9usPl9Ht8OaN tIE2l3wFWNdYYnpOJ34MuXnlon/0TV+3RGzvs8QGgSFPGAPMegyNypvVCvVZq0dFDXXG 7C7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571075; x=1707175875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i4Nk7Fr5V+E+EQgUKIfA2DtzakJRYTC/OjGjeS9cqxs=; b=kRUF+RqLzhOf9RmdasQey8tKIKq2TObNlBa/Yo5Gv8glL0cIzUaY147LSGQr8kjbjs rPE8EkMkiekyFa2reMNjnnF9/HbmJJNltBco7DO2Alw2FId/EgpmsK4Po9V2Q3SCGuxr AVcWN5Lf25XSiMtj5qhSCStj8i+z3u+012Wyz6DGkmjz3sH8jSu8pxh6xYgJHIzb0/LJ fEF5QZbGgeHg/kokT91bVfiIsgQWmkZrzqdt82TX6wul90QQdSaB/NDNv3IOxBQa0A+1 MU+o5t2zBOqVURdQkEYNEc+J6g2XOKxarG7hQp49uHkayTzipqFMclX/gmreuby4ytat KfDQ== X-Gm-Message-State: AOJu0YyStuRdqYpBoJxj/c91WDGztrEeTz58YD2Mzb5Viv1h4aAsgN4o zMaqUt9CTVoQhFw1rJlxJmyudbcx1o8Xpl+tIo9EhxaCWQnKK4tZqnTjdjObyKFI7r03JOcqE0T dj/U= X-Google-Smtp-Source: AGHT+IEt+GQjSHnTK1lS6AoJLHBt3Vvc+uQaXlDE1FUa2Fbb0aUKdMH+2BgGBmPqg1+kv3lFYlTbvA== X-Received: by 2002:a17:902:c115:b0:1d8:efa9:3b61 with SMTP id 21-20020a170902c11500b001d8efa93b61mr2081216pli.36.1706571075675; Mon, 29 Jan 2024 15:31:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 12/33] target/loongarch: Rename MMU_IDX_* Date: Tue, 30 Jan 2024 09:30:22 +1000 Message-Id: <20240129233043.34558-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571125706100002 Content-Type: text/plain; charset="utf-8" The expected form is MMU_FOO_IDX, not MMU_IDX_FOO. Rename to match generic code. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/loongarch/cpu.h | 8 ++++---- target/loongarch/cpu.c | 2 +- target/loongarch/tcg/tlb_helper.c | 4 ++-- target/loongarch/tcg/translate.c | 2 +- target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 5dfcfeb3a4..47fd110e81 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -404,15 +404,15 @@ struct LoongArchCPUClass { */ #define MMU_PLV_KERNEL 0 #define MMU_PLV_USER 3 -#define MMU_IDX_KERNEL MMU_PLV_KERNEL -#define MMU_IDX_USER MMU_PLV_USER -#define MMU_IDX_DA 4 +#define MMU_KERNEL_IDX MMU_PLV_KERNEL +#define MMU_USER_IDX MMU_PLV_USER +#define MMU_DA_IDX 4 =20 int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY - return MMU_IDX_USER; + return MMU_USER_IDX; #else return loongarch_cpu_mmu_index(env_cpu(env), ifetch); #endif diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index cbecc63213..139acfe373 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -382,7 +382,7 @@ int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); } - return MMU_IDX_DA; + return MMU_DA_IDX; } =20 static void loongarch_la464_initfn(Object *obj) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 449043c68b..65ffbef08e 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -188,8 +188,8 @@ static int get_physical_address(CPULoongArchState *env,= hwaddr *physical, int *prot, target_ulong address, MMUAccessType access_type, int mmu_idx) { - int user_mode =3D mmu_idx =3D=3D MMU_IDX_USER; - int kernel_mode =3D mmu_idx =3D=3D MMU_IDX_KERNEL; + int user_mode =3D mmu_idx =3D=3D MMU_USER_IDX; + int kernel_mode =3D mmu_idx =3D=3D MMU_KERNEL_IDX; uint32_t plv, base_c, base_v; int64_t addr_high; uint8_t da =3D FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA); diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/transl= ate.c index 235515c629..58674cb268 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -125,7 +125,7 @@ static void loongarch_tr_init_disas_context(DisasContex= tBase *dcbase, if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) { ctx->mem_idx =3D ctx->plv; } else { - ctx->mem_idx =3D MMU_IDX_DA; + ctx->mem_idx =3D MMU_DA_IDX; } =20 /* Bound the number of insns to execute to those left on the page. */ diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/targe= t/loongarch/tcg/insn_trans/trans_privileged.c.inc index 01d457212b..7e4ec93edb 100644 --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc @@ -323,7 +323,7 @@ TRANS(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr= _d) =20 static void check_mmu_idx(DisasContext *ctx) { - if (ctx->mem_idx !=3D MMU_IDX_DA) { + if (ctx->mem_idx !=3D MMU_DA_IDX) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4); 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571078; x=1707175878; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/OUWFZBgzvOfgT4Ih6uQ0qaIP/PxSyaD+oSDUXr46+M=; b=uj1gZWoRXsILIVRJ+S2Tm28eMPZYBO6N5muLfVMuUDzhqg5qIys5IxNHhsVOndprg0 /RpsKyVSeRPDzey//XAxeK1wAGi4H2bs0F5xnSpYVdLRDekrZgePPvWwBCiU/8LKKvnl gmp1fMFmLMxqaUJVgmfQRw3ytWOKSmT4aFlaTHFsVDSSIV5KerNoWMqeY5gtMLVMcHsx 09XlOne+SB3yXUAczn+1ROg3MYC2IkDT1YArEJhowRyH58k8ckt8j/TpW3OvSGbfV3Vq oBE83NMa5HnqYdx3mdZf4v422vsgs/OB7vYDmSmTakDMHiPe15bI3aHtyS4qnz7ehcCN N4zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571078; x=1707175878; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/OUWFZBgzvOfgT4Ih6uQ0qaIP/PxSyaD+oSDUXr46+M=; b=iB8L/W50rBD0o/OPobyjLE5bg+8+MupNYrJze0rPKs91p/Ruqs3SMpzagcHKFTE0Yp T2ypS5G4EofV7jPbsjZdI7OeZzUM8ziNBDHo0XbkBylfZk7GYmyy4u5WlfDK5B+jNG5e ku/uTcEV1k/IaB0uiIrMBE677BuMfKtacwgYXToAauh2WGV7AHTLnwmToAwm5Olw47jn 4uc9+Q9FbumwtMQVWci0n0FvUQZ+woilnRrYCiD6ZQtNTqIZvFHkckmW+CBfHDwQ25Yc IBpruJvGhZP8E9gzOILlmScBpEYFxzWIT6+bltvrQeKhSeKOmYzTEtj7jpMdChAAo1+f ymOA== X-Gm-Message-State: AOJu0YyWXC7e4YpDPy0BgGCWYLnKSLYzVSO4wUgGe75fP4M424ijkIku MbpMRXovPaBfyb9Bkozoj5aePBK5UBMwcZtQMpTFts+mbYhGDpJCv/wTUlV/pO7v7saDsPDlSyX 00Ic= X-Google-Smtp-Source: AGHT+IHlMdn7NiF3GUqkHMfKLb2OsyB1+8hlmszuwXHi1t/YNEEpKeL4pi9ONF5q0Nyw+NvUS5ZCDQ== X-Received: by 2002:a17:903:2442:b0:1d7:490b:2c01 with SMTP id l2-20020a170903244200b001d7490b2c01mr6770981pls.8.1706571077951; Mon, 29 Jan 2024 15:31:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 13/33] target/m68k: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:23 +1000 Message-Id: <20240129233043.34558-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571384143100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/m68k/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 44000f5869..8a8392e694 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -56,6 +56,11 @@ static bool m68k_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } =20 +static int m68k_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return cpu_env(cs)->sr & SR_S ? MMU_KERNEL_IDX : MMU_USER_IDX; +} + static void m68k_set_feature(CPUM68KState *env, int feature) { env->features |=3D BIT_ULL(feature); @@ -551,6 +556,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) =20 cc->class_by_name =3D m68k_cpu_class_by_name; cc->has_work =3D m68k_cpu_has_work; + cc->mmu_index =3D m68k_cpu_mmu_index; cc->dump_state =3D m68k_cpu_dump_state; cc->set_pc =3D m68k_cpu_set_pc; cc->get_pc =3D m68k_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571588; cv=none; d=zohomail.com; s=zohoarc; b=RLzSWAK2+82aW0dle11Znatajj6m0HVH3kH9pB/tVsduLswKNhD8bypRBGKj7KRQ8/1jfAwHZ5/3rD8PKr+K/UUYPKownfmmuGcX1itf19DNu2OquFcXUo32l6usyJ+EOrD1SoXn8lrw8fQf8/JI0fh2HqAA4KykJ/AcQE6X5EI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571588; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zRmglClgoVHSDx5STL3QfC7K3ahzi83m4KSgoX1Lwpc=; b=Uy4tvlMm9n8zOtWQVoT00R74xICtHxrn9O8mc1S5OGfP+L6uTVuXx19Rk0xucNEVgUDlZFIeGglK4gHUVtYYqJksFDVxeKmHnDnDlf5RyoBAfNuENUXVUgild/FvXETx3yOHOfxk0OnEr1snqnb3LJMUW0xQ/nERe8O0Dch5tW8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706571588596549.9207411256592; Mon, 29 Jan 2024 15:39:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUb6D-0005r4-PN; Mon, 29 Jan 2024 18:31:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUb64-0005av-7F for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:24 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUb62-00054Y-33 for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:23 -0500 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1d746856d85so16089695ad.0 for ; Mon, 29 Jan 2024 15:31:21 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571590606100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/microblaze/cpu.h | 13 ++----------- target/microblaze/cpu.c | 18 +++++++++++++++++- 2 files changed, 19 insertions(+), 12 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b5374365f5..90ab796de9 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -434,19 +434,10 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr p= hysaddr, vaddr addr, MemTxResult response, uintptr_t retaddr); #endif =20 +int mb_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) { - MicroBlazeCPU *cpu =3D env_archcpu(env); - - /* Are we in nommu mode?. */ - if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { - return MMU_NOMMU_IDX; - } - - if (env->msr & MSR_UM) { - return MMU_USER_IDX; - } - return MMU_KERNEL_IDX; + return mb_cpu_mmu_index(env_cpu(env), ifetch); } =20 #ifndef CONFIG_USER_ONLY diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 2318ad7013..6dad11905b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -118,6 +118,22 @@ static bool mb_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); } =20 +int mb_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUMBState *env =3D cpu_env(cs); + MicroBlazeCPU *cpu =3D env_archcpu(env); + + /* Are we in nommu mode?. */ + if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { + return MMU_NOMMU_IDX; + } + + if (env->msr & MSR_UM) { + return MMU_USER_IDX; + } + return MMU_KERNEL_IDX; +} + #ifndef CONFIG_USER_ONLY static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) { @@ -415,7 +431,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 cc->class_by_name =3D mb_cpu_class_by_name; cc->has_work =3D mb_cpu_has_work; - + cc->mmu_index =3D mb_cpu_mmu_index; cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; cc->get_pc =3D mb_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571325; cv=none; d=zohomail.com; s=zohoarc; b=MWIhVZo9QS9+4NM33kD4vskK/nM9Un7Sz0B8i16gHbCFFDeULRyOfmD6D3rJA80nvtMmuZ5MKbH32dacPzqVJNRrrGF0SRoP5MC4eL3V5s5TRGI0SfSXwU1m7sNTGJjsmbkXyYbmDn+l9xEjA+cLjYJ4NDMPYBHuuYzhvO4MLlo= ARC-Message-Signature: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571082; x=1707175882; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cX9p1w8gwSjbvchi0L5D4HF7R4GEOnc6YSNW0pomVF4=; b=rUkNe65LqnioJuFclhbz/U5jKKK+T7A/XFRzHEEkhGKRFueONs0Z8Mo55djOZXjaHV vtnuxWq0J69k+St73ICfcixk6JkNQmcRjP3hK6m873vS+55bMFYuaTm7pvNq4ipHOieT dRW7nUvma8/HuhP9xkGZ2z3HeI555saulk+wueX70BJlDmfZj8a/nQEr2FEEkSSKLLGI NOJ58KOzyZCFkvixAr1xdPGYsJUH1IVWSVoTDQVbxmdiIr6dOr0gdVd4m+A8xRDKRkN1 +FzzZB6ymejjmPRugpO6qOkZFugAXIFrKJeRVF3nZYjqWNid7EnCJV9j0Ds/Mg5YoOUx JFTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571082; x=1707175882; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cX9p1w8gwSjbvchi0L5D4HF7R4GEOnc6YSNW0pomVF4=; b=wmsCq+i9T1KsB3FY+OfFt1Uca1ldo4GyfmdC6FlXknP1bufcLMzoFkvdf0RnQ9ngm7 VvX3ifzLTqHeeXwQEquwTyg2nOjITpc1uiXhaljpRQYcKqqNkiPSpg9t3sza2FfDNK5a xgd8wtxrXl3ktGOqTrQCfTuyFgR12T7ACpxYAXqs0zlp/t1vyAdlqgnwUKwq7PifbTnY UydvYtce4QErjRA/pE6Nqs+wUZRBVJB1GnoYIrg7LKd//AfSGyPKgIZejXbOSCj0KkCM vOWWWcAfhy9CjptYbpc4V19YVt6mvR3zQc7Zvekog8ucEiUKgPaTQmcNHnYIndzopadQ hqWQ== X-Gm-Message-State: AOJu0YwqSQs8FqnIRjC1UYYLQ1So6oS8qQw1ELkIV5SnKjN71bBpAK7u PNGFxqZQpZ6w0GsYN+EMo/zIV5acQTb44d+mnWrAgE9ge4m3+27IBlMSrIp9MuIZwQaUUBusNC3 Ftlo= X-Google-Smtp-Source: AGHT+IGlXWUbzVf01GsoCXgRD0LtsZf7FvDzrPLjU3x1SLrtPh7pBHiuG3sfy8qARmrS9JsRc4gM6g== X-Received: by 2002:a17:903:a90:b0:1d7:3192:de38 with SMTP id mo16-20020a1709030a9000b001d73192de38mr3697696plb.69.1706571082505; Mon, 29 Jan 2024 15:31:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 15/33] target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill Date: Tue, 30 Jan 2024 09:30:25 +1000 Message-Id: <20240129233043.34558-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571326143100007 Content-Type: text/plain; charset="utf-8" Rather than adjust env->hflags so that the value computed by cpu_mmu_index() changes, compute the mmu_idx that we want directly and pass it down. Introduce symbolic constants for MMU_{KERNEL,ERL}_IDX. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.h | 4 +++- target/mips/tcg/sysemu/tlb_helper.c | 32 ++++++++++++----------------- 2 files changed, 16 insertions(+), 20 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1163a71f3c..3ba8dccd2d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1242,12 +1242,14 @@ uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState = *env); * MMU modes definitions. We carefully match the indices with our * hflags layout. */ +#define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 2 +#define MMU_ERL_IDX 3 =20 static inline int hflags_mmu_index(uint32_t hflags) { if (hflags & MIPS_HFLAG_ERL) { - return 3; /* ERL */ + return MMU_ERL_IDX; } else { return hflags & MIPS_HFLAG_KSU; } diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index 4ede904800..b715449114 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -623,7 +623,7 @@ static uint64_t get_tlb_entry_layout(CPUMIPSState *env,= uint64_t entry, static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, int directory_index, bool *huge_page, bool *hgpg_directory_hit, uint64_t *pw_entrylo0, uint64_t *pw_entrylo1, - unsigned directory_shift, unsigned leaf_shift) + unsigned directory_shift, unsigned leaf_shift, int ptw_mmu_idx) { int dph =3D (env->CP0_PWCtl >> CP0PC_DPH) & 0x1; int psn =3D (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F; @@ -638,8 +638,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *= vaddr, uint64_t w =3D 0; =20 if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D - TLBRET_MATCH) { + ptw_mmu_idx) !=3D TLBRET_MATCH) { /* wrong base address */ return 0; } @@ -666,8 +665,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *= vaddr, *pw_entrylo0 =3D entry; } if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_= LOAD, - cpu_mmu_index(env, false)) !=3D - TLBRET_MATCH) { + ptw_mmu_idx) !=3D TLBRET_MATCH) { return 0; } if (!get_pte(env, vaddr2, leafentry_size, &entry)) { @@ -690,7 +688,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *= vaddr, } =20 static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, - int mmu_idx) + int ptw_mmu_idx) { int gdw =3D (env->CP0_PWSize >> CP0PS_GDW) & 0x3F; int udw =3D (env->CP0_PWSize >> CP0PS_UDW) & 0x3F; @@ -776,7 +774,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, v= addr address, vaddr |=3D goffset; switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhi= t, &pw_entrylo0, &pw_entrylo1, - directory_shift, leaf_shift)) + directory_shift, leaf_shift, ptw_mmu_idx)) { case 0: return false; @@ -793,7 +791,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, v= addr address, vaddr |=3D uoffset; switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhi= t, &pw_entrylo0, &pw_entrylo1, - directory_shift, leaf_shift)) + directory_shift, leaf_shift, ptw_mmu_idx)) { case 0: return false; @@ -810,7 +808,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, v= addr address, vaddr |=3D moffset; switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhi= t, &pw_entrylo0, &pw_entrylo1, - directory_shift, leaf_shift)) + directory_shift, leaf_shift, ptw_mmu_idx)) { case 0: return false; @@ -825,8 +823,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, v= addr address, /* Leaf Level Page Table - First half of PTE pair */ vaddr |=3D ptoffset0; if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D - TLBRET_MATCH) { + ptw_mmu_idx) !=3D TLBRET_MATCH) { return false; } if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { @@ -838,8 +835,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, v= addr address, /* Leaf Level Page Table - Second half of PTE pair */ vaddr |=3D ptoffset1; if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D - TLBRET_MATCH) { + ptw_mmu_idx) !=3D TLBRET_MATCH) { return false; } if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { @@ -944,12 +940,10 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, * Memory reads during hardware page table walking are performed * as if they were kernel-mode load instructions. */ - int mode =3D (env->hflags & MIPS_HFLAG_KSU); - bool ret_walker; - env->hflags &=3D ~MIPS_HFLAG_KSU; - ret_walker =3D page_table_walk_refill(env, address, mmu_idx); - env->hflags |=3D mode; - if (ret_walker) { + int ptw_mmu_idx =3D (env->hflags & MIPS_HFLAG_ERL ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571291966100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.h | 7 ++++++- target/mips/sysemu/physaddr.c | 2 +- target/mips/tcg/msa_helper.c | 10 +++++----- target/mips/tcg/sysemu/cp0_helper.c | 2 +- target/mips/tcg/sysemu/special_helper.c | 2 +- target/mips/tcg/sysemu/tlb_helper.c | 2 +- 6 files changed, 15 insertions(+), 10 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3ba8dccd2d..4c15e76781 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1255,11 +1255,16 @@ static inline int hflags_mmu_index(uint32_t hflags) } } =20 -static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) +static inline int mips_env_mmu_index(CPUMIPSState *env) { return hflags_mmu_index(env->hflags); } =20 +static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) +{ + return mips_env_mmu_index(env); +} + #include "exec/cpu-all.h" =20 /* Exceptions */ diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c index 05990aa5bb..13c8bc8f47 100644 --- a/target/mips/sysemu/physaddr.c +++ b/target/mips/sysemu/physaddr.c @@ -236,7 +236,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) int prot; =20 if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D 0) { + mips_env_mmu_index(env)) !=3D 0) { return -1; } return phys_addr; diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 7a8dbada5d..d2181763e7 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8214,7 +8214,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_= t df, uint32_t wd, #if !defined(CONFIG_USER_ONLY) #define MEMOP_IDX(DF) \ MemOpIdx oi =3D make_memop_idx(MO_TE | DF | MO_UNALN, \ - cpu_mmu_index(env, false)); + mips_env_mmu_index(env)); #else #define MEMOP_IDX(DF) #endif @@ -8323,7 +8323,7 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D mips_env_mmu_index(env); uintptr_t ra =3D GETPC(); =20 ensure_writable_pages(env, addr, mmu_idx, ra); @@ -8337,7 +8337,7 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D mips_env_mmu_index(env); uintptr_t ra =3D GETPC(); uint64_t d0, d1; =20 @@ -8358,7 +8358,7 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D mips_env_mmu_index(env); uintptr_t ra =3D GETPC(); uint64_t d0, d1; =20 @@ -8379,7 +8379,7 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D mips_env_mmu_index(env); uintptr_t ra =3D GETPC(); =20 ensure_writable_pages(env, addr, mmu_idx, GETPC()); diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/c= p0_helper.c index cc545aed9c..62f6fb4bf6 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -1202,7 +1202,7 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulo= ng arg1) old, old & env->CP0_Cause & CP0Ca_IP_mask, val, val & env->CP0_Cause & CP0Ca_IP_mask, env->CP0_Cause); - switch (cpu_mmu_index(env, false)) { + switch (mips_env_mmu_index(env)) { case 3: qemu_log(", ERL\n"); break; diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/syse= mu/special_helper.c index 93276f789d..518d3fbc34 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -68,7 +68,7 @@ static void debug_post_eret(CPUMIPSState *env) if (env->hflags & MIPS_HFLAG_DM) { qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); } - switch (cpu_mmu_index(env, false)) { + switch (mips_env_mmu_index(env)) { case 3: qemu_log(", ERL\n"); break; diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index b715449114..cdae42ffdd 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -973,7 +973,7 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, ta= rget_ulong address, =20 /* data access */ ret =3D get_physical_address(env, &physical, &prot, address, access_ty= pe, - cpu_mmu_index(env, false)); + mips_env_mmu_index(env)); if (ret =3D=3D TLBRET_MATCH) { return physical; } --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571593; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571594624100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index df544ab39b..d644adbc77 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -182,6 +182,11 @@ static bool mips_cpu_has_work(CPUState *cs) return has_work; } =20 +static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) +{ + return mips_env_mmu_index(cpu_env(cs)); +} + #include "cpu-defs.c.inc" =20 static void mips_cpu_reset_hold(Object *obj) @@ -579,6 +584,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) =20 cc->class_by_name =3D mips_cpu_class_by_name; cc->has_work =3D mips_cpu_has_work; + cc->mmu_index =3D mips_cpu_mmu_index; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; cc->get_pc =3D mips_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571580; cv=none; d=zohomail.com; s=zohoarc; b=JFLtDO1vmTr0puO5jNfPaOHogRyH381qsK+acT45K9EBHQHaWX2ocgQyD/4s0PPgdLPJm2OF29s58zg20Sre/gjQFzFwWNFQFjGUAmawdrzGRmQ1D6y/jKaLKLFyF4kGj8J13/niW/zPMlHoC7hko+33gBvPViYFxP1+HKCWAUI= ARC-Message-Signature: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571089; x=1707175889; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YucELH6fbErp+6umx07QFC7pYx6ueR6ifc1TTKY+quw=; b=Xd1j6lJmmNj4DOrDmW7nywRSnoxJ6Zl+FwrmYAoE5hsGzZKNjiyjaZR+5IEGGOxo+3 FgXWr+tcfJqIQ2vs+woBOksP1dslKLj3u4l7bS7gjX91Be2YlRHDs2bGgJgictM8Qxj+ dbqfMtBEfoXmdJOAcvJWwoFbs4cjnqv8y1ofypeHEXaCFh4EsCqB7UPkHhLYTxFUoyXa CU7qpaLUP3EFSp4zInVid3wj7zFthWtz6MsMAmbmv1GX8Hzg8/Y5rRFkpvlXdfdeqspM 6UG5hZ3Laun/fcNp78Cjo7jNLDhzyNhMb1k2twXVJBlsIZowkYYGNWmKvLxUJ9RUuHGp qX3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571089; x=1707175889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YucELH6fbErp+6umx07QFC7pYx6ueR6ifc1TTKY+quw=; b=n+gAY0H790DltBIwBxktIff71lOAwkewOQqtKek+a9UuHcTzaM+R01vQ0lH7bdHEgr Ipdt9CBrWbfTDs7P8S+uneGt2/oActIaiSNTiK0Dr3oPP+K8B6IL94kQE6FWRApCgQcq EoZ4/ck3vehGVbr1YcSnlfsNYU4/UAUPwwwfw6D/fOPn+1mOxyyg307dIG2exSV4SP6q qQpsRH4raAaObYjooCNCJpCTM46xyUBH+FnrdQEnFRyf0zo3ULgmzV6KPaWUUxmYQhKC JwJCGyXHl71u24LB6homymt2BGuy2PuehI4MMRWREJ7qCr15u5fsmH0MOcKVwX4+GCDo 5Rtg== X-Gm-Message-State: AOJu0YxEjTzwoaB1Rl3g5BVvHtaHpSwB1su3yyGytxkofyMC1jetjyJ2 2k5h0Jz7Di2IxZtS9wkuCr6Ec0yCjlG+QVJMIYdrKDLewkCCtQqNbcwLJ3xdADBOVotKnnPKRl+ 9RPo= X-Google-Smtp-Source: AGHT+IH5IDqnUWaUif2N5yUmkdlgjzY0Q6qtGXX1Ysho1vm8SpPiLEp8ttnWEZvzI9aMq8QHSf7okw== X-Received: by 2002:a17:90a:a581:b0:28f:f19d:e43 with SMTP id b1-20020a17090aa58100b0028ff19d0e43mr4253528pjq.3.1706571089376; Mon, 29 Jan 2024 15:31:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 18/33] target/nios2: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:28 +1000 Message-Id: <20240129233043.34558-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571582618100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/nios2/cpu.h | 12 ++++++------ target/nios2/cpu.c | 7 +++++++ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2d79b5b298..9965ff74c1 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -270,12 +270,6 @@ void do_nios2_semihosting(CPUNios2State *env); #define MMU_SUPERVISOR_IDX 0 #define MMU_USER_IDX 1 =20 -static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) -{ - return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : - MMU_SUPERVISOR_IDX; -} - #ifndef CONFIG_USER_ONLY hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -292,6 +286,12 @@ FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS =3D=3D 0. */ FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */ FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 =3D=3D 0. */ =20 +int nios2_cpu_mmu_index(CPUState *cs, bool ifetch); +static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) +{ + return nios2_cpu_mmu_index(env_cpu(env), ifetch); +} + static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 596c0c5617..e42885997e 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -57,6 +57,12 @@ static bool nios2_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } =20 +int nios2_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return (cpu_env(cs)->ctrl[CR_STATUS] & CR_STATUS_U + ? MMU_USER_IDX : MMU_SUPERVISOR_IDX); +} + static void nios2_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); @@ -381,6 +387,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D nios2_cpu_class_by_name; cc->has_work =3D nios2_cpu_has_work; + cc->mmu_index =3D nios2_cpu_mmu_index; cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; cc->get_pc =3D nios2_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571204; cv=none; d=zohomail.com; s=zohoarc; b=EI6wyaj+4rDYNZxaOn54GGgUZpkLSyhCub8YsYwLigeivKVgdY41tg3NUMNFZObTJddG7dMsnLoVemJG4epdodSg4bw7l1NN51rcAiuhyw8VgNrW+h/X2P0Rvtr8a+KGsauZm/JEO+uovHX493e7iHAkJvOTWTwb2Yqg+1NkwU8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571204; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=KeckyFuoEvdgwHDKZRRirlX+WDs+LbKrZFrG7XL0TJk=; b=GunIoWFQzMrVsGEQFA98ZHfzP6AR3uxOuTNOrl3/w3UravTKpNeoU+jvW0kTJR0Fz7rgS+ao8A6p3Gx8UHWnPXqewlO+YhMac/T88EKmtkdASsokqNO2MMEX2d6lIbfpbU18m3VmGZVilhbR3idcJPpo0z+YG5CPiftUA4HsJLw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706571204322952.6280836515856; Mon, 29 Jan 2024 15:33:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUb6H-0005uj-CB; Mon, 29 Jan 2024 18:31:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUb6E-0005sM-Ns for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:34 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUb6D-00056h-1f for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:34 -0500 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1d76671e5a4so24152605ad.0 for ; Mon, 29 Jan 2024 15:31:32 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571091; x=1707175891; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KeckyFuoEvdgwHDKZRRirlX+WDs+LbKrZFrG7XL0TJk=; b=xnik9OU4u37UwQV2jLj+YnG19G2k9IPAh46scxUfAa0icHDEO5vpdue/MCjYKBSCXn RUM7KflzOP513Wn1gSJgGhSxE/ylNYpaf4lDIwEKVG1tDkrWhP/X8h155kWWlhVm8hwA +KwMHctcnMHzidDKN/eU7sbuny+Sc4L5Y0wZuoIF38QAdhrnl41XuP8lPfnz+cvKg3ko P6Ab8bGJQ40toNpFoOH/hxPiMdWCSw08Uyphb+wurcCJCPGBjzzgvCTtjIcCTOHNmsI5 K2mQ7+H8NyabT0O+FVe+/ku3DQ1UGkCHspgIs4UwB8nNX74We9ebXibb4RaErsvRDfb3 TEgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571091; x=1707175891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KeckyFuoEvdgwHDKZRRirlX+WDs+LbKrZFrG7XL0TJk=; b=FipGBuKZmN6KyHhw3EkdEAAptfyJ6qM/OBxEnTmDY18iyeaaAovGyFKwVqo7vwnY1+ 2oJ5248LSQHNgzkInDoEgUdbAtp0P+CVjdl7lMxLNWT/lCne+hZiO7PtagqcktbdZYey oCtCIBcWCGiMETnb0WN0gp2CXZ8KtydiCQ3WjzzLvwt1Xvqs1Qn7VUNVGCRpQWqho5Fy JKseqxklZzxASL+SLtmtuX9NxkwQrtesxXr6XP8DEXM854oi0OGyYDaxrmdd2vASodm2 453ji/eAg0ywpNcWE3y/W7rTqqtBDpD9+TaYOvIZp2+KyEW0JS8MzkqQiEpJVPOePGj0 keDA== X-Gm-Message-State: AOJu0Yzu9fBPnVbM7fT6Nb4CDFypilLRPYxXyu4RlHTl32z2mfaQL21G tbjEW8v1NHDTdaz9YPfvEAGyxIzTmAHDK2u6j06wm0ukSIgdLiPxMnQmp0nIvkDd1O1PqfsoWfK hzqc= X-Google-Smtp-Source: AGHT+IEcf1hxchPld14Dmkd+CXvljYK7qCOR8zD6SErI6SzjI8olt+mXscuftIKFNsYUFYzd7qXnZA== X-Received: by 2002:a17:902:6b46:b0:1d7:5601:9fb2 with SMTP id g6-20020a1709026b4600b001d756019fb2mr5324087plt.21.1706571091631; Mon, 29 Jan 2024 15:31:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 19/33] target/openrisc: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:29 +1000 Message-Id: <20240129233043.34558-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571205748100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/openrisc/cpu.h | 10 ++-------- target/openrisc/cpu.c | 13 +++++++++++++ 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b454014ddd..7dbed8d8be 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -361,16 +361,10 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCSt= ate *env, vaddr *pc, | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); } =20 +int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) { - int ret =3D MMU_NOMMU_IDX; /* mmu is disabled */ - - if (env->sr & (ifetch ? SR_IME : SR_DME)) { - /* The mmu is enabled; test supervisor state. */ - ret =3D env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; - } - - return ret; + return openrisc_cpu_mmu_index(env_cpu(env), ifetch); } =20 static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 477d49d4bc..8670152c84 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -68,6 +68,18 @@ static bool openrisc_cpu_has_work(CPUState *cs) CPU_INTERRUPT_TIMER); } =20 +int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUOpenRISCState *env =3D cpu_env(cs); + + if (env->sr & (ifetch ? SR_IME : SR_DME)) { + /* The mmu is enabled; test supervisor state. */ + return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; + } + + return MMU_NOMMU_IDX; /* mmu is disabled */ +} + static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) { info->print_insn =3D print_insn_or1k; @@ -239,6 +251,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) =20 cc->class_by_name =3D openrisc_cpu_class_by_name; cc->has_work =3D openrisc_cpu_has_work; + cc->mmu_index =3D openrisc_cpu_mmu_index; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; cc->get_pc =3D openrisc_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571457; cv=none; d=zohomail.com; s=zohoarc; b=EFr02V2y2P0NSeqs7VExkGFs7ePLpzZ5kVFnv+ifjVmoMnHoCdOo16d0jTCpwjCOqPwoZ1XWkX+POmOWg3VqmtXKaMsNnr7Ojk+KwtbsAs5CL+3b/WqK5rRRRZ6/wlXElTqL4GjuPrI4NYRcQTF+T4rdZ4uYjvvZpJm3OUgd1x0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571457; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rvOQFTMkY9QB65SS7g0QhXugn3UR4E0seouTHChD6V0=; b=OrrOKnNjhAtleZCsS7ag3lk1K7517qI1bdPZbwYWsWRqolZFv+4hU2GKwiIDgRW76L3WV58ngD7XXIR3KV5FWZIrhtT1i1CU5jLrt8l4O59FgK6akVdzQBbsj7JZDf7VHM6X+dd+/Hf/BQgApJmT/BrX41oC6k50RAnGDsnF3yE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706571457846188.1084957471062; Mon, 29 Jan 2024 15:37:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUb6I-0005w6-HO; Mon, 29 Jan 2024 18:31:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUb6H-0005uh-2B for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:37 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUb6F-000576-6L for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:36 -0500 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1d748d43186so16536145ad.0 for ; Mon, 29 Jan 2024 15:31:34 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571094; x=1707175894; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rvOQFTMkY9QB65SS7g0QhXugn3UR4E0seouTHChD6V0=; b=xcnb47P7ZQ+PbKxstvhd7l6+AQmAV+mwf8l0IAKUvvqxfQg737ZnzmRuCMCUQzXIA1 FXSoabViFJsv5SkaufDHoIp+sHCd2PUr8dIe53VIYvVUGnn+0XBXs024WOLIlKiJIkAi GrLT5RY2ilwZ6pAcX0pH+HKkVCXY80JpTgOO/0RgScfoylX9vv0p7NoAcyiObaO+Cjnf mbe/HsTW8neJRpQgS/d3QDoi1d1akTRGNe8A+2s+NUKEvR05R8ZDXfI1nNmZoRwhsy3l VBbbYEzffQ/8SFe//h51cGrEQX7CoFEjY9ZLCtWuPHGgXNRiQMD+ss5hh/BEYoMl2JAt bynw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571094; x=1707175894; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571458348100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/ppc/cpu.h | 7 ++++++- target/ppc/cpu_init.c | 2 +- target/ppc/mem_helper.c | 10 +++++----- target/ppc/mmu_common.c | 4 ++-- 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f8101ffa29..5f4f52aec5 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1624,7 +1624,7 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint3= 2_t val); =20 /* MMU modes definitions */ #define MMU_USER_IDX 0 -static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) +static inline int ppc_env_mmu_index(CPUPPCState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return MMU_USER_IDX; @@ -1633,6 +1633,11 @@ static inline int cpu_mmu_index(CPUPPCState *env, bo= ol ifetch) #endif } =20 +static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) +{ + return ppc_env_mmu_index(env, ifetch); +} + /* Compatibility modes */ #if defined(TARGET_PPC64) bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 23eb5522b6..86c8031765 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7457,7 +7457,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " "%08x iidx %d didx %d\n", env->msr, env->spr[SPR_HID0], env->hflags, - cpu_mmu_index(env, true), cpu_mmu_index(env, false)); + ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, fals= e)); #if !defined(CONFIG_USER_ONLY) if (env->tb_env) { qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index c7535481d6..ea7e8443a8 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -83,7 +83,7 @@ static void *probe_contiguous(CPUPPCState *env, target_ul= ong addr, uint32_t nb, void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg) { uintptr_t raddr =3D GETPC(); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D ppc_env_mmu_index(env, false); void *host =3D probe_contiguous(env, addr, (32 - reg) * 4, MMU_DATA_LOAD, mmu_idx, raddr); =20 @@ -105,7 +105,7 @@ void helper_lmw(CPUPPCState *env, target_ulong addr, ui= nt32_t reg) void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg) { uintptr_t raddr =3D GETPC(); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D ppc_env_mmu_index(env, false); void *host =3D probe_contiguous(env, addr, (32 - reg) * 4, MMU_DATA_STORE, mmu_idx, raddr); =20 @@ -135,7 +135,7 @@ static void do_lsw(CPUPPCState *env, target_ulong addr,= uint32_t nb, return; } =20 - mmu_idx =3D cpu_mmu_index(env, false); + mmu_idx =3D ppc_env_mmu_index(env, false); host =3D probe_contiguous(env, addr, nb, MMU_DATA_LOAD, mmu_idx, raddr= ); =20 if (likely(host)) { @@ -224,7 +224,7 @@ void helper_stsw(CPUPPCState *env, target_ulong addr, u= int32_t nb, return; } =20 - mmu_idx =3D cpu_mmu_index(env, false); + mmu_idx =3D ppc_env_mmu_index(env, false); host =3D probe_contiguous(env, addr, nb, MMU_DATA_STORE, mmu_idx, radd= r); =20 if (likely(host)) { @@ -276,7 +276,7 @@ static void dcbz_common(CPUPPCState *env, target_ulong = addr, target_ulong mask, dcbz_size =3D env->dcache_line_size; uint32_t i; void *haddr; - int mmu_idx =3D epid ? PPC_TLB_EPID_STORE : cpu_mmu_index(env, false); + int mmu_idx =3D epid ? PPC_TLB_EPID_STORE : ppc_env_mmu_index(env, fal= se); =20 #if defined(TARGET_PPC64) /* Check for dcbz vs dcbzl on 970 */ diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 6ca5d12207..751403f1c8 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -1561,9 +1561,9 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) * mapped by code TLBs, so we also try a MMU_INST_FETCH. */ if (ppc_xlate(cpu, addr, MMU_DATA_LOAD, &raddr, &s, &p, - cpu_mmu_index(&cpu->env, false), false) || + ppc_env_mmu_index(&cpu->env, false), false) || ppc_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p, - cpu_mmu_index(&cpu->env, true), false)) { + ppc_env_mmu_index(&cpu->env, true), false)) { return raddr & TARGET_PAGE_MASK; } return -1; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571300; cv=none; d=zohomail.com; s=zohoarc; b=fgnBWavCz2jQR4ot+Nx6WRwUyirXcajZoHMKfZJrJ7EMfmbYBc8SYnmcNwgviHLNcOcch6N+BDFNkAxNw8XvRTX8iVHKNamtjfxKizgKFfnuGNxhtP0RqtiVW5c6A5e98GZH4p2c6aHzIrhfc7k9/XlPr4VVzqEljHFURQ0la3A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571300; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BdVwXO6aZnnqYTNIGGclZOCzzCuGYC0jnGIBlpxlAKQ=; b=m+Om5g/OHWak5Qlr0CR0zTMwxmx7g6aGe+nYKpwTr7XyhaJMGd/fjqmk4bbd3B9O7qz9mvcGtdUgOWwYM98efwP7A3a85NBV+lcjyOgWRAQeJdnF6qhmciJ8zphilcMfh2EoisXQgaLzS+cwEZBM4t2w7Lxh7n6vcGR0BJfudRw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706571300913706.8477133538995; Mon, 29 Jan 2024 15:35:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUb6M-0005wN-AQ; Mon, 29 Jan 2024 18:31:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUb6J-0005w8-GH for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:39 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUb6H-00057o-Jt for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:38 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1d7431e702dso22461315ad.1 for ; Mon, 29 Jan 2024 15:31:37 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571302058100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/ppc/cpu_init.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 86c8031765..9931372a08 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7105,6 +7105,11 @@ static bool ppc_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } =20 +static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return ppc_env_mmu_index(cpu_env(cs), ifetch); +} + static void ppc_cpu_reset_hold(Object *obj) { CPUState *s =3D CPU(obj); @@ -7372,6 +7377,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D ppc_cpu_class_by_name; cc->has_work =3D ppc_cpu_has_work; + cc->mmu_index =3D ppc_cpu_mmu_index; cc->dump_state =3D ppc_cpu_dump_state; cc->set_pc =3D ppc_cpu_set_pc; cc->get_pc =3D ppc_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571236; cv=none; d=zohomail.com; s=zohoarc; b=VEMT+ddClscKq3yueJgoV5TjQbmZGD8toxj0viqqWkVDIzNMkYAeP58gJs7GR8ot0pFtoHH/czZvbYiSx++YSOpehXQ9AlzDAzIup9FvrlAs0MNPYzwQo3KzuWz/FMgmoL1s5p4ZYlFHwZuQsddqbjOdDglT5NspDE2hT2VmqFo= ARC-Message-Signature: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571098; x=1707175898; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w0VyFnxuloTGEbgz18a76FD3rClrdXq5QXu0ykcKSCs=; b=dDu5Fzmg1m1j4TMzpFO5oBgSfAeYER55EUWsAP6AISz4GNTuOXsNLEQOpxBOjxfVeh OFKxHY1Dg9jM8v15c6yBNB4TqCnWHfZOAbkqsu3vQanHP7dydAWjulusS7ejuuEXj+fE tNMwJdjjIEzFzc1lzGc8M9N1tOlOuMLKvj2DNy2U53ahCPvDMiKJ9V0c70/bV3JXH8Hw lQ5hiurd1PYyXBZ0g7sx3HUeW3HlSU34NvcI6OIFnyeadNpNeeWBt3kvFBxBvWP3lkWr cr1kFYBK8mNfHm7+DkL5lR9iP3/rAuOeLaOhyCR04qt2IL1YePOFxEyhWnQXLqWu8Kpl faQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571098; x=1707175898; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w0VyFnxuloTGEbgz18a76FD3rClrdXq5QXu0ykcKSCs=; b=cg5nFdDobEIhj72E4H9kAOnOyrYHog9rQxh8NjowidbtGZKDtQpUfpjGG1Aiamk4fK DoK6lTFFSR9nq11sNGNNvfqWJgYcnsZGFYYGKaIvTSXIW8n9hU/i+vcNCXJpnhZxc9hb l5QyDCcl9k3p2XAEsdLyOabt+BF6Stmp+/Sw+ye3gFX6muvM3Ao1Piizyf5Q1twkAuQ5 Wthmb1R4eVqSvNrLuhqK961JKaPE2Bf4/Yw1s8poBIA5KkfOfebszP8ifEBoXOWY+NXp Q4Ezi1T9Lq/E80lFLDnkucqrbMv23uqvxoiP7gGdGKr3f6lmDNaa7ctl72c4no6sojYg dmMw== X-Gm-Message-State: AOJu0YzhbFPMEF0QYYWVhD6nI8Gw2jutirZQqxoZymkeAjmwHSwhCc/a 2wb2rCuKsblDL4PA44HnclfWkEFwRopt5D1iDlDBX5xy5m0TQMrV7pXfDErgwEa74Vdb9Jg73cP 2+A8= X-Google-Smtp-Source: AGHT+IGw/8CG5ZBjwIZcWvlYi4Oa4Q3VTp3fsYs80/zzCxy2X/R2NxoC0sTGvcNQ4Ui7N9tQnWA/bw== X-Received: by 2002:a17:90a:a512:b0:290:6c4:ad45 with SMTP id a18-20020a17090aa51200b0029006c4ad45mr4216647pjq.39.1706571098448; Mon, 29 Jan 2024 15:31:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 22/33] target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index Date: Tue, 30 Jan 2024 09:30:32 +1000 Message-Id: <20240129233043.34558-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571237868100003 Content-Type: text/plain; charset="utf-8" Free up the riscv_cpu_mmu_index name for other usage; emphasize that the argument is 'env'. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 4 ++-- target/riscv/cpu_helper.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5f3955c38d..9c825c7b51 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -498,7 +498,7 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); +int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t reta= ddr); @@ -507,7 +507,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); =20 -#define cpu_mmu_index riscv_cpu_mmu_index +#define cpu_mmu_index riscv_env_mmu_index =20 #ifndef CONFIG_USER_ONLY void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c7cc7eb423..15f87ecdb0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -33,7 +33,7 @@ #include "debug.h" #include "tcg/oversized-guest.h" =20 -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) +int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return 0; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571458; cv=none; d=zohomail.com; s=zohoarc; b=GLxvW8akke2UdUTgpKpIAznkH+OIozpkL4r8IhaflVu4TMT103aJZ/NY09ocv+MiGtXxyoEfyi5u/dBwflCehzeghJS4kpq4rmLGQsdaop7amjjXndltzK0p69sOGCzqX9TDmYAiC1AzyOEjSP7yO2RC6FegrWT6q+VbXjK2+ic= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571458; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=T1A5JMP4c4pUqbkuAUmVb/gWlj2brd508NIa6msXbG4=; b=A6+K2KPIu4H991ZcqZtgBaEo8IRx2g8F916Lwil11srpldwie8ct7g7XmStnOCLBkq5FxRdXrnDIFsJHu6l19oAV016eWyWSSMGTQl+mAi043kSZwM7t30AVSwkqxDVpjymQphDs9lvuqwi4BmFSQRaMZkuuRpQN8K084XuUsHE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706571458474989.1672530326557; Mon, 29 Jan 2024 15:37:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUb6Q-0005xh-8N; Mon, 29 Jan 2024 18:31:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUb6N-0005wy-Tr for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:43 -0500 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUb6L-00059A-TX for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:43 -0500 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-29065efa06fso2677526a91.1 for ; Mon, 29 Jan 2024 15:31:41 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571100; x=1707175900; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T1A5JMP4c4pUqbkuAUmVb/gWlj2brd508NIa6msXbG4=; b=MGzoZ4epBncI5QdoFjTJHMeHiruX7062BSBjEKQfsj2F6Dk232Ckaoa9GXzEMBszce OQCB8mBQA5J/cpDgyxGghxSLN+50hgcWD9z0haTXLjKK2pBAn9nod8fpeJ9r9bYnN9nn H+3NRc608baQXq9xYeYhB2R94rNqnixcp+Bz+3xFkN4tyhHcRKtE8RTy5ekYkihPitBf kBiTrYYnDImlTNhd6xKb2JySK5dKUt6ly49qMHga4RUq4+mbJXcqtD8Abuv8M5gshrXp caX0Ip4ICO4S8+MkXeUfxzPieuNkDXlRVEpJ+CW3wrOboyBuHNgV72oznEaqXCtCyG4a YtRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571100; x=1707175900; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T1A5JMP4c4pUqbkuAUmVb/gWlj2brd508NIa6msXbG4=; b=sM2gW26v45FHQ/eYTs2rnVk2gf6gzYao3Fv1xXymRXeF/7mfAcKGEYQKe9ncEK2vzR ODNOPF3Fa2Ot/7SSXB1HvhWKXlnZz9QrLsBi59CU6bkV83LR4JEwQaM2TFY9w8FE6zLw jXxyvNU8zh7+6Kbtcb2UrTtMNKaHTSeXsX+h58Bk0OU4WlEsPYjixpWG9UWNlFd+AWdJ uo3/btnBCzfbEBP/mbPLGexLeENqFJRqJlOlUh/Zm2aqr01LrL4FkTtOrmrbiEZZaFMa /CHUJWJo8Vjl+NZRt8EGBKJmVgeKNQiTUajn07r9o4zWlAM6eVRBb8GgyFefgyCUrYYC jdNA== X-Gm-Message-State: AOJu0Ywl76DMgOwZJOTaYTkmBWIzLvz5OaSpd10TVo18WrdXTrb6a1hY VeFCkzdBnUEXBsMHky0dJfevF1PP7ZcQJmQTi8sOtFrq+nfDcr56pmc9SD38gVAkUHgT+hMVOLI WThA= X-Google-Smtp-Source: AGHT+IG6vM83YY3uPWXAD7JYlKQ8m3WdGStjzEtf7yjU7xeAW5yQi8oOPXva6ouHN0tr7oD3Oa1v1A== X-Received: by 2002:a17:90a:898e:b0:28e:8692:af8 with SMTP id v14-20020a17090a898e00b0028e86920af8mr4363356pjn.26.1706571100740; Mon, 29 Jan 2024 15:31:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 23/33] target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index Date: Tue, 30 Jan 2024 09:30:33 +1000 Message-Id: <20240129233043.34558-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571460348100012 Content-Type: text/plain; charset="utf-8" Use the target-specific function name in preference to the generic name. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu_helper.c | 4 ++-- target/riscv/op_helper.c | 4 ++-- target/riscv/vector_helper.c | 9 +++++---- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 15f87ecdb0..b6b23b7d03 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -106,7 +106,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, #else flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); =20 - flags |=3D cpu_mmu_index(env, 0); + flags |=3D riscv_env_mmu_index(env, 0); fs =3D get_field(env->mstatus, MSTATUS_FS); vs =3D get_field(env->mstatus, MSTATUS_VS); =20 @@ -1200,7 +1200,7 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, va= ddr addr) CPURISCVState *env =3D &cpu->env; hwaddr phys_addr; int prot; - int mmu_idx =3D cpu_mmu_index(&cpu->env, false); + int mmu_idx =3D riscv_env_mmu_index(&cpu->env, false); =20 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_id= x, true, env->virt_enabled, true)) { diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 5355225d56..f414aaebdb 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -157,7 +157,7 @@ void helper_cbo_zero(CPURISCVState *env, target_ulong a= ddress) { RISCVCPU *cpu =3D env_archcpu(env); uint16_t cbozlen =3D cpu->cfg.cboz_blocksize; - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D riscv_env_mmu_index(env, false); uintptr_t ra =3D GETPC(); void *mem; =20 @@ -205,7 +205,7 @@ static void check_zicbom_access(CPURISCVState *env, uintptr_t ra) { RISCVCPU *cpu =3D env_archcpu(env); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D riscv_env_mmu_index(env, false); uint16_t cbomlen =3D cpu->cfg.cbom_blocksize; void *phost; int ret; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c1c3a4d1ea..fe0d5d053c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -113,14 +113,15 @@ static void probe_pages(CPURISCVState *env, target_ul= ong addr, { target_ulong pagelen =3D -(addr | TARGET_PAGE_MASK); target_ulong curlen =3D MIN(pagelen, len); + int mmu_index =3D riscv_env_mmu_index(env, false); =20 probe_access(env, adjust_addr(env, addr), curlen, access_type, - cpu_mmu_index(env, false), ra); + mmu_index, ra); if (len > curlen) { addr +=3D curlen; curlen =3D len - curlen; probe_access(env, adjust_addr(env, addr), curlen, access_type, - cpu_mmu_index(env, false), ra); + mmu_index, ra); } } =20 @@ -464,6 +465,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, uint32_t esz =3D 1 << log2_esz; uint32_t vma =3D vext_vma(desc); target_ulong addr, offset, remain; + int mmu_index =3D riscv_env_mmu_index(env, false); =20 /* probe every access */ for (i =3D env->vstart; i < env->vl; i++) { @@ -478,8 +480,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, remain =3D nf << log2_esz; while (remain > 0) { offset =3D -(addr | TARGET_PAGE_MASK); - host =3D tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)); + host =3D tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_i= ndex); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571340041100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8cbfc7e781..be21fa09c6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -867,6 +867,11 @@ static bool riscv_cpu_has_work(CPUState *cs) #endif } =20 +static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return riscv_env_mmu_index(cpu_env(cs), ifetch); +} + static void riscv_cpu_reset_hold(Object *obj) { #ifndef CONFIG_USER_ONLY @@ -1810,6 +1815,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) =20 cc->class_by_name =3D riscv_cpu_class_by_name; cc->has_work =3D riscv_cpu_has_work; + cc->mmu_index =3D riscv_cpu_mmu_index; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; cc->get_pc =3D riscv_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571582; cv=none; d=zohomail.com; s=zohoarc; b=CmLhEYK3pCV7NW3pA0FxmVa6kdtECDUaygL5MMjXn5wWm8TNKp+PKuWS5+TUd6euOjLbJ1umgZhYBVgV5xKKgvBetqxFpO4VtVulkKWnCkebuNjpcV7vOgS/xL/bzCKJex3UXuHTg95dqRWa7gXGkk4C4zD2WC0LfmIOpxcyozo= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571584620100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/rx/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 353132dac2..5205167da1 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -64,6 +64,11 @@ static bool rx_cpu_has_work(CPUState *cs) (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); } =20 +static int riscv_cpu_mmu_index(CPUState *cs, bool ifunc) +{ + return 0; +} + static void rx_cpu_reset_hold(Object *obj) { RXCPU *cpu =3D RX_CPU(obj); @@ -204,6 +209,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) =20 cc->class_by_name =3D rx_cpu_class_by_name; cc->has_work =3D rx_cpu_has_work; + cc->mmu_index =3D riscv_cpu_mmu_index; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; cc->get_pc =3D rx_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571380; cv=none; d=zohomail.com; s=zohoarc; b=SP8jDr01/kXy5Mrh9D22O4tSHCpYs2bdAB4xhfFOUNsPKLXfSOZ5NoN+a93kRxMVCTfvwB5ugZuHGbwVYDIN32Mo8IJSz2uGzGGCf5iv/IEFwSqJe2myEdaA3hoUkEkUtrT75nYXLicbxd1GOPo+mTmyrFT02GR7kmEhGJ0I1LU= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571382140100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/s390x/cpu.h | 4 +++- target/s390x/tcg/mem_helper.c | 34 ++++++++++++++++++---------------- 2 files changed, 21 insertions(+), 17 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index fa3aac4f97..f0fed5d6ad 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -381,7 +381,7 @@ extern const VMStateDescription vmstate_s390_cpu; #define MMU_HOME_IDX 2 #define MMU_REAL_IDX 3 =20 -static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) +static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return MMU_USER_IDX; @@ -412,6 +412,8 @@ static inline int cpu_mmu_index(CPUS390XState *env, boo= l ifetch) #endif } =20 +#define cpu_mmu_index s390x_env_mmu_index + #ifdef CONFIG_TCG =20 #include "tcg/tcg_s390x.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 84103251b9..557831def4 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -358,7 +358,7 @@ static int mmu_idx_from_as(uint8_t as) static uint32_t do_helper_nc(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src, uintptr_t ra) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); S390Access srca1, srca2, desta; uint32_t i; uint8_t c =3D 0; @@ -392,7 +392,7 @@ uint32_t HELPER(nc)(CPUS390XState *env, uint32_t l, uin= t64_t dest, static uint32_t do_helper_xc(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src, uintptr_t ra) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); S390Access srca1, srca2, desta; uint32_t i; uint8_t c =3D 0; @@ -433,7 +433,7 @@ uint32_t HELPER(xc)(CPUS390XState *env, uint32_t l, uin= t64_t dest, static uint32_t do_helper_oc(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src, uintptr_t ra) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); S390Access srca1, srca2, desta; uint32_t i; uint8_t c =3D 0; @@ -467,7 +467,7 @@ uint32_t HELPER(oc)(CPUS390XState *env, uint32_t l, uin= t64_t dest, static uint32_t do_helper_mvc(CPUS390XState *env, uint32_t l, uint64_t des= t, uint64_t src, uintptr_t ra) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); S390Access srca, desta; uint32_t i; =20 @@ -508,7 +508,7 @@ void HELPER(mvc)(CPUS390XState *env, uint32_t l, uint64= _t dest, uint64_t src) /* move right to left */ void HELPER(mvcrl)(CPUS390XState *env, uint64_t l, uint64_t dest, uint64_t= src) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); const uint64_t ra =3D GETPC(); S390Access srca, desta; int32_t i; @@ -529,7 +529,7 @@ void HELPER(mvcrl)(CPUS390XState *env, uint64_t l, uint= 64_t dest, uint64_t src) /* move inverse */ void HELPER(mvcin)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t= src) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); S390Access srca, desta; uintptr_t ra =3D GETPC(); int i; @@ -550,7 +550,7 @@ void HELPER(mvcin)(CPUS390XState *env, uint32_t l, uint= 64_t dest, uint64_t src) /* move numerics */ void HELPER(mvn)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t s= rc) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); S390Access srca1, srca2, desta; uintptr_t ra =3D GETPC(); int i; @@ -572,7 +572,7 @@ void HELPER(mvn)(CPUS390XState *env, uint32_t l, uint64= _t dest, uint64_t src) /* move with offset */ void HELPER(mvo)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t s= rc) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); /* MVO always processes one more byte than specified - maximum is 16 */ const int len_dest =3D (l >> 4) + 1; const int len_src =3D (l & 0xf) + 1; @@ -606,7 +606,7 @@ void HELPER(mvo)(CPUS390XState *env, uint32_t l, uint64= _t dest, uint64_t src) /* move zones */ void HELPER(mvz)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t s= rc) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); S390Access srca1, srca2, desta; uintptr_t ra =3D GETPC(); int i; @@ -669,7 +669,7 @@ uint32_t HELPER(clm)(CPUS390XState *env, uint32_t r1, u= int32_t mask, =20 if (!mask) { /* Recognize access exceptions for the first byte */ - probe_read(env, addr, 1, cpu_mmu_index(env, false), ra); + probe_read(env, addr, 1, s390x_env_mmu_index(env, false), ra); } =20 while (mask) { @@ -893,7 +893,7 @@ uint32_t HELPER(mvpg)(CPUS390XState *env, uint64_t r0, = uint32_t r1, uint32_t r2) { const uint64_t src =3D get_address(env, r2) & TARGET_PAGE_MASK; const uint64_t dst =3D get_address(env, r1) & TARGET_PAGE_MASK; - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); const bool f =3D extract64(r0, 11, 1); const bool s =3D extract64(r0, 10, 1); const bool cco =3D extract64(r0, 8, 1); @@ -946,7 +946,7 @@ inject_exc: /* string copy */ uint32_t HELPER(mvst)(CPUS390XState *env, uint32_t r1, uint32_t r2) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); const uint64_t d =3D get_address(env, r1); const uint64_t s =3D get_address(env, r2); const uint8_t c =3D env->regs[0]; @@ -1027,7 +1027,7 @@ static inline uint32_t do_mvcl(CPUS390XState *env, uint64_t *src, uint64_t *srclen, uint16_t pad, int wordsize, uintptr_t ra) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); int len =3D MIN(*destlen, -(*dest | TARGET_PAGE_MASK)); S390Access srca, desta; int i, cc; @@ -1084,7 +1084,7 @@ static inline uint32_t do_mvcl(CPUS390XState *env, /* move long */ uint32_t HELPER(mvcl)(CPUS390XState *env, uint32_t r1, uint32_t r2) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); uintptr_t ra =3D GETPC(); uint64_t destlen =3D env->regs[r1 + 1] & 0xffffff; uint64_t dest =3D get_address(env, r1); @@ -1742,7 +1742,7 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1= , uint32_t r2, static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2, bool parallel) { - uint32_t mem_idx =3D cpu_mmu_index(env, false); + uint32_t mem_idx =3D s390x_env_mmu_index(env, false); MemOpIdx oi16 =3D make_memop_idx(MO_TE | MO_128, mem_idx); MemOpIdx oi8 =3D make_memop_idx(MO_TE | MO_64, mem_idx); MemOpIdx oi4 =3D make_memop_idx(MO_TE | MO_32, mem_idx); @@ -2867,12 +2867,14 @@ uint32_t HELPER(cu42)(CPUS390XState *env, uint32_t = r1, uint32_t r2, uint32_t m3) void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len, uintptr_t ra) { + const int mmu_idx =3D s390x_env_mmu_index(env, false); + /* test the actual access, not just any access to the page due to LAP = */ while (len) { const uint64_t pagelen =3D -(addr | TARGET_PAGE_MASK); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571326103100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/s390x/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7f123863dc..49a2341acc 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -142,6 +142,11 @@ static bool s390_cpu_has_work(CPUState *cs) return s390_cpu_has_int(cpu); } =20 +static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return s390x_env_mmu_index(cpu_env(cs), ifetch); +} + static void s390_query_cpu_fast(CPUState *cpu, CpuInfoFast *value) { S390CPU *s390_cpu =3D S390_CPU(cpu); @@ -352,6 +357,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) scc->reset =3D s390_cpu_reset; cc->class_by_name =3D s390_cpu_class_by_name, cc->has_work =3D s390_cpu_has_work; + cc->mmu_index =3D s390x_cpu_mmu_index; cc->dump_state =3D s390_cpu_dump_state; cc->query_cpu_fast =3D s390_query_cpu_fast; cc->set_pc =3D s390_cpu_set_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571551; cv=none; d=zohomail.com; s=zohoarc; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571112; x=1707175912; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pNNENKH/HQj+hw6JTH28lUCmFQmGh5or2lvTAvTEZkw=; b=T2Uavm53nWw++xcqq73mP5KT7OM6qbF6z88B3NbCUFLeYLoVT7UYqkQ6EyK2Fknt9S 6xJaqAS6qesioodjSDhEvzp2yUfzVrNtS7xMuyyjQwaNwagrVnCtf1ZfnZMDW8uk/cT9 mYDtRbqlA8CGlZ9ZPbiL602IpbORvO9/waI884+D+lFU37b8C4pknZ5ujkgvy2phFLvY LJknPyOSwn5nCEo90K41Ftahj/A3HTIMbSXMf4Y6vysRkCxOdxZWtO9qOwMnQxYoCGMh jhKspJLfqOc4W7cofJyG7OGeavFVLGlH3coJc/9prsq5MhWIERzTcbdOPKnDm+jrYvVc 4aww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571112; x=1707175912; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pNNENKH/HQj+hw6JTH28lUCmFQmGh5or2lvTAvTEZkw=; b=ABAlH/A57X0f3VY6YOuHHxzoJV3JYcZb9XPrdou1vWuAkVK1D6lrjH9Mv0rU8x+cPI G/08oUdDjbwZT7DNiNsTLQ8Ed6ie6oTcsWlWbgbYtMS7USKsI5kDcqr13nlYActF+Ta0 /DYhYsES52TodJKb3yY5nWeSJTh4W5jCNwPh7RYHtLMAlm/628Z7TjU5vgcT/aB6QVR9 g5T2HAlmkWuG0yhmdOZpsQEnpZPIuuPU0c0sFZyUJNYOu2oEGtrZVqDZXlTBbBE6IBNp I+mbsENBozBrLweWoGxuw8rimmRwL23RXO1dlwiCT2fIC/IkG1dnFczwMb606fhxPQF/ MXfg== X-Gm-Message-State: AOJu0Yyc7peRGMdMiG57KurPEcBeBbFicl5KXRsx1E5hO2bZNi9pLax7 5kKUjEp+0lLRp5bXVSMWoUxr6NCDFHAmhKaOcbtaChuShfmnJ9BJz2FUq3/pPYVKxAy/dUyZWo/ chcU= X-Google-Smtp-Source: AGHT+IEA8s3zPLl5CgEhOaWD8vCynTc+bHpj0vi+QeYfCMX2RAAMGsmPDFKousDVnaVic4GBcVC7BQ== X-Received: by 2002:a17:903:2351:b0:1d7:428f:50fd with SMTP id c17-20020a170903235100b001d7428f50fdmr7656338plh.31.1706571112105; Mon, 29 Jan 2024 15:31:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 28/33] target/sh4: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:38 +1000 Message-Id: <20240129233043.34558-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571552568100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/sh4/cpu.h | 16 ++++++---------- target/sh4/cpu.c | 16 ++++++++++++++++ 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 0e6fa65bae..9c5e2b349e 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -273,16 +273,6 @@ void cpu_load_tlb(CPUSH4State * env); =20 /* MMU modes definitions */ #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch) -{ - /* The instruction in a RTE delay slot is fetched in privileged - mode, but executed in user mode. */ - if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { - return 0; - } else { - return (env->sr & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; - } -} =20 #include "exec/cpu-all.h" =20 @@ -380,6 +370,12 @@ static inline void cpu_write_sr(CPUSH4State *env, targ= et_ulong sr) env->sr =3D sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); } =20 +int sh4_cpu_mmu_index(CPUState *cs, bool ifetch); +static inline int cpu_mmu_index(CPUSH4State *env, bool ifetch) +{ + return sh4_cpu_mmu_index(env_cpu(env), ifetch); +} + static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 39772955b5..6fead5655f 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -89,6 +89,21 @@ static bool superh_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } =20 +int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUSH4State *env =3D cpu_env(cs); + + /* + * The instruction in a RTE delay slot is fetched in privileged mode, + * but executed in user mode. + */ + if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { + return 0; + } else { + return (env->sr & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; + } +} + static void superh_cpu_reset_hold(Object *obj) { CPUState *s =3D CPU(obj); @@ -266,6 +281,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D superh_cpu_class_by_name; cc->has_work =3D superh_cpu_has_work; + cc->mmu_index =3D sh4_cpu_mmu_index; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; cc->get_pc =3D superh_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571204; cv=none; d=zohomail.com; s=zohoarc; b=IFMSQb2ECl+Zqcz8/yFReZQ4M6G6tjsocdCoUkm4ePbUoXEGQ4O72oRE4pcnUOUxwAgQq1d09WvOxdJZ85lIj50sERPu3iJUU/mDJKC6f4teG0D51U0JxRw16Vv8hFi8YEoLUeGqWuBvwlYE8zBjfbQ4GyplvpSrB6aUQ7ZDwgA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571204; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OUpbcCo1Gwdi5RtgiHT0o/+TLFpXSWoQp1ADmvaIAeE=; b=FXMGhFj7zN/J/Ol141T2GeTykx0ppDsibGkCL+vLJR+VFJTqw3EcOErU/gdEQj+DVexfL4768VLbxQdQ1WMhjsMANCW1rklsyBBe4cF5uPWp158j7LJL8rrN9Iwfs7R0sE8f2WkSmsIHN8g0N543q3RyZf+h97Rp8NuxutrFcjc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170657120489774.56426905415731; Mon, 29 Jan 2024 15:33:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUb6z-0006eP-Ps; Mon, 29 Jan 2024 18:32:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUb6d-0006BE-JI for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:32:03 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUb6a-0005As-A0 for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:31:57 -0500 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-290b1e19101so3281998a91.0 for ; Mon, 29 Jan 2024 15:31:55 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571114; x=1707175914; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OUpbcCo1Gwdi5RtgiHT0o/+TLFpXSWoQp1ADmvaIAeE=; b=eRr3aR97g1P5+ySHFEy/kK+B9hqTXLOA/Ia1x7v10uVy04UdifUX+40RaboUvdMonw L+SyEs1rvMKZk+FE1FXk8MWa7C5hQXzd80FOPVIbY183RfAav4XHCeY+eWSEr8iHefG/ NtydjIIAPacTMDxrR28ue9RAS2XuZodLJsdESMEvvPFqzDqyvruJAJmFdVsfQa3sbJLW gSNCGDe63ZzIgqv9sNABf7H8YHSgrGJuyLCTozARgnTIlJcZzpC5i5lsX3bKBmgP/IZ5 02Dzw+JjVCOXY9zzniXm81oVCSd2Y3V2gk8ZgYsCAvXLFVhj6nVx07HHmEy7kJkGUfAC B09Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571114; x=1707175914; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OUpbcCo1Gwdi5RtgiHT0o/+TLFpXSWoQp1ADmvaIAeE=; b=bqqggRF89UpetZkM6/+xrfbabqWEU3at+araHKSih1JulZuA8GbL0LwyN+VuFQEeIx zUCh8BGDDFx2Afd47bD1YCs5LgLhhlGFT5Z3ZPucMcQvVdBkJYYDTvLcshWvKU8z2gs/ JyEBETZ4uNMI2VbmapDPpDD7pmjqPsKLAlsW4yxZUmJrSfpH/xmA1T/67EhzLbPIFJ6i 7JY/bBqlpZuGk18VlBaV+HoyvUTcaILCXGErTdfeSozXPcM6fk3BnkM/Jz/7R9aSTGwS CUzfEvGb68qTi0y0Sauv4//RGJsW93CgfSduWN7mZnZaqQoNQ4BwM/kL7SMAJHnqCzUR seMw== X-Gm-Message-State: AOJu0YztWzoYiO/hm93vkgLV/f1/Z80Etos9KQZFbLciaXyH0/S7u0zK TskuclxY0YmJxolhUtXD6uocx9FK/cyza5T8Xlklat3odCqmWtrbypbhAmyY1hpVvh6uAnfbZHS hLsY= X-Google-Smtp-Source: AGHT+IFW+/JiwHFFTRiKhroGzPNS5wC66nCN9prVjIt2Dm20vB3Nsj5WmAszJv8ufKbie9yyMSDA4A== X-Received: by 2002:a17:90a:f0d7:b0:290:c94b:6667 with SMTP id fa23-20020a17090af0d700b00290c94b6667mr49378pjb.48.1706571114361; Mon, 29 Jan 2024 15:31:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 29/33] target/sparc: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:39 +1000 Message-Id: <20240129233043.34558-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571205831100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/sparc/cpu.h | 34 ++++++---------------------------- target/sparc/cpu.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 28 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 12a11ecb26..92c58c92c1 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -708,34 +708,6 @@ static inline int cpu_supervisor_mode(CPUSPARCState *e= nv1) } #endif =20 -static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) -{ -#if defined(CONFIG_USER_ONLY) - return MMU_USER_IDX; -#elif !defined(TARGET_SPARC64) - if ((env->mmuregs[0] & MMU_E) =3D=3D 0) { /* MMU disabled */ - return MMU_PHYS_IDX; - } else { - return env->psrs; - } -#else - /* IMMU or DMMU disabled. */ - if (ifetch - ? (env->lsu & IMMU_E) =3D=3D 0 || (env->pstate & PS_RED) !=3D 0 - : (env->lsu & DMMU_E) =3D=3D 0) { - return MMU_PHYS_IDX; - } else if (cpu_hypervisor_mode(env)) { - return MMU_PHYS_IDX; - } else if (env->tl > 0) { - return MMU_NUCLEUS_IDX; - } else if (cpu_supervisor_mode(env)) { - return MMU_KERNEL_IDX; - } else { - return MMU_USER_IDX; - } -#endif -} - static inline int cpu_interrupts_enabled(CPUSPARCState *env1) { #if !defined (TARGET_SPARC64) @@ -777,6 +749,12 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_HYPER (1 << 7) #define TB_FLAG_ASI_SHIFT 24 =20 +int sparc_cpu_mmu_index(CPUState *cs, bool ifetch); +static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) +{ + return sparc_cpu_mmu_index(env_cpu(env), ifetch); +} + static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflag= s) { diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 7d0d629a3d..7a3b815737 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -718,6 +718,34 @@ static bool sparc_cpu_has_work(CPUState *cs) cpu_interrupts_enabled(env); } =20 +int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUSPARCState *env =3D cpu_env(cs); + +#ifndef TARGET_SPARC64 + if ((env->mmuregs[0] & MMU_E) =3D=3D 0) { /* MMU disabled */ + return MMU_PHYS_IDX; + } else { + return env->psrs; + } +#else + /* IMMU or DMMU disabled. */ + if (ifetch + ? (env->lsu & IMMU_E) =3D=3D 0 || (env->pstate & PS_RED) !=3D 0 + : (env->lsu & DMMU_E) =3D=3D 0) { + return MMU_PHYS_IDX; + } else if (cpu_hypervisor_mode(env)) { + return MMU_PHYS_IDX; + } else if (env->tl > 0) { + return MMU_NUCLEUS_IDX; + } else if (cpu_supervisor_mode(env)) { + return MMU_KERNEL_IDX; + } else { + return MMU_USER_IDX; + } +#endif +} + static char *sparc_cpu_type_name(const char *cpu_model) { char *name =3D g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model); @@ -906,6 +934,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->class_by_name =3D sparc_cpu_class_by_name; cc->parse_features =3D sparc_cpu_parse_features; cc->has_work =3D sparc_cpu_has_work; + cc->mmu_index =3D sparc_cpu_mmu_index; cc->dump_state =3D sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug =3D sparc_cpu_memory_rw_debug; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571464; cv=none; d=zohomail.com; s=zohoarc; b=A21d7OHid6UJTA3b9fJQ0Np+Qc5Yns4y0Wf2JwCOoD8F2jpVSJSDgxsHO1h9sstZYMDZjQMGk179Z/uDRjrYCFDW59TVRYG9elza1yOJ6y64QGeJCLuN7rY/J5naaXNtk8WOoRSmw0UO2hTrjKwqXSxohnEQ0/V+avWat0uGOsw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571464; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Q1GkbX/2RhRtI6NxAEXwoMhTS8WkrOI/cziGDkYfcrg=; b=B2eYdMtIbIcgwfkwHMPd4Sg3/OxyRcpISgoY/4fOrTrUxMDxPh6wBXKWheyP5jVV9yQLP8BCyKuA27dxd9qi8hY9qKIQewlB9uV3UIL37np71xqAbbrjsmxg/gJGTFwafIVdHh3GTribtXUpTwSGfL7zkiuZU2SOCmjv6apHk30= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706571464190126.3487522216817; Mon, 29 Jan 2024 15:37:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUb73-0006zd-Dw; Mon, 29 Jan 2024 18:32:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUb6f-0006BP-PN for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:32:09 -0500 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUb6d-0005BB-BJ for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:32:01 -0500 Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-5ca29c131ebso3012380a12.0 for ; Mon, 29 Jan 2024 15:31:57 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571116; x=1707175916; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q1GkbX/2RhRtI6NxAEXwoMhTS8WkrOI/cziGDkYfcrg=; b=vZJ3YOQQoepBeeuY41GiScFHKMLk6jXnROrxMH6JRgBTBTHxElDxkP3Q1obnwnUA0z t+mMDDTVGXt8M01E1W7qtK3WD3fSYRouPWJPJnAUF+44Fue8PyGg23Zkikktm2vnwb4W DylN1bMnaB5AtX02POFvqt1H6ADi5DYWme0WHmsfcdO97oIjPJWp4YrkEYNle4aqDsee QPcf4UrPhBCZZ9TQ00mwCx+/SF9Yfg32ddDth1syC0Qwop3bdFbHbdOj84FUh5zDDloZ GRZAp89XBj6nWZAA1HZLTW/pPgCu06NLPLUqZJaYrKXuc7ZQVhbE0+ZOn70qPhXmoX7c Ofyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571116; x=1707175916; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571466371100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Bastian Koppelmann Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/tricore/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index e6d91c74b5..74e8a22b86 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -89,6 +89,11 @@ static bool tricore_cpu_has_work(CPUState *cs) return true; } =20 +static int tricore_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return 0; +} + static void tricore_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -194,6 +199,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) &mcc->parent_phases); cc->class_by_name =3D tricore_cpu_class_by_name; cc->has_work =3D tricore_cpu_has_work; + cc->mmu_index =3D tricore_cpu_mmu_index; =20 cc->gdb_read_register =3D tricore_cpu_gdb_read_register; cc->gdb_write_register =3D tricore_cpu_gdb_write_register; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571332; cv=none; d=zohomail.com; s=zohoarc; b=ZLAnuXfew7E9b6qHVPWp7ZPn8ProedeOyPKSAAbp2EbagvE+ss0xCAm6NY3vyMxqNYrnUzAaWJA7VFkJ3kymL0Mox+ZKDmIGjt1KyQLtieVsBkGZPyCctC8o+446xCBnzxUQ7/EFGmHE784pdBGqxiUV1AjhawAMnvBJb0ejrpc= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571334095100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/xtensa/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 62020b1f33..79f91819df 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -74,6 +74,11 @@ static bool xtensa_cpu_has_work(CPUState *cs) #endif } =20 +static int xtensa_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return xtensa_get_cring(cpu_env(cs)); +} + #ifdef CONFIG_USER_ONLY static bool abi_call0; =20 @@ -252,6 +257,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D xtensa_cpu_class_by_name; cc->has_work =3D xtensa_cpu_has_work; + cc->mmu_index =3D xtensa_cpu_mmu_index; cc->dump_state =3D xtensa_cpu_dump_state; cc->set_pc =3D xtensa_cpu_set_pc; cc->get_pc =3D xtensa_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571488; cv=none; d=zohomail.com; s=zohoarc; b=bChkpaDb2FfNdSeC2+CQbIEKQySsJsoIU75KFQMSrETSV4/Us8D2Utw0Kt1GmtzQ88bgbuepuDZLhFfUG4hmjFtdrz3XDdTVksZRUsSyNSIw5U0tDrpCm3Xsezj1CEX5+kZQW5aPGJYfcRYuTu1J2dSZpFYrqxHS1gHXFkFmrRk= ARC-Message-Signature: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:32:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706571121; x=1707175921; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EOCVROUqo6BWAAqVMvgh7b7Oex6mEKUK85oHrQsmtgA=; b=RclNK3urAyrZ4AMb+v6ccZ00J7/DxTDRhbAmocnN7pVg4zYLktUaQZJYHoHBLYL1fF CMQs4TPqxLUdwgWwriX4zpS/75xv9c9OTnruMkyM16MuZF1kMYxHQTNWPPRcIHzWEIlq Cazcd9zF3G37+EDd56t363e1eAGcDZJvHQIKkLWIIXpBqK4lR/72w87sxOg/eKAGxWR9 BSz6xj3cgMiF8WMPBACjtKSgj8DDQLdNPd/+kceFIzViVLfNRfhI1FMn9tFDOFKWcBEU UX5uMl6N2vdhL4905zOL+VjVI2+i9SL8zDOCUw2Zch3Z+39RyO5DChSt8750r2URA5IJ alJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706571121; x=1707175921; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EOCVROUqo6BWAAqVMvgh7b7Oex6mEKUK85oHrQsmtgA=; b=WEsUHrcFQuCNr8iDfohJd740YsSFZcO3EjAkk8+2GTQA3P1ld87vl0y6ZDvqFnt13k UKj8gh9mTkkjhOaHQOFLmqrccrMJ3WmHWK2kSrvsmvoo1p3T55RklYbxSRFMGSHyIE1f LnsRX0tZYQ0KJcgSFSkh774x+Y5YA1bV7MUvNforZtongk4qSw04MW7u8lhk4JF2g2M7 JM/zzFGMW7zNIHyZvlioDc13zpmUjSKJwa/KlpI0IVLdiLS3OPVizI0St/K/sgDNpyor T3haKWRcXUp2UCn5pytUuAcu5PS1C5eAIQ84emoXxm3oZovCYAZWwE7pWcT5M/ByawSb MqRQ== X-Gm-Message-State: AOJu0Yw1YFg1r502pEJPOIEQ/Y265ZEadyDEjMuJ266XFM7WO8DWexiP r+UR+wq/3bZeS5ZTHgenzJBlfnExVaq97BvIYY554nAgvoV9rwCKnS4N0ent7qi0i3krzfdGhMv 8/sc= X-Google-Smtp-Source: AGHT+IGzZgaS9y2Oo12mptc2a7aRYB01QlrEnbc2E/Yfkp2HZCPUpxlkI+lSR1sH2z/88okZ9YWMyA== X-Received: by 2002:a17:903:124a:b0:1d7:5e48:7304 with SMTP id u10-20020a170903124a00b001d75e487304mr5414514plh.86.1706571121449; Mon, 29 Jan 2024 15:32:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 32/33] include/exec: Implement cpu_mmu_index generically Date: Tue, 30 Jan 2024 09:30:42 +1000 Message-Id: <20240129233043.34558-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571490461100003 Content-Type: text/plain; charset="utf-8" For user-only mode, use MMU_USER_IDX. For system mode, use CPUClass.mmu_index. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-all.h | 4 ++++ include/exec/cpu-common.h | 19 +++++++++++++++++++ target/alpha/cpu.h | 5 ----- target/arm/cpu.h | 13 ------------- target/avr/cpu.h | 5 ----- target/cris/cpu.h | 4 ---- target/hexagon/cpu.h | 9 --------- target/hppa/cpu.h | 10 ---------- target/i386/cpu.h | 6 ------ target/loongarch/cpu.h | 10 ---------- target/m68k/cpu.h | 4 ---- target/microblaze/cpu.h | 6 ------ target/mips/cpu.h | 5 ----- target/nios2/cpu.h | 6 ------ target/openrisc/cpu.h | 6 ------ target/ppc/cpu.h | 5 ----- target/riscv/cpu.h | 2 -- target/rx/cpu.h | 5 ----- target/s390x/cpu.h | 2 -- target/sh4/cpu.h | 6 ------ target/sparc/cpu.h | 6 ------ target/tricore/cpu.h | 5 ----- target/xtensa/cpu.h | 5 ----- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- 31 files changed, 31 insertions(+), 133 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 8501a33dbf..80c0d0699b 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -311,6 +311,10 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) #define TLB_WATCHPOINT 0 =20 +static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) +{ + return MMU_USER_IDX; +} #else =20 /* diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index dcbd5f5783..5a4a36a7d8 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -262,4 +262,23 @@ static inline CPUState *env_cpu(CPUArchState *env) return (void *)env - sizeof(CPUState); } =20 +#ifndef CONFIG_USER_ONLY +/** + * cpu_mmu_index: + * @env: The cpu environment + * @ifetch: True for code access, false for data access. + * + * Return the core mmu index for the current translation regime. + * This function is used by generic TCG code paths. + * + * The user-only version of this function is inline in cpu-all.h, + * where it always returns MMU_USER_IDX. + */ +static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) +{ + CPUState *cs =3D env_cpu(env); + return cs->cc->mmu_index(cs, ifetch); +} +#endif /* !CONFIG_USER_ONLY */ + #endif /* CPU_COMMON_H */ diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 3beff2738a..7188a409a0 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -398,11 +398,6 @@ static inline int alpha_env_mmu_index(CPUAlphaState *e= nv) return ret; } =20 -static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) -{ - return alpha_env_mmu_index(env); -} - enum { IR_V0 =3D 0, IR_T0 =3D 1, diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d3477b1601..63f31e0d98 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3240,19 +3240,6 @@ FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHIC= H) =20 -/** - * cpu_mmu_index: - * @env: The cpu environment - * @ifetch: True for code access, false for data access. - * - * Return the core mmu index for the current translation regime. - * This function is used by generic TCG code paths. - */ -static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) -{ - return EX_TBFLAG_ANY(env->hflags, MMUIDX); -} - /** * sve_vq * @env: the cpu context diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 4595c6bb18..d185d20dcb 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -184,11 +184,6 @@ static inline void set_avr_feature(CPUAVRState *env, i= nt feature) env->features |=3D (1U << feature); } =20 -static inline int cpu_mmu_index(CPUAVRState *env, bool ifetch) -{ - return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; -} - void avr_cpu_tcg_init(void); =20 int cpu_avr_exec(CPUState *cpu); diff --git a/target/cris/cpu.h b/target/cris/cpu.h index d830dcac5b..3904e5448c 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -260,10 +260,6 @@ enum { =20 /* MMU modes definitions */ #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) -{ - return !!(env->pregs[PR_CCS] & U_FLAG); -} =20 /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 5c11ae3445..3eef58fe8f 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -146,15 +146,6 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonStat= e *env, vaddr *pc, *flags =3D hex_flags; } =20 -static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else -#error System mode not supported on Hexagon yet -#endif -} - typedef HexagonCPU ArchCPU; =20 void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 04439f247d..7a181e8f33 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -281,16 +281,6 @@ static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE; } =20 -int hppa_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else - return hppa_cpu_mmu_index(env_cpu(env), ifetch); -#endif -} - void hppa_translate_init(void); =20 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 62bdb02378..6a5b180ccb 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2315,12 +2315,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *= env) #include "hw/i386/apic.h" #endif =20 -int x86_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) -{ - return x86_cpu_mmu_index(env_cpu(env), ifetch); -} - static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 47fd110e81..ec37579fd6 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -408,16 +408,6 @@ struct LoongArchCPUClass { #define MMU_USER_IDX MMU_PLV_USER #define MMU_DA_IDX 4 =20 -int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else - return loongarch_cpu_mmu_index(env_cpu(env), ifetch); -#endif -} - static inline bool is_la64(CPULoongArchState *env) { return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) =3D=3D CPUCFG1_ARCH_L= A64; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index d13427b0fe..aca4aa610b 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -577,10 +577,6 @@ enum { /* MMU modes definitions */ #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) -{ - return (env->sr & SR_S) =3D=3D 0 ? 1 : 0; -} =20 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 90ab796de9..446af5dd4c 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -434,12 +434,6 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr ph= ysaddr, vaddr addr, MemTxResult response, uintptr_t retaddr); #endif =20 -int mb_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) -{ - return mb_cpu_mmu_index(env_cpu(env), ifetch); -} - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_mb_cpu; #endif diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 4c15e76781..ef26fe03c7 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1260,11 +1260,6 @@ static inline int mips_env_mmu_index(CPUMIPSState *e= nv) return hflags_mmu_index(env->hflags); } =20 -static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) -{ - return mips_env_mmu_index(env); -} - #include "exec/cpu-all.h" =20 /* Exceptions */ diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 9965ff74c1..4164a3432e 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -286,12 +286,6 @@ FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS =3D=3D 0. */ FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */ FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 =3D=3D 0. */ =20 -int nios2_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) -{ - return nios2_cpu_mmu_index(env_cpu(env), ifetch); -} - static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 7dbed8d8be..b1b7db5cbd 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -361,12 +361,6 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCSta= te *env, vaddr *pc, | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); } =20 -int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) -{ - return openrisc_cpu_mmu_index(env_cpu(env), ifetch); -} - static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) { return (env->sr diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5f4f52aec5..a44de22ca4 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1633,11 +1633,6 @@ static inline int ppc_env_mmu_index(CPUPPCState *env= , bool ifetch) #endif } =20 -static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) -{ - return ppc_env_mmu_index(env, ifetch); -} - /* Compatibility modes */ #if defined(TARGET_PPC64) bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9c825c7b51..f63ee9cc58 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -507,8 +507,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); =20 -#define cpu_mmu_index riscv_env_mmu_index - #ifndef CONFIG_USER_ONLY void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 65f9cd2d0a..c53593d7aa 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -158,11 +158,6 @@ static inline void cpu_get_tb_cpu_state(CPURXState *en= v, vaddr *pc, *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); } =20 -static inline int cpu_mmu_index(CPURXState *env, bool ifetch) -{ - return 0; -} - static inline uint32_t rx_cpu_pack_psw(CPURXState *env) { uint32_t psw =3D 0; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index f0fed5d6ad..d37a49b4d9 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -412,8 +412,6 @@ static inline int s390x_env_mmu_index(CPUS390XState *en= v, bool ifetch) #endif } =20 -#define cpu_mmu_index s390x_env_mmu_index - #ifdef CONFIG_TCG =20 #include "tcg/tcg_s390x.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 9c5e2b349e..9211da6bde 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -370,12 +370,6 @@ static inline void cpu_write_sr(CPUSH4State *env, targ= et_ulong sr) env->sr =3D sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); } =20 -int sh4_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUSH4State *env, bool ifetch) -{ - return sh4_cpu_mmu_index(env_cpu(env), ifetch); -} - static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 92c58c92c1..51856152fa 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -749,12 +749,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_HYPER (1 << 7) #define TB_FLAG_ASI_SHIFT 24 =20 -int sparc_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) -{ - return sparc_cpu_mmu_index(env_cpu(env), ifetch); -} - static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflag= s) { diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 2d4446cea5..220af69fc2 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -246,11 +246,6 @@ void fpu_set_state(CPUTriCoreState *env); =20 #define MMU_USER_IDX 2 =20 -static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) -{ - return 0; -} - #include "exec/cpu-all.h" =20 FIELD(TB_FLAGS, PRIV, 0, 2) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 4b033ee924..6b8d0636d2 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -713,11 +713,6 @@ static inline uint32_t xtensa_replicate_windowstart(CP= UXtensaState *env) /* MMU modes definitions */ #define MMU_USER_IDX 3 =20 -static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) -{ - return xtensa_get_cring(env); -} - #define XTENSA_TBFLAG_RING_MASK 0x3 #define XTENSA_TBFLAG_EXCM 0x4 #define XTENSA_TBFLAG_LITBASE 0x8 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index fbb37e541e..5f87c1b12a 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -94,7 +94,7 @@ static bool hppa_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); } =20 -int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) +static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUHPPAState *env =3D cpu_env(cs); =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 280bcb7d00..ef46755a50 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7720,7 +7720,7 @@ static bool x86_cpu_has_work(CPUState *cs) return x86_cpu_pending_interrupt(cs, cs->interrupt_request) !=3D 0; } =20 -int x86_cpu_mmu_index(CPUState *cs, bool ifetch) +static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUX86State *env =3D cpu_env(cs); =20 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 139acfe373..b08d0dc5de 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -375,7 +375,7 @@ static bool loongarch_cpu_has_work(CPUState *cs) #endif } =20 -int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) +static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) { CPULoongArchState *env =3D cpu_env(cs); =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6dad11905b..2002231a6b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -118,7 +118,7 @@ static bool mb_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); } =20 -int mb_cpu_mmu_index(CPUState *cs, bool ifetch) +static int mb_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUMBState *env =3D cpu_env(cs); MicroBlazeCPU *cpu =3D env_archcpu(env); diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index e42885997e..0760bf6b38 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -57,7 +57,7 @@ static bool nios2_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } =20 -int nios2_cpu_mmu_index(CPUState *cs, bool ifetch) +static int nios2_cpu_mmu_index(CPUState *cs, bool ifetch) { return (cpu_env(cs)->ctrl[CR_STATUS] & CR_STATUS_U ? MMU_USER_IDX : MMU_SUPERVISOR_IDX); diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 8670152c84..a3cb80ca34 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -68,7 +68,7 @@ static bool openrisc_cpu_has_work(CPUState *cs) CPU_INTERRUPT_TIMER); } =20 -int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) +static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUOpenRISCState *env =3D cpu_env(cs); =20 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 6fead5655f..2031168dc6 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -89,7 +89,7 @@ static bool superh_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } =20 -int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) +static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUSH4State *env =3D cpu_env(cs); =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 7a3b815737..afa62723fe 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -718,7 +718,7 @@ static bool sparc_cpu_has_work(CPUState *cs) cpu_interrupts_enabled(env); } =20 -int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) +static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUSPARCState *env =3D cpu_env(cs); =20 --=20 2.34.1 From nobody Tue Nov 26 16:23:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706571585; cv=none; d=zohomail.com; s=zohoarc; b=VvAmJxEXdtLUR4UC0BgfpP2j9mk2DKHdmUOf2i3SAkAWXbO7/xrb/BeQerRgt/beTHpFPpbZ2KoEO2OdZiNXn1xNPTbuVxzmEAxlYHDkWVeXGLMkS2WIT0OU1tSDlKGT0K1kr5vDF3GeasZAYHCzekZHqcMCgAzKEEDkgKGzBRQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706571585; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=NRFiIFFXsXgZu5z5Pbd1LGjtyQm58p6bIAWrhZNFn9w=; b=OidZEZQ5RYvNlQb2UDuo/6B4R2fs+qT0rlLHn5RR7+JPPu5tF2fmtoYYZ7BGUlROh2g4DaL/tjBAOVi4qFN/TZv5SxPsVVTLXkXudgAoKcAS6WeUIa65dpd9YHInS6sdSg3YbbuS6ti30cl58P4GoLtUlnx/lxp8QWnlAWlZf7E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706571585526585.295725094002; Mon, 29 Jan 2024 15:39:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUb76-0007I3-IQ; Mon, 29 Jan 2024 18:32:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUb6n-0006R1-83 for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:32:14 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUb6k-0005Bx-1T for qemu-devel@nongnu.org; Mon, 29 Jan 2024 18:32:08 -0500 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1d8f3966982so6566005ad.2 for ; Mon, 29 Jan 2024 15:32:05 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706571586737100011 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-all.h | 2 +- include/exec/cpu-common.h | 3 +-- target/sparc/cpu.h | 2 +- accel/tcg/cputlb.c | 22 +++++++++------- semihosting/uaccess.c | 2 +- target/cris/translate.c | 2 +- target/hppa/mem_helper.c | 2 +- target/hppa/op_helper.c | 8 +++--- target/i386/tcg/translate.c | 2 +- target/loongarch/tcg/tlb_helper.c | 4 +-- target/m68k/op_helper.c | 2 +- target/microblaze/helper.c | 3 +-- target/microblaze/mmu.c | 2 +- target/microblaze/translate.c | 2 +- target/nios2/translate.c | 2 +- target/openrisc/translate.c | 2 +- target/sparc/ldst_helper.c | 2 +- target/sparc/mmu_helper.c | 2 +- target/tricore/helper.c | 2 +- target/tricore/translate.c | 2 +- target/xtensa/mmu_helper.c | 2 +- accel/tcg/ldst_common.c.inc | 42 ++++++++++++++++++++----------- 22 files changed, 65 insertions(+), 49 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 80c0d0699b..bc05dce7ab 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -311,7 +311,7 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) #define TLB_WATCHPOINT 0 =20 -static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) +static inline int cpu_mmu_index(CPUState *cs, bool ifetch) { return MMU_USER_IDX; } diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 5a4a36a7d8..532663e81d 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -274,9 +274,8 @@ static inline CPUState *env_cpu(CPUArchState *env) * The user-only version of this function is inline in cpu-all.h, * where it always returns MMU_USER_IDX. */ -static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) +static inline int cpu_mmu_index(CPUState *cs, bool ifetch) { - CPUState *cs =3D env_cpu(env); return cs->cc->mmu_index(cs, ifetch); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 51856152fa..1e076f6355 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -755,7 +755,7 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *= env, vaddr *pc, uint32_t flags; *pc =3D env->pc; *cs_base =3D env->npc; - flags =3D cpu_mmu_index(env, false); + flags =3D cpu_mmu_index(env_cpu(env), false); #ifndef CONFIG_USER_ONLY if (cpu_supervisor_mode(env)) { flags |=3D TB_FLAG_SUPER; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3facfcbb24..047cd2cc0a 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1601,7 +1601,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState = *env, vaddr addr, void *p; =20 (void)probe_access_internal(env_cpu(env), addr, 1, MMU_INST_FETCH, - cpu_mmu_index(env, true), false, + cpu_mmu_index(env_cpu(env), true), false, &p, &full, 0, false); if (p =3D=3D NULL) { return -1; @@ -2959,26 +2959,30 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, = Int128 val, =20 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr) { - MemOpIdx oi =3D make_memop_idx(MO_UB, cpu_mmu_index(env, true)); - return do_ld1_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); + CPUState *cs =3D env_cpu(env); + MemOpIdx oi =3D make_memop_idx(MO_UB, cpu_mmu_index(cs, true)); + return do_ld1_mmu(cs, addr, oi, 0, MMU_INST_FETCH); } =20 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr) { - MemOpIdx oi =3D make_memop_idx(MO_TEUW, cpu_mmu_index(env, true)); - return do_ld2_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); + CPUState *cs =3D env_cpu(env); + MemOpIdx oi =3D make_memop_idx(MO_TEUW, cpu_mmu_index(cs, true)); + return do_ld2_mmu(cs, addr, oi, 0, MMU_INST_FETCH); } =20 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr) { - MemOpIdx oi =3D make_memop_idx(MO_TEUL, cpu_mmu_index(env, true)); - return do_ld4_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); + CPUState *cs =3D env_cpu(env); + MemOpIdx oi =3D make_memop_idx(MO_TEUL, cpu_mmu_index(cs, true)); + return do_ld4_mmu(cs, addr, oi, 0, MMU_INST_FETCH); } =20 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr) { - MemOpIdx oi =3D make_memop_idx(MO_TEUQ, cpu_mmu_index(env, true)); - return do_ld8_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); + CPUState *cs =3D env_cpu(env); + MemOpIdx oi =3D make_memop_idx(MO_TEUQ, cpu_mmu_index(cs, true)); + return do_ld8_mmu(cs, addr, oi, 0, MMU_INST_FETCH); } =20 uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c index 5d889f9263..dc587d73bc 100644 --- a/semihosting/uaccess.c +++ b/semihosting/uaccess.c @@ -26,7 +26,7 @@ void *uaccess_lock_user(CPUArchState *env, target_ulong a= ddr, =20 ssize_t uaccess_strlen_user(CPUArchState *env, target_ulong addr) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D cpu_mmu_index(env_cpu(env), false); size_t len =3D 0; =20 while (1) { diff --git a/target/cris/translate.c b/target/cris/translate.c index 7acea29a01..8f74b6c53f 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -2966,7 +2966,7 @@ static void cris_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) dc->cpu =3D env_archcpu(env); dc->ppc =3D pc_start; dc->pc =3D pc_start; - dc->mem_index =3D cpu_mmu_index(env, false); + dc->mem_index =3D cpu_mmu_index(cs, false); dc->flags_uptodate =3D 1; dc->flags_x =3D tb_flags & X_FLAG; dc->cc_x_uptodate =3D 0; diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 4fcc612754..629a9d90ef 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -646,7 +646,7 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulon= g vaddr) void HELPER(diag_btlb)(CPUHPPAState *env) { unsigned int phys_page, len, slot; - int mmu_idx =3D cpu_mmu_index(env, 0); + int mmu_idx =3D cpu_mmu_index(env_cpu(env), 0); uintptr_t ra =3D GETPC(); HPPATLBEntry *btlb; uint64_t virt_page; diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index ce15469465..b1f24a5aad 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -59,7 +59,7 @@ void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr, uint32_t val, uint32_t mask, uintptr_t ra) { - int mmu_idx =3D cpu_mmu_index(env, 0); + int mmu_idx =3D cpu_mmu_index(env_cpu(env), 0); uint32_t old, new, cmp, *haddr; void *vaddr; =20 @@ -86,7 +86,7 @@ static void atomic_store_mask64(CPUHPPAState *env, target= _ulong addr, int size, uintptr_t ra) { #ifdef CONFIG_ATOMIC64 - int mmu_idx =3D cpu_mmu_index(env, 0); + int mmu_idx =3D cpu_mmu_index(env_cpu(env), 0); uint64_t old, new, cmp, *haddr; void *vaddr; =20 @@ -235,7 +235,7 @@ static void do_stby_e(CPUHPPAState *env, target_ulong a= ddr, target_ulong val, default: /* Nothing is stored, but protection is checked and the cacheline is marked dirty. */ - probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra); + probe_write(env, addr, 0, cpu_mmu_index(env_cpu(env), 0), ra); break; } } @@ -296,7 +296,7 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong = addr, uint64_t val, default: /* Nothing is stored, but protection is checked and the cacheline is marked dirty. */ - probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra); + probe_write(env, addr, 0, cpu_mmu_index(env_cpu(env), 0), ra); break; } } diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 2808903661..10cba16256 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -6955,7 +6955,7 @@ static void i386_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cpu) dc->cc_op_dirty =3D false; dc->popl_esp_hack =3D 0; /* select memory access functions */ - dc->mem_index =3D cpu_mmu_index(env, false); + dc->mem_index =3D cpu_mmu_index(cpu, false); dc->cpuid_features =3D env->features[FEAT_1_EDX]; dc->cpuid_ext_features =3D env->features[FEAT_1_ECX]; dc->cpuid_ext2_features =3D env->features[FEAT_8000_0001_EDX]; diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 65ffbef08e..9e2a44c119 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -241,7 +241,7 @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) int prot; =20 if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D 0) { + cpu_mmu_index(cs, false)) !=3D 0) { return -1; } return phys_addr; @@ -320,7 +320,7 @@ static void invalidate_tlb_entry(CPULoongArchState *env= , int index) uint8_t tlb_ps; LoongArchTLB *tlb =3D &env->tlb[index]; =20 - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D cpu_mmu_index(env_cpu(env), false); uint8_t tlb_v0 =3D FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V); uint8_t tlb_v1 =3D FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V); uint64_t tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 1ce850bbc5..47b4173bb9 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -811,7 +811,7 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, = uint32_t a1, uint32_t a2, uint32_t l1, l2; uintptr_t ra =3D GETPC(); #if defined(CONFIG_ATOMIC64) - int mmu_idx =3D cpu_mmu_index(env, 0); + int mmu_idx =3D cpu_mmu_index(env_cpu(env), 0); MemOpIdx oi =3D make_memop_idx(MO_BEUQ, mmu_idx); #endif =20 diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 98bdb82de8..460eee0cf5 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -228,10 +228,9 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, = vaddr addr, MemTxAttrs *attrs) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); - CPUMBState *env =3D &cpu->env; target_ulong vaddr, paddr =3D 0; MicroBlazeMMULookup lu; - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D cpu_mmu_index(cs, false); unsigned int hit; =20 /* Caller doesn't initialize */ diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 75651979a9..234006634e 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -305,7 +305,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, = uint32_t v) } =20 hit =3D mmu_translate(cpu, &lu, v & TLB_EPN_MASK, - 0, cpu_mmu_index(env, false)); + 0, cpu_mmu_index(env_cpu(env), false)); if (hit) { env->mmu.regs[MMU_R_TLBX] =3D lu.idx; } else { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 2e628647d1..a465c2d245 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1607,7 +1607,7 @@ static void mb_tr_init_disas_context(DisasContextBase= *dcb, CPUState *cs) dc->ext_imm =3D dc->base.tb->cs_base; dc->r0 =3D NULL; dc->r0_set =3D false; - dc->mem_index =3D cpu_mmu_index(&cpu->env, false); + dc->mem_index =3D cpu_mmu_index(cs, false); dc->jmp_cond =3D dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NE= VER; dc->jmp_dest =3D -1; =20 diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 3078372b36..612556b297 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -948,7 +948,7 @@ static void nios2_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) Nios2CPU *cpu =3D env_archcpu(env); int page_insns; =20 - dc->mem_idx =3D cpu_mmu_index(env, false); + dc->mem_idx =3D cpu_mmu_index(cs, false); dc->cr_state =3D cpu->cr_state; dc->tb_flags =3D dc->base.tb->flags; dc->eic_present =3D cpu->eic_present; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index d4cbc5eaea..785bcb6552 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1528,7 +1528,7 @@ static void openrisc_tr_init_disas_context(DisasConte= xtBase *dcb, CPUState *cs) CPUOpenRISCState *env =3D cpu_env(cs); int bound; =20 - dc->mem_idx =3D cpu_mmu_index(env, false); + dc->mem_idx =3D cpu_mmu_index(cs, false); dc->tb_flags =3D dc->base.tb->flags; dc->delayed_branch =3D (dc->tb_flags & TB_FLAGS_DFLAG) !=3D 0; dc->cpucfgr =3D env->cpucfgr; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 09066d5487..52aa6c631b 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -690,7 +690,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong= addr, case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ break; case ASI_KERNELTXT: /* Supervisor code access */ - oi =3D make_memop_idx(memop, cpu_mmu_index(env, true)); + oi =3D make_memop_idx(memop, cpu_mmu_index(env_cpu(env), true)); switch (size) { case 1: ret =3D cpu_ldb_code_mmu(env, addr, oi, GETPC()); diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 453498c670..5170a668bb 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -901,7 +901,7 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; hwaddr phys_addr; - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D cpu_mmu_index(cs, false); =20 if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) !=3D 0)= { if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != =3D 0) { diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 174f666e1e..649373a9cb 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -48,7 +48,7 @@ hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) TriCoreCPU *cpu =3D TRICORE_CPU(cs); hwaddr phys_addr; int prot; - int mmu_idx =3D cpu_mmu_index(&cpu->env, false); + int mmu_idx =3D cpu_mmu_index(cs, false); =20 if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, MMU_DATA_LOAD, mmu_idx)) { diff --git a/target/tricore/translate.c b/target/tricore/translate.c index f1156c39e7..278c514ab0 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8355,7 +8355,7 @@ static void tricore_tr_init_disas_context(DisasContex= tBase *dcbase, { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUTriCoreState *env =3D cpu_env(cs); - ctx->mem_idx =3D cpu_mmu_index(env, false); + ctx->mem_idx =3D cpu_mmu_index(cs, false); =20 uint32_t tb_flags =3D (uint32_t)ctx->base.tb->flags; ctx->priv =3D FIELD_EX32(tb_flags, TB_FLAGS, PRIV); diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 2fda4e887c..47063b0a57 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -66,7 +66,7 @@ void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t = vaddr) * only the side-effects (ie any MMU or other exception) */ probe_access(env, vaddr, 1, MMU_INST_FETCH, - cpu_mmu_index(env, true), GETPC()); + cpu_mmu_index(env_cpu(env), true), GETPC()); } =20 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) diff --git a/accel/tcg/ldst_common.c.inc b/accel/tcg/ldst_common.c.inc index 44833513fb..c82048e377 100644 --- a/accel/tcg/ldst_common.c.inc +++ b/accel/tcg/ldst_common.c.inc @@ -354,7 +354,8 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ad= dr, uint64_t val, =20 uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_ldub_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_ldub_mmuidx_ra(env, addr, mmu_index, ra); } =20 int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) @@ -364,7 +365,8 @@ int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, u= intptr_t ra) =20 uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_lduw_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_lduw_be_mmuidx_ra(env, addr, mmu_index, ra); } =20 int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) @@ -374,17 +376,20 @@ int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ad= dr, uintptr_t ra) =20 uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_ldl_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_ldl_be_mmuidx_ra(env, addr, mmu_index, ra); } =20 uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_ldq_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_ldq_be_mmuidx_ra(env, addr, mmu_index, ra); } =20 uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_lduw_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_lduw_le_mmuidx_ra(env, addr, mmu_index, ra); } =20 int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) @@ -394,54 +399,63 @@ int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ad= dr, uintptr_t ra) =20 uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_ldl_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_ldl_le_mmuidx_ra(env, addr, mmu_index, ra); } =20 uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_ldq_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_ldq_le_mmuidx_ra(env, addr, mmu_index, ra); } =20 void cpu_stb_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra) { - cpu_stb_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stb_mmuidx_ra(env, addr, val, mmu_index, ra); } =20 void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra) { - cpu_stw_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stw_be_mmuidx_ra(env, addr, val, mmu_index, ra); } =20 void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra) { - cpu_stl_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stl_be_mmuidx_ra(env, addr, val, mmu_index, ra); } =20 void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr addr, uint64_t val, uintptr_t ra) { - cpu_stq_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stq_be_mmuidx_ra(env, addr, val, mmu_index, ra); } =20 void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra) { - cpu_stw_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stw_le_mmuidx_ra(env, addr, val, mmu_index, ra); } =20 void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra) { - cpu_stl_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stl_le_mmuidx_ra(env, addr, val, mmu_index, ra); } =20 void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr addr, uint64_t val, uintptr_t ra) { - cpu_stq_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stq_le_mmuidx_ra(env, addr, val, mmu_index, ra); } =20 /*--------------------------*/ --=20 2.34.1