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[188.255.126.251]) by smtp.gmail.com with ESMTPSA id co28-20020a0560000a1c00b0033af0cb2a35sm2577206wrb.108.2024.01.29.11.22.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 11:22:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1706556153; x=1707160953; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VJNXAbxh5J4Ei6H86PyidDozdFrMhcx4WIs/J6XrOAs=; b=Bi2GUebO2r4Zhsde9pV0zSsb/gZloOhHpxOJWEppb2C/PDC5znpA2sgdAkD056Gai6 4PIBqQMV1Fd0DmEnN89b247GFNsaX+VaiSlcfDVaK5Ftpj3bWYkSds1tadtDrmyxjeGj N4/yHI2Jne9DFO+Wd6/l4Toxz/bXye+D3TnJ49qtZCuiUKlm7Y1Kc03w4ADOBdLcDa7f zNGRp9imkj5cLZSGps7G5CmdndYfKQHyTp96ZXPu0csmApUe5M1rJ9qGbCx357S6UBK9 EiPew0xNQ5sBwwICLCE2xPdb7SPNOP+32xba8A8bZ1TcrJVBT/ZK5WpEJ0+YksuwVev5 NZoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706556153; x=1707160953; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VJNXAbxh5J4Ei6H86PyidDozdFrMhcx4WIs/J6XrOAs=; b=Dg4KTB+uB6A0fheeO0mgF6EBRLpXC/7tp/F9DHFKBwg2yollr5YeTGUKN+8b/nwYJr PADuEY7X+hPNjyDMb/Wa6LxhbxaUbgiFzen2giYyvH4FnB6cqZBdynCtoy6yaI4GkvZq 2EwiNDMFf/M8K3brudTXPBww+YxtAFN6WP5peOV2XsRZQAGRZ7lO8TVMRtFsGIxqxAuv i4CQEqWBigvSmzmR9C2tqW/j95MxnXa1nLPAuCyesBvbga+tdtffQjoGBDnRF21gYe4l fWMd7gJicOYoCmkwQyn2Rr7J5G5fxrGs+WXFBqCK3YPlK1YnOjm6iRY8RK59F+Z3JYQV gG9g== X-Gm-Message-State: AOJu0YwLzZRj3n2Ba9I0p4Sp4iI1OQ6eG4iQCtEhomnmlgF4xbG/0pLZ 8Gr992VNgm+7VYuKYhGTxdt0XYMcluLzy2FnzXYfNhtntk7Svms0 X-Google-Smtp-Source: AGHT+IGxuB62qroUeNlwchOrWD4MWwf8zESQy6+5hkXe5W2F4Tg/4m9+wKTXWum8C/7h8moCHMVPhQ== X-Received: by 2002:a5d:510f:0:b0:33a:e7de:aa8b with SMTP id s15-20020a5d510f000000b0033ae7deaa8bmr3156503wrt.26.1706556152879; Mon, 29 Jan 2024 11:22:32 -0800 (PST) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v5 4/6] target/riscv: Add pointer masking tb flags Date: Mon, 29 Jan 2024 19:22:05 +0000 Message-Id: <20240129192207.2946870-5-me@deliversmonkey.space> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129192207.2946870-1-me@deliversmonkey.space> References: <20240129192207.2946870-1-me@deliversmonkey.space> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=baturo.alexey@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1706556250743100001 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 +++++ 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1c8979c1c8..0284ea418f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -545,6 +545,9 @@ FIELD(TB_FLAGS, ITRIGGER, 20, 1) FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) FIELD(TB_FLAGS, PRIV, 22, 2) FIELD(TB_FLAGS, AXL, 24, 2) +/* If pointer masking should be applied and address sign extended */ +FIELD(TB_FLAGS, PM_PMM, 26, 2) +FIELD(TB_FLAGS, PM_SIGNEXTEND, 28, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9640e4c2c5..67bc51e510 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -68,6 +68,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, RISCVCPU *cpu =3D env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags =3D 0; + bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); =20 *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base =3D 0; @@ -135,6 +136,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); =20 *pflags =3D flags; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6b4b9a671c..2c89d749c0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -103,6 +103,9 @@ typedef struct DisasContext { bool vl_eq_vlmax; CPUState *cs; TCGv zero; + /* actual address width */ + uint8_t addr_width; + bool addr_signed; /* Use icount trigger for native debug */ bool itrigger; /* FRM is known to contain a valid value. */ @@ -1176,6 +1179,8 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs =3D cs; + ctx->addr_width =3D 0; + ctx->addr_signed =3D false; ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; --=20 2.34.1