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Mon, 29 Jan 2024 08:46:09 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Alexander Graf Subject: [PATCH v3 08/29] target/arm: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:44:50 +0100 Message-ID: <20240129164514.73104-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22a; envelope-from=philmd@linaro.org; helo=mail-lj1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706547400880100005 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_cpuif.c | 7 ++----- hw/intc/arm_gicv3_cpuif_common.c | 5 +---- target/arm/cpu.c | 19 +++++-------------- target/arm/debug_helper.c | 8 ++------ target/arm/gdbstub.c | 6 ++---- target/arm/gdbstub64.c | 6 ++---- target/arm/helper.c | 9 +++------ target/arm/hvf/hvf.c | 12 ++++-------- target/arm/kvm.c | 3 +-- target/arm/ptw.c | 3 +-- target/arm/tcg/cpu32.c | 4 +--- target/arm/tcg/translate.c | 3 +-- 12 files changed, 25 insertions(+), 60 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index e1a60d8c15..80f64a5154 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -182,8 +182,6 @@ static int hppvi_index(GICv3CPUState *cs) * priority than the highest priority list register at every * callsite of HighestPriorityVirtualInterrupt; we check it here.) */ - ARMCPU *cpu =3D ARM_CPU(cs->cpu); - CPUARMState *env =3D &cpu->env; int idx =3D -1; int i; /* Note that a list register entry with a priority of 0xff will @@ -230,7 +228,7 @@ static int hppvi_index(GICv3CPUState *cs) * fails the priority check here. vLPIs are only considered * when we are in Non-Secure state. */ - if (cs->hppvlpi.prio < prio && !arm_is_secure(env)) { + if (cs->hppvlpi.prio < prio && !arm_is_secure(cpu_env(cs->cpu))) { if (cs->hppvlpi.grp =3D=3D GICV3_G0) { if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0) { return HPPVI_INDEX_VLPI; @@ -931,8 +929,7 @@ void gicv3_cpuif_update(GICv3CPUState *cs) /* Tell the CPU about its highest priority pending interrupt */ int irqlevel =3D 0; int fiqlevel =3D 0; - ARMCPU *cpu =3D ARM_CPU(cs->cpu); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs->cpu); =20 g_assert(bql_locked()); =20 diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_com= mon.c index ff1239f65d..bab3c3cdbd 100644 --- a/hw/intc/arm_gicv3_cpuif_common.c +++ b/hw/intc/arm_gicv3_cpuif_common.c @@ -15,8 +15,5 @@ =20 void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) { - ARMCPU *arm_cpu =3D ARM_CPU(cpu); - CPUARMState *env =3D &arm_cpu->env; - - env->gicv3state =3D (void *)s; + cpu_env(cpu)->gicv3state =3D (void *)s; }; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e5deb5195b..23f4de127f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -53,8 +53,7 @@ =20 static void arm_cpu_set_pc(CPUState *cs, vaddr value) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); =20 if (is_a64(env)) { env->pc =3D value; @@ -67,8 +66,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) =20 static vaddr arm_cpu_get_pc(CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); =20 if (is_a64(env)) { return env->pc; @@ -996,19 +994,15 @@ static void arm_cpu_kvm_set_irq(void *opaque, int irq= , int level) =20 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - cpu_synchronize_state(cs); - return arm_cpu_data_is_big_endian(env); + return arm_cpu_data_is_big_endian(cpu_env(cs)); } =20 #endif =20 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) { - ARMCPU *ac =3D ARM_CPU(cpu); - CPUARMState *env =3D &ac->env; + CPUARMState *env =3D cpu_env(cpu); bool sctlr_b; =20 if (is_a64(env)) { @@ -2435,10 +2429,7 @@ static Property arm_cpu_properties[] =3D { =20 static const gchar *arm_gdb_arch_name(CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { + if (arm_feature(cpu_env(cs), ARM_FEATURE_IWMMXT)) { return "iwmmxt"; } return "arm"; diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 7d856acddf..7bd5467414 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -468,8 +468,7 @@ void arm_debug_excp_handler(CPUState *cs) * Called by core code when a watchpoint or breakpoint fires; * need to check which one and raise the appropriate exception. */ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); CPUWatchpoint *wp_hit =3D cs->watchpoint_hit; =20 if (wp_hit) { @@ -757,9 +756,6 @@ void hw_breakpoint_update_all(ARMCPU *cpu) =20 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - /* * In BE32 system mode, target memory is stored byteswapped (on a * little-endian host system), and by the time we reach here (via an @@ -767,7 +763,7 @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr= addr, int len) * to account for that, which means that watchpoints will not match. * Undo the adjustment here. */ - if (arm_sctlr_b(env)) { + if (arm_sctlr_b(cpu_env(cs))) { if (len =3D=3D 1) { addr ^=3D 3; } else if (len =3D=3D 2) { diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 28f546a5ff..dc6c29669c 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -40,8 +40,7 @@ typedef struct RegisterSysregXmlParam { =20 int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); =20 if (n < 16) { /* Core integer register. */ @@ -61,8 +60,7 @@ int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *m= em_buf, int n) =20 int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); uint32_t tmp; =20 tmp =3D ldl_p(mem_buf); diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index d7b79a6589..b9f29b0a60 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -24,8 +24,7 @@ =20 int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); =20 if (n < 31) { /* Core integer register. */ @@ -45,8 +44,7 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArra= y *mem_buf, int n) =20 int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); uint64_t tmp; =20 tmp =3D ldq_p(mem_buf); diff --git a/target/arm/helper.c b/target/arm/helper.c index 945d8571a6..a9d2c23df2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10902,8 +10902,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUSta= te *cs) * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. */ uint32_t addr, mask; - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); =20 switch (cs->exception_index) { case EXCP_UDEF: @@ -10981,8 +10980,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUSta= te *cs) =20 static void arm_cpu_do_interrupt_aarch32(CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); uint32_t addr; uint32_t mask; int new_mode; @@ -11481,8 +11479,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) #ifdef CONFIG_TCG static void tcg_handle_semihosting(CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); =20 if (is_a64(env)) { qemu_log_mask(CPU_LOG_INT, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index e5f0f60093..849f0772e6 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1006,8 +1006,7 @@ void hvf_kick_vcpu_thread(CPUState *cpu) static void hvf_raise_exception(CPUState *cpu, uint32_t excp, uint32_t syndrome) { - ARMCPU *arm_cpu =3D ARM_CPU(cpu); - CPUARMState *env =3D &arm_cpu->env; + CPUARMState *env =3D cpu_env(cpu); =20 cpu->exception_index =3D excp; env->exception.target_el =3D 1; @@ -1485,8 +1484,7 @@ static bool hvf_sysreg_write_cp(CPUState *cpu, uint32= _t reg, uint64_t val) =20 static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) { - ARMCPU *arm_cpu =3D ARM_CPU(cpu); - CPUARMState *env =3D &arm_cpu->env; + CPUARMState *env =3D cpu_env(cpu); =20 trace_hvf_sysreg_write(reg, SYSREG_OP0(reg), @@ -2152,8 +2150,7 @@ static void hvf_put_gdbstub_debug_registers(CPUState = *cpu) */ static void hvf_put_guest_debug_registers(CPUState *cpu) { - ARMCPU *arm_cpu =3D ARM_CPU(cpu); - CPUARMState *env =3D &arm_cpu->env; + CPUARMState *env =3D cpu_env(cpu); hv_return_t r =3D HV_SUCCESS; int i; =20 @@ -2207,8 +2204,7 @@ static void hvf_arch_set_traps(void) =20 void hvf_arch_update_guest_debug(CPUState *cpu) { - ARMCPU *arm_cpu =3D ARM_CPU(cpu); - CPUARMState *env =3D &arm_cpu->env; + CPUARMState *env =3D cpu_env(cpu); =20 /* Check whether guest debugging is enabled */ cpu->accel->guest_debug_enabled =3D cpu->singlestep_enabled || diff --git a/target/arm/kvm.c b/target/arm/kvm.c index ab85d628a8..cccb512f23 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1958,8 +1958,7 @@ int kvm_arch_destroy_vcpu(CPUState *cs) /* Callers must hold the iothread mutex lock */ static void kvm_inject_arm_sea(CPUState *c) { - ARMCPU *cpu =3D ARM_CPU(c); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(c); uint32_t esr; bool same_el; =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5eb3577bcd..57a761ad68 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3528,8 +3528,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); ARMSecuritySpace ss =3D arm_security_space(env); S1Translate ptw =3D { diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index d9e0e2a4dd..e96f1119c0 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -102,8 +102,6 @@ void aa32_max_features(ARMCPU *cpu) static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; bool ret =3D false; =20 /* @@ -115,7 +113,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, in= t interrupt_request) * currently active exception). */ if (interrupt_request & CPU_INTERRUPT_HARD - && (armv7m_nvic_can_take_pending_exception(env->nvic))) { + && (armv7m_nvic_can_take_pending_exception(cpu_env(cs)->nvic))) { cs->exception_index =3D EXCP_IRQ; cc->tcg_ops->do_interrupt(cs); ret =3D true; diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index b3660173d1..ab73250f04 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -9326,7 +9326,6 @@ static void arm_post_translate_insn(DisasContext *dc) static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUARMState *env =3D cpu_env(cpu); uint32_t pc =3D dc->base.pc_next; unsigned int insn; =20 @@ -9356,7 +9355,7 @@ static void arm_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cpu) } =20 dc->pc_curr =3D pc; - insn =3D arm_ldl_code(env, &dc->base, pc, dc->sctlr_b); + insn =3D arm_ldl_code(cpu_env(cpu), &dc->base, pc, dc->sctlr_b); dc->insn =3D insn; dc->base.pc_next =3D pc + 4; disas_arm_insn(dc, insn); --=20 2.41.0