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Mon, 29 Jan 2024 08:46:03 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 07/29] target/alpha: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:44:49 +0100 Message-ID: <20240129164514.73104-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706547416452100003 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/cpu.c | 31 +++++++------------------------ target/alpha/gdbstub.c | 6 ++---- target/alpha/helper.c | 15 +++++---------- target/alpha/mem_helper.c | 11 +++-------- target/alpha/translate.c | 4 ++-- 5 files changed, 19 insertions(+), 48 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b8ed29e343..e21a8936c7 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -130,40 +130,27 @@ static ObjectClass *alpha_cpu_class_by_name(const cha= r *cpu_model) =20 static void ev4_cpu_initfn(Object *obj) { - AlphaCPU *cpu =3D ALPHA_CPU(obj); - CPUAlphaState *env =3D &cpu->env; - - env->implver =3D IMPLVER_2106x; + cpu_env(CPU(obj))->implver =3D IMPLVER_2106x; } =20 static void ev5_cpu_initfn(Object *obj) { - AlphaCPU *cpu =3D ALPHA_CPU(obj); - CPUAlphaState *env =3D &cpu->env; - - env->implver =3D IMPLVER_21164; + cpu_env(CPU(obj))->implver =3D IMPLVER_21164; } =20 static void ev56_cpu_initfn(Object *obj) { - AlphaCPU *cpu =3D ALPHA_CPU(obj); - CPUAlphaState *env =3D &cpu->env; - - env->amask |=3D AMASK_BWX; + cpu_env(CPU(obj))->amask |=3D AMASK_BWX; } =20 static void pca56_cpu_initfn(Object *obj) { - AlphaCPU *cpu =3D ALPHA_CPU(obj); - CPUAlphaState *env =3D &cpu->env; - - env->amask |=3D AMASK_MVI; + cpu_env(CPU(obj))->amask |=3D AMASK_MVI; } =20 static void ev6_cpu_initfn(Object *obj) { - AlphaCPU *cpu =3D ALPHA_CPU(obj); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(CPU(obj)); =20 env->implver =3D IMPLVER_21264; env->amask =3D AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP; @@ -171,16 +158,12 @@ static void ev6_cpu_initfn(Object *obj) =20 static void ev67_cpu_initfn(Object *obj) { - AlphaCPU *cpu =3D ALPHA_CPU(obj); - CPUAlphaState *env =3D &cpu->env; - - env->amask |=3D AMASK_CIX | AMASK_PREFETCH; + cpu_env(CPU(obj))->amask |=3D AMASK_CIX | AMASK_PREFETCH; } =20 static void alpha_cpu_initfn(Object *obj) { - AlphaCPU *cpu =3D ALPHA_CPU(obj); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(CPU(obj)); =20 env->lock_addr =3D -1; #if defined(CONFIG_USER_ONLY) diff --git a/target/alpha/gdbstub.c b/target/alpha/gdbstub.c index 0f8fa150f8..13694fd321 100644 --- a/target/alpha/gdbstub.c +++ b/target/alpha/gdbstub.c @@ -23,8 +23,7 @@ =20 int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); uint64_t val; CPU_DoubleU d; =20 @@ -59,8 +58,7 @@ int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) =20 int alpha_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); target_ulong tmp =3D ldtul_p(mem_buf); CPU_DoubleU d; =20 diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 970c869771..d6d4353edd 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -286,11 +286,10 @@ static int get_physical_address(CPUAlphaState *env, t= arget_ulong addr, =20 hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); target_ulong phys; int prot, fail; =20 - fail =3D get_physical_address(&cpu->env, addr, 0, 0, &phys, &prot); + fail =3D get_physical_address(cpu_env(cs), addr, 0, 0, &phys, &prot); return (fail >=3D 0 ? -1 : phys); } =20 @@ -298,8 +297,7 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int s= ize, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); target_ulong phys; int prot, fail; =20 @@ -325,8 +323,7 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int s= ize, =20 void alpha_cpu_do_interrupt(CPUState *cs) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); int i =3D cs->exception_index; =20 if (qemu_loglevel_mask(CPU_LOG_INT)) { @@ -435,8 +432,7 @@ void alpha_cpu_do_interrupt(CPUState *cs) =20 bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); int idx =3D -1; =20 /* We never take interrupts while in PALmode. */ @@ -487,8 +483,7 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", "t10", "t11", "ra", "t12", "at", "gp", "sp" }; - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); int i; =20 qemu_fprintf(f, "PC " TARGET_FMT_lx " PS %02x\n", diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index a39b52c5dd..872955f5e7 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -42,18 +42,14 @@ static void do_unaligned_access(CPUAlphaState *env, vad= dr addr, uintptr_t retadd void alpha_cpu_record_sigbus(CPUState *cs, vaddr addr, MMUAccessType access_type, uintptr_t retaddr) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; - - do_unaligned_access(env, addr, retaddr); + do_unaligned_access(cpu_env(cs), addr, retaddr); } #else void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); =20 do_unaligned_access(env, addr, retaddr); cs->exception_index =3D EXCP_UNALIGN; @@ -67,8 +63,7 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retad= dr) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); =20 env->trap_arg0 =3D addr; env->trap_arg1 =3D access_type =3D=3D MMU_DATA_STORE ? 1 : 0; diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 32333081d8..d1188194ba 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2917,8 +2917,8 @@ static void alpha_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUAlphaState *env =3D cpu_env(cpu); - uint32_t insn =3D translator_ldl(env, &ctx->base, ctx->base.pc_next); + uint32_t insn =3D translator_ldl(cpu_env(cpu), &ctx->base, + ctx->base.pc_next); =20 ctx->base.pc_next +=3D 4; ctx->base.is_jmp =3D translate_one(ctx, insn); --=20 2.41.0