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Iglesias" , Brian Cain , Song Gao , Laurent Vivier , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Yoshinori Sato , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov Subject: [PATCH v3 06/29] target: Replace CPU_GET_CLASS(cpu -> obj) in cpu_reset_hold() handler Date: Mon, 29 Jan 2024 17:44:48 +0100 Message-ID: <20240129164514.73104-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706546897165100002 Since CPU() macro is a simple cast, the following are equivalent: Object *obj; CPUState *cs =3D CPU(obj) In order to ease static analysis when running scripts/coccinelle/cpu_env.cocci from the previous commit, replace: - CPU_GET_CLASS(cpu); + CPU_GET_CLASS(obj); Most code use the 'cs' variable name for CPUState handle. Replace few 's' -> 'cs' to unify cpu_reset_hold() style. No logical change in this patch. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Richard Henderson --- target/arm/cpu.c | 14 +++++++------- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hexagon/cpu.c | 2 +- target/i386/cpu.c | 14 +++++++------- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 6 +++--- target/microblaze/cpu.c | 6 +++--- target/mips/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 8 ++++---- target/ppc/cpu_init.c | 12 ++++++------ target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/sh4/cpu.c | 6 +++--- target/sparc/cpu.c | 6 +++--- target/tricore/cpu.c | 6 +++--- target/xtensa/cpu.c | 8 ++++---- 18 files changed, 51 insertions(+), 51 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 60ab8f3242..e5deb5195b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -209,9 +209,9 @@ static void cp_reg_check_reset(gpointer key, gpointer v= alue, gpointer opaque) =20 static void arm_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - ARMCPU *cpu =3D ARM_CPU(s); - ARMCPUClass *acc =3D ARM_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + ARMCPU *cpu =3D ARM_CPU(cs); + ARMCPUClass *acc =3D ARM_CPU_GET_CLASS(obj); CPUARMState *env =3D &cpu->env; =20 if (acc->parent_phases.hold) { @@ -228,7 +228,7 @@ static void arm_cpu_reset_hold(Object *obj) env->vfp.xregs[ARM_VFP_MVFR1] =3D cpu->isar.mvfr1; env->vfp.xregs[ARM_VFP_MVFR2] =3D cpu->isar.mvfr2; =20 - cpu->power_state =3D s->start_powered_off ? PSCI_OFF : PSCI_ON; + cpu->power_state =3D cs->start_powered_off ? PSCI_OFF : PSCI_ON; =20 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { env->iwmmxt.cregs[ARM_IWMMXT_wCID] =3D 0x69051000 | 'Q'; @@ -433,7 +433,7 @@ static void arm_cpu_reset_hold(Object *obj) =20 /* Load the initial SP and PC from offset 0 and 4 in the vector ta= ble */ vecbase =3D env->v7m.vecbase[env->v7m.secure]; - rom =3D rom_ptr_for_as(s->as, vecbase, 8); + rom =3D rom_ptr_for_as(cs->as, vecbase, 8); if (rom) { /* Address zero is covered by ROM which hasn't yet been * copied into physical memory. @@ -446,8 +446,8 @@ static void arm_cpu_reset_hold(Object *obj) * it got copied into memory. In the latter case, rom_ptr * will return a NULL pointer and we should use ldl_phys inste= ad. */ - initial_msp =3D ldl_phys(s->as, vecbase); - initial_pc =3D ldl_phys(s->as, vecbase + 4); + initial_msp =3D ldl_phys(cs->as, vecbase); + initial_pc =3D ldl_phys(cs->as, vecbase + 4); } =20 qemu_log_mask(CPU_LOG_INT, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index f5cbdc4a8c..0f191a4c9d 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -74,7 +74,7 @@ static void avr_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); AVRCPU *cpu =3D AVR_CPU(cs); - AVRCPUClass *mcc =3D AVR_CPU_GET_CLASS(cpu); + AVRCPUClass *mcc =3D AVR_CPU_GET_CLASS(obj); CPUAVRState *env =3D &cpu->env; =20 if (mcc->parent_phases.hold) { diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 9ba08e8b0c..4187e0ef3c 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -60,7 +60,7 @@ static void cris_cpu_reset_hold(Object *obj) { CPUState *s =3D CPU(obj); CRISCPU *cpu =3D CRIS_CPU(s); - CRISCPUClass *ccc =3D CRIS_CPU_GET_CLASS(cpu); + CRISCPUClass *ccc =3D CRIS_CPU_GET_CLASS(obj); CPUCRISState *env =3D &cpu->env; uint32_t vr; =20 diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index c0cd739e15..085d6c0115 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -289,7 +289,7 @@ static void hexagon_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); HexagonCPU *cpu =3D HEXAGON_CPU(cs); - HexagonCPUClass *mcc =3D HEXAGON_CPU_GET_CLASS(cpu); + HexagonCPUClass *mcc =3D HEXAGON_CPU_GET_CLASS(obj); CPUHexagonState *env =3D &cpu->env; =20 if (mcc->parent_phases.hold) { diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 03822d9ba8..66345c204a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6690,9 +6690,9 @@ static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *= env) =20 static void x86_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - X86CPU *cpu =3D X86_CPU(s); - X86CPUClass *xcc =3D X86_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + X86CPU *cpu =3D X86_CPU(cs); + X86CPUClass *xcc =3D X86_CPU_GET_CLASS(obj); CPUX86State *env =3D &cpu->env; target_ulong cr4; uint64_t xcr0; @@ -6780,8 +6780,8 @@ static void x86_cpu_reset_hold(Object *obj) memset(env->dr, 0, sizeof(env->dr)); env->dr[6] =3D DR6_FIXED_1; env->dr[7] =3D DR7_FIXED_1; - cpu_breakpoint_remove_all(s, BP_CPU); - cpu_watchpoint_remove_all(s, BP_CPU); + cpu_breakpoint_remove_all(cs, BP_CPU); + cpu_watchpoint_remove_all(cs, BP_CPU); =20 cr4 =3D 0; xcr0 =3D XSTATE_FP_MASK; @@ -6832,9 +6832,9 @@ static void x86_cpu_reset_hold(Object *obj) env->triple_fault_pending =3D false; #if !defined(CONFIG_USER_ONLY) /* We hard-wire the BSP to the first CPU. */ - apic_designate_bsp(cpu->apic_state, s->cpu_index =3D=3D 0); + apic_designate_bsp(cpu->apic_state, cs->cpu_index =3D=3D 0); =20 - s->halted =3D !cpu_is_bsp(cpu); + cs->halted =3D !cpu_is_bsp(cpu); =20 if (kvm_enabled()) { kvm_arch_reset_vcpu(cpu); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 064540397d..3094bbc0d9 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -500,7 +500,7 @@ static void loongarch_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - LoongArchCPUClass *lacc =3D LOONGARCH_CPU_GET_CLASS(cpu); + LoongArchCPUClass *lacc =3D LOONGARCH_CPU_GET_CLASS(obj); CPULoongArchState *env =3D &cpu->env; =20 if (lacc->parent_phases.hold) { diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 1421e77c2c..4d14d04c33 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -68,9 +68,9 @@ static void m68k_unset_feature(CPUM68KState *env, int fea= ture) =20 static void m68k_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - M68kCPU *cpu =3D M68K_CPU(s); - M68kCPUClass *mcc =3D M68K_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + M68kCPU *cpu =3D M68K_CPU(cs); + M68kCPUClass *mcc =3D M68K_CPU_GET_CLASS(obj); CPUM68KState *env =3D &cpu->env; floatx80 nan =3D floatx80_default_nan(NULL); int i; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bbb3335cad..6d4b7c2c8f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -167,9 +167,9 @@ static void microblaze_cpu_set_irq(void *opaque, int ir= q, int level) =20 static void mb_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(s); - MicroBlazeCPUClass *mcc =3D MICROBLAZE_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + MicroBlazeCPUClass *mcc =3D MICROBLAZE_CPU_GET_CLASS(obj); CPUMBState *env =3D &cpu->env; =20 if (mcc->parent_phases.hold) { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a0023edd43..6ced52f985 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -188,7 +188,7 @@ static void mips_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); MIPSCPU *cpu =3D MIPS_CPU(cs); - MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(cpu); + MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(obj); CPUMIPSState *env =3D &cpu->env; =20 if (mcc->parent_phases.hold) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index a27732bf2b..09b122e24d 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -61,7 +61,7 @@ static void nios2_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); Nios2CPU *cpu =3D NIOS2_CPU(cs); - Nios2CPUClass *ncc =3D NIOS2_CPU_GET_CLASS(cpu); + Nios2CPUClass *ncc =3D NIOS2_CPU_GET_CLASS(obj); CPUNios2State *env =3D &cpu->env; =20 if (ncc->parent_phases.hold) { diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 381ebe00d3..0fdadf9e55 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -75,9 +75,9 @@ static void openrisc_disas_set_info(CPUState *cpu, disass= emble_info *info) =20 static void openrisc_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - OpenRISCCPU *cpu =3D OPENRISC_CPU(s); - OpenRISCCPUClass *occ =3D OPENRISC_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); + OpenRISCCPUClass *occ =3D OPENRISC_CPU_GET_CLASS(obj); =20 if (occ->parent_phases.hold) { occ->parent_phases.hold(obj); @@ -88,7 +88,7 @@ static void openrisc_cpu_reset_hold(Object *obj) cpu->env.pc =3D 0x100; cpu->env.sr =3D SR_FO | SR_SM; cpu->env.lock_addr =3D -1; - s->exception_index =3D -1; + cs->exception_index =3D -1; cpu_set_fpcsr(&cpu->env, 0); =20 set_float_detect_tininess(float_tininess_before_rounding, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 344196a8ce..61b8495a90 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7107,9 +7107,9 @@ static bool ppc_cpu_has_work(CPUState *cs) =20 static void ppc_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - PowerPCCPU *cpu =3D POWERPC_CPU(s); - PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(obj); CPUPPCState *env =3D &cpu->env; target_ulong msr; int i; @@ -7158,8 +7158,8 @@ static void ppc_cpu_reset_hold(Object *obj) env->nip =3D env->hreset_vector | env->excp_prefix; =20 if (tcg_enabled()) { - cpu_breakpoint_remove_all(s, BP_CPU); - cpu_watchpoint_remove_all(s, BP_CPU); + cpu_breakpoint_remove_all(cs, BP_CPU); + cpu_watchpoint_remove_all(cs, BP_CPU); if (env->mmu_model !=3D POWERPC_MMU_REAL) { ppc_tlb_invalidate_all(env); } @@ -7173,7 +7173,7 @@ static void ppc_cpu_reset_hold(Object *obj) env->reserve_addr =3D (target_ulong)-1ULL; /* Be sure no exception or interrupt is pending */ env->pending_interrupts =3D 0; - s->exception_index =3D POWERPC_EXCP_NONE; + cs->exception_index =3D POWERPC_EXCP_NONE; env->error_code =3D 0; ppc_irq_reset(cpu); =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8cbfc7e781..1bd99bc5c6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -875,7 +875,7 @@ static void riscv_cpu_reset_hold(Object *obj) #endif CPUState *cs =3D CPU(obj); RISCVCPU *cpu =3D RISCV_CPU(cs); - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(obj); CPURISCVState *env =3D &cpu->env; =20 if (mcc->parent_phases.hold) { diff --git a/target/rx/cpu.c b/target/rx/cpu.c index c5ffeffe32..58ca26184d 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -67,7 +67,7 @@ static bool rx_cpu_has_work(CPUState *cs) static void rx_cpu_reset_hold(Object *obj) { RXCPU *cpu =3D RX_CPU(obj); - RXCPUClass *rcc =3D RX_CPU_GET_CLASS(cpu); + RXCPUClass *rcc =3D RX_CPU_GET_CLASS(obj); CPURXState *env =3D &cpu->env; uint32_t *resetvec; =20 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 806a0ef875..1b03c7bcb1 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -91,9 +91,9 @@ static bool superh_cpu_has_work(CPUState *cs) =20 static void superh_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - SuperHCPU *cpu =3D SUPERH_CPU(s); - SuperHCPUClass *scc =3D SUPERH_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + SuperHCPU *cpu =3D SUPERH_CPU(cs); + SuperHCPUClass *scc =3D SUPERH_CPU_GET_CLASS(obj); CPUSH4State *env =3D &cpu->env; =20 if (scc->parent_phases.hold) { diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index befa7fc4eb..152bee4f81 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -31,9 +31,9 @@ =20 static void sparc_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - SPARCCPU *cpu =3D SPARC_CPU(s); - SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + SPARCCPU *cpu =3D SPARC_CPU(cs); + SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(obj); CPUSPARCState *env =3D &cpu->env; =20 if (scc->parent_phases.hold) { diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 8acacdf0c0..9bdaa1593a 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -72,9 +72,9 @@ static void tricore_restore_state_to_opc(CPUState *cs, =20 static void tricore_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - TriCoreCPU *cpu =3D TRICORE_CPU(s); - TriCoreCPUClass *tcc =3D TRICORE_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + TriCoreCPU *cpu =3D TRICORE_CPU(cs); + TriCoreCPUClass *tcc =3D TRICORE_CPU_GET_CLASS(obj); CPUTriCoreState *env =3D &cpu->env; =20 if (tcc->parent_phases.hold) { diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 99c0ca130f..ce044466ad 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -90,9 +90,9 @@ bool xtensa_abi_call0(void) =20 static void xtensa_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - XtensaCPU *cpu =3D XTENSA_CPU(s); - XtensaCPUClass *xcc =3D XTENSA_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + XtensaCPU *cpu =3D XTENSA_CPU(cs); + XtensaCPUClass *xcc =3D XTENSA_CPU_GET_CLASS(obj); CPUXtensaState *env =3D &cpu->env; bool dfpu =3D xtensa_option_enabled(env->config, XTENSA_OPTION_DFP_COPROCESSOR); @@ -127,7 +127,7 @@ static void xtensa_cpu_reset_hold(Object *obj) =20 #ifndef CONFIG_USER_ONLY reset_mmu(env); - s->halted =3D env->runstall; + cs->halted =3D env->runstall; #endif set_no_signaling_nans(!dfpu, &env->fp_status); set_use_first_nan(!dfpu, &env->fp_status); --=20 2.41.0