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Mon, 29 Jan 2024 08:47:57 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH v3 26/29] target/sparc: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:45:08 +0100 Message-ID: <20240129164514.73104-27-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706547235856100001 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Mark Cave-Ayland --- target/sparc/cpu.c | 17 +++++------------ target/sparc/gdbstub.c | 3 +-- target/sparc/int32_helper.c | 3 +-- target/sparc/int64_helper.c | 3 +-- target/sparc/ldst_helper.c | 6 ++---- target/sparc/mmu_helper.c | 15 +++++---------- target/sparc/translate.c | 9 +++------ 7 files changed, 18 insertions(+), 38 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 152bee4f81..72a9b9a285 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -32,9 +32,8 @@ static void sparc_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); - SPARCCPU *cpu =3D SPARC_CPU(cs); SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(obj); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); =20 if (scc->parent_phases.hold) { scc->parent_phases.hold(obj); @@ -83,8 +82,7 @@ static void sparc_cpu_reset_hold(Object *obj) static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); =20 if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) { int pil =3D env->interrupt_index & 0xf; @@ -613,8 +611,7 @@ static void cpu_print_cc(FILE *f, uint32_t cc) =20 static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); int i, x; =20 qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env= ->pc, @@ -711,11 +708,8 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, =20 static bool sparc_cpu_has_work(CPUState *cs) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; - return (cs->interrupt_request & CPU_INTERRUPT_HARD) && - cpu_interrupts_enabled(env); + cpu_interrupts_enabled(cpu_env(cs)); } =20 static char *sparc_cpu_type_name(const char *cpu_model) @@ -749,8 +743,7 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error= **errp) CPUState *cs =3D CPU(dev); SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(dev); Error *local_err =3D NULL; - SPARCCPU *cpu =3D SPARC_CPU(dev); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); =20 #if defined(CONFIG_USER_ONLY) /* We are emulating the kernel, which will trap and emulate float128. = */ diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index a1c8fdc4d5..5257c49a0d 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -29,8 +29,7 @@ =20 int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); =20 if (n < 8) { /* g0..g7 */ diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index 058dd712b5..6b7d65b031 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -99,8 +99,7 @@ void cpu_check_irqs(CPUSPARCState *env) =20 void sparc_cpu_do_interrupt(CPUState *cs) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); int cwp, intno =3D cs->exception_index; =20 if (qemu_loglevel_mask(CPU_LOG_INT)) { diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c index 27df9dba89..bd14c7a0db 100644 --- a/target/sparc/int64_helper.c +++ b/target/sparc/int64_helper.c @@ -130,8 +130,7 @@ void cpu_check_irqs(CPUSPARCState *env) =20 void sparc_cpu_do_interrupt(CPUState *cs) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); int intno =3D cs->exception_index; trap_state *tsptr; =20 diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 09066d5487..203441bfb2 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -421,8 +421,7 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr = addr, bool is_write, bool is_exec, int is_asi, unsigned size, uintptr_t retaddr) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); int fault_type; =20 #ifdef DEBUG_UNASSIGNED @@ -483,8 +482,7 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr = addr, bool is_write, bool is_exec, int is_asi, unsigned size, uintptr_t retaddr) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); =20 #ifdef DEBUG_UNASSIGNED printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_= lx diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 453498c670..a05ee22315 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -206,8 +206,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); CPUTLBEntryFull full =3D {}; target_ulong vaddr; int error_code =3D 0, access_index; @@ -391,8 +390,7 @@ void dump_mmu(CPUSPARCState *env) int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, int len, bool is_write) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); target_ulong addr =3D address; int i; int len1; @@ -759,8 +757,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); CPUTLBEntryFull full =3D {}; int error_code =3D 0, access_index; =20 @@ -898,8 +895,7 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, ta= rget_ulong addr, =20 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); hwaddr phys_addr; int mmu_idx =3D cpu_mmu_index(env, false); =20 @@ -916,8 +912,7 @@ G_NORETURN void sparc_cpu_do_unaligned_access(CPUState = *cs, vaddr addr, int mmu_idx, uintptr_t retaddr) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); =20 #ifdef TARGET_SPARC64 env->dmmu.sfsr =3D build_sfsr(env, mmu_idx, access_type); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9387299559..769418d6b0 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5154,13 +5154,12 @@ TRANS(FCMPEq, ALL, do_fcmpq, a, true) static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUSPARCState *env =3D cpu_env(cs); int bound; =20 dc->pc =3D dc->base.pc_first; dc->npc =3D (target_ulong)dc->base.tb->cs_base; dc->mem_idx =3D dc->base.tb->flags & TB_FLAG_MMU_MASK; - dc->def =3D &env->def; + dc->def =3D &cpu_env(cs)->def; dc->fpu_enabled =3D tb_fpu_enabled(dc->base.tb->flags); dc->address_mask_32bit =3D tb_am_enabled(dc->base.tb->flags); #ifndef CONFIG_USER_ONLY @@ -5210,10 +5209,9 @@ static void sparc_tr_insn_start(DisasContextBase *dc= base, CPUState *cs) static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUSPARCState *env =3D cpu_env(cs); unsigned int insn; =20 - insn =3D translator_ldl(env, &dc->base, dc->pc); + insn =3D translator_ldl(cpu_env(cs), &dc->base, dc->pc); dc->base.pc_next +=3D 4; =20 if (!decode(dc, insn)) { @@ -5406,8 +5404,7 @@ void sparc_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); target_ulong pc =3D data[0]; target_ulong npc =3D data[1]; =20 --=20 2.41.0