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Mon, 29 Jan 2024 08:47:51 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato Subject: [PATCH v3 25/29] target/sh4: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:45:07 +0100 Message-ID: <20240129164514.73104-26-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706546975167100001 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/sh4/cpu.c | 18 ++++++------------ target/sh4/gdbstub.c | 6 ++---- target/sh4/helper.c | 14 ++++---------- target/sh4/translate.c | 6 ++---- 4 files changed, 14 insertions(+), 30 deletions(-) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 1b03c7bcb1..3308a2be07 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -71,8 +71,7 @@ static void superh_restore_state_to_opc(CPUState *cs, static bool superh_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(cs); =20 if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND)) && !(cs->tcg_cflags & CF_PCREL) && env->pc !=3D tb->pc) { @@ -92,9 +91,8 @@ static bool superh_cpu_has_work(CPUState *cs) static void superh_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); - SuperHCPU *cpu =3D SUPERH_CPU(cs); SuperHCPUClass *scc =3D SUPERH_CPU_GET_CLASS(obj); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(cs); =20 if (scc->parent_phases.hold) { scc->parent_phases.hold(obj); @@ -144,8 +142,7 @@ out: =20 static void sh7750r_cpu_initfn(Object *obj) { - SuperHCPU *cpu =3D SUPERH_CPU(obj); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(CPU(obj)); =20 env->id =3D SH_CPU_SH7750R; env->features =3D SH_FEATURE_BCR3_AND_BCR4; @@ -162,8 +159,7 @@ static void sh7750r_class_init(ObjectClass *oc, void *d= ata) =20 static void sh7751r_cpu_initfn(Object *obj) { - SuperHCPU *cpu =3D SUPERH_CPU(obj); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(CPU(obj)); =20 env->id =3D SH_CPU_SH7751R; env->features =3D SH_FEATURE_BCR3_AND_BCR4; @@ -180,8 +176,7 @@ static void sh7751r_class_init(ObjectClass *oc, void *d= ata) =20 static void sh7785_cpu_initfn(Object *obj) { - SuperHCPU *cpu =3D SUPERH_CPU(obj); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(CPU(obj)); =20 env->id =3D SH_CPU_SH7785; env->features =3D SH_FEATURE_SH4A; @@ -216,8 +211,7 @@ static void superh_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 static void superh_cpu_initfn(Object *obj) { - SuperHCPU *cpu =3D SUPERH_CPU(obj); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(CPU(obj)); =20 env->movcal_backup_tail =3D &(env->movcal_backup); } diff --git a/target/sh4/gdbstub.c b/target/sh4/gdbstub.c index d8e199fc06..75926d4e04 100644 --- a/target/sh4/gdbstub.c +++ b/target/sh4/gdbstub.c @@ -26,8 +26,7 @@ =20 int superh_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(cs); =20 switch (n) { case 0 ... 7: @@ -76,8 +75,7 @@ int superh_cpu_gdb_read_register(CPUState *cs, GByteArray= *mem_buf, int n) =20 int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(cs); =20 switch (n) { case 0 ... 7: diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 5a6f653c12..7c6f9d374a 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -55,8 +55,7 @@ int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr) =20 void superh_cpu_do_interrupt(CPUState *cs) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(cs); int do_irq =3D cs->interrupt_request & CPU_INTERRUPT_HARD; int do_exp, irq_vector =3D cs->exception_index; =20 @@ -432,11 +431,10 @@ static int get_physical_address(CPUSH4State * env, ta= rget_ulong * physical, =20 hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); target_ulong physical; int prot; =20 - if (get_physical_address(&cpu->env, &physical, &prot, addr, MMU_DATA_L= OAD) + if (get_physical_address(cpu_env(cs), &physical, &prot, addr, MMU_DATA= _LOAD) =3D=3D MMU_OK) { return physical; } @@ -782,11 +780,8 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong = addr) bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; - /* Delay slots are indivisible, ignore interrupts */ - if (env->flags & TB_FLAG_DELAY_SLOT_MASK) { + if (cpu_env(cs)->flags & TB_FLAG_DELAY_SLOT_MASK) { return false; } else { superh_cpu_do_interrupt(cs); @@ -800,8 +795,7 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(cs); int ret; =20 target_ulong physical; diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 81f825f125..d9f222bd15 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -159,8 +159,7 @@ void sh4_translate_init(void) =20 void superh_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(cs); int i; =20 qemu_fprintf(f, "pc=3D0x%08x sr=3D0x%08x pr=3D0x%08x fpscr=3D0x%08x\n", @@ -2186,7 +2185,6 @@ static void decode_gusa(DisasContext *ctx, CPUSH4Stat= e *env) static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUSH4State *env =3D cpu_env(cs); uint32_t tbflags; int bound; =20 @@ -2196,7 +2194,7 @@ static void sh4_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) /* We don't know if the delayed pc came from a dynamic or static branc= h, so assume it is a dynamic branch. */ ctx->delayed_pc =3D -1; /* use delayed pc from env pointer */ - ctx->features =3D env->features; + ctx->features =3D cpu_env(cs)->features; ctx->has_movcal =3D (tbflags & TB_FLAG_PENDING_MOVCA); ctx->gbank =3D ((tbflags & (1 << SR_MD)) && (tbflags & (1 << SR_RB))) * 0x10; --=20 2.41.0