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Mon, 29 Jan 2024 08:47:21 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Stafford Horne Subject: [PATCH v3 20/29] target/openrisc: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:45:02 +0100 Message-ID: <20240129164514.73104-21-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706547368216100001 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/openrisc/gdbstub.c | 6 ++---- target/openrisc/interrupt.c | 6 ++---- target/openrisc/translate.c | 6 ++---- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index d1074a0581..c2a77d5d4d 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -23,8 +23,7 @@ =20 int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int = n) { - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - CPUOpenRISCState *env =3D &cpu->env; + CPUOpenRISCState *env =3D cpu_env(cs); =20 if (n < 32) { return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n)); @@ -48,9 +47,8 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArr= ay *mem_buf, int n) =20 int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); CPUClass *cc =3D CPU_GET_CLASS(cs); - CPUOpenRISCState *env =3D &cpu->env; + CPUOpenRISCState *env =3D cpu_env(cs); uint32_t tmp; =20 if (n > cc->gdb_num_core_regs) { diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index d4fdb8ce8e..b3b5b40577 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -29,8 +29,7 @@ =20 void openrisc_cpu_do_interrupt(CPUState *cs) { - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - CPUOpenRISCState *env =3D &cpu->env; + CPUOpenRISCState *env =3D cpu_env(cs); int exception =3D cs->exception_index; =20 env->epcr =3D env->pc; @@ -105,8 +104,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) =20 bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - CPUOpenRISCState *env =3D &cpu->env; + CPUOpenRISCState *env =3D cpu_env(cs); int idx =3D -1; =20 if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) { diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index ecff4412b7..12899c911d 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1564,8 +1564,7 @@ static void openrisc_tr_insn_start(DisasContextBase *= dcbase, CPUState *cs) static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState = *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - uint32_t insn =3D translator_ldl(&cpu->env, &dc->base, dc->base.pc_nex= t); + uint32_t insn =3D translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_n= ext); =20 if (!decode(dc, insn)) { gen_illegal_exception(dc); @@ -1668,8 +1667,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int *max_insns, =20 void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - CPUOpenRISCState *env =3D &cpu->env; + CPUOpenRISCState *env =3D cpu_env(cs); int i; =20 qemu_fprintf(f, "PC=3D%08x\n", env->pc); --=20 2.41.0