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Mon, 29 Jan 2024 08:45:25 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Mark Cave-Ayland , "Michael S. Tsirkin" , Marcel Apfelbaum , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nicholas Piggin , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Viresh Kumar , mzamazal@redhat.com, Stefano Stabellini , Anthony Perard , Paul Durrant , Peter Xu , Fabiano Rosas , Peter Maydell , Cameron Esfahani , Roman Bolshakov , Laurent Vivier , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , xen-devel@lists.xenproject.org Subject: [PATCH v3 01/29] bulk: Access existing variables initialized to &S->F when available Date: Mon, 29 Jan 2024 17:44:43 +0100 Message-ID: <20240129164514.73104-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706546752874100001 When a variable is initialized to &struct->field, use it in place. Rationale: while this makes the code more concise, this also helps static analyzers. Mechanical change using the following Coccinelle spatch script: @@ type S, F; identifier s, m, v; @@ S *s; ... F *v =3D &s->m; <+... - &s->m + v ...+> Inspired-by: Zhao Liu Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Fabiano Rosas Reviewed-by: Anthony PERARD Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu --- hw/display/ati.c | 2 +- hw/misc/macio/pmu.c | 2 +- hw/misc/pvpanic-pci.c | 2 +- hw/pci-bridge/cxl_root_port.c | 2 +- hw/ppc/pnv.c | 20 ++++++++++---------- hw/virtio/vhost-user-gpio.c | 8 ++++---- hw/virtio/vhost-user-scmi.c | 6 +++--- hw/virtio/virtio-pci.c | 2 +- hw/xen/xen_pt.c | 6 +++--- migration/multifd-zlib.c | 2 +- target/arm/cpu.c | 4 ++-- target/arm/kvm.c | 2 +- target/arm/machine.c | 6 +++--- target/i386/hvf/x86hvf.c | 2 +- target/m68k/helper.c | 2 +- target/ppc/kvm.c | 8 ++++---- target/riscv/cpu_helper.c | 2 +- 17 files changed, 39 insertions(+), 39 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index 569b8f6165..8d2501bd82 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -991,7 +991,7 @@ static void ati_vga_realize(PCIDevice *dev, Error **err= p) } vga_init(vga, OBJECT(s), pci_address_space(dev), pci_address_space_io(dev), true); - vga->con =3D graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, &s->vga= ); + vga->con =3D graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, vga); if (s->cursor_guest_mode) { vga->cursor_invalidate =3D ati_cursor_invalidate; vga->cursor_draw_line =3D ati_cursor_draw_line; diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index e9a90da88f..7fe1c4e517 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -737,7 +737,7 @@ static void pmu_realize(DeviceState *dev, Error **errp) timer_mod(s->one_sec_timer, s->one_sec_target); =20 if (s->has_adb) { - qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, + qbus_init(adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, dev, "adb.0"); adb_register_autopoll_callback(adb_bus, pmu_adb_poll, s); } diff --git a/hw/misc/pvpanic-pci.c b/hw/misc/pvpanic-pci.c index c01e4ce864..83be95d0d2 100644 --- a/hw/misc/pvpanic-pci.c +++ b/hw/misc/pvpanic-pci.c @@ -48,7 +48,7 @@ static void pvpanic_pci_realizefn(PCIDevice *dev, Error *= *errp) PVPanicPCIState *s =3D PVPANIC_PCI_DEVICE(dev); PVPanicState *ps =3D &s->pvpanic; =20 - pvpanic_setup_io(&s->pvpanic, DEVICE(s), 2); + pvpanic_setup_io(ps, DEVICE(s), 2); =20 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &ps->mr); } diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 8f97697631..2cf2f7bf5f 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -175,7 +175,7 @@ static void cxl_rp_realize(DeviceState *dev, Error **er= rp) =20 cxl_cstate->dvsec_offset =3D CXL_ROOT_PORT_DVSEC_OFFSET; cxl_cstate->pdev =3D pci_dev; - build_dvsecs(&crp->cxl_cstate); + build_dvsecs(cxl_cstate); =20 cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate, TYPE_CXL_ROOT_PORT); diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0297871bdd..202a569e27 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1257,11 +1257,11 @@ static void pnv_chip_power8_realize(DeviceState *de= v, Error **errp) } =20 /* Processor Service Interface (PSI) Host Bridge */ - object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chi= p), + object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), &error_fatal); - object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, + object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, OBJECT(chip8->xics), &error_abort); - if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { + if (!qdev_realize(DEVICE(psi8), NULL, errp)) { return; } pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, @@ -1292,7 +1292,7 @@ static void pnv_chip_power8_realize(DeviceState *dev,= Error **errp) } pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_re= gs); qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, - qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_= OCC)); + qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); =20 /* OCC SRAM model */ memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(c= hip), @@ -1543,12 +1543,12 @@ static void pnv_chip_power9_realize(DeviceState *de= v, Error **errp) &chip9->xive.xscom_regs); =20 /* Processor Service Interface (PSI) Host Bridge */ - object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(ch= ip), + object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), &error_fatal); /* This is the only device with 4k ESB pages */ - object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, + object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, &error_fatal); - if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { + if (!qdev_realize(DEVICE(psi9), NULL, errp)) { return; } pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, @@ -1571,7 +1571,7 @@ static void pnv_chip_power9_realize(DeviceState *dev,= Error **errp) } pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_r= egs); qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( - DEVICE(&chip9->psi), PSIHB9_IRQ_OCC)); + DEVICE(psi9), PSIHB9_IRQ_OCC)); =20 /* OCC SRAM model */ memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(= chip), @@ -1586,7 +1586,7 @@ static void pnv_chip_power9_realize(DeviceState *dev,= Error **errp) pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, &chip9->sbe.xscom_mbox_regs); qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( - DEVICE(&chip9->psi), PSIHB9_IRQ_PSU)); + DEVICE(psi9), PSIHB9_IRQ_PSU)); =20 /* HOMER */ object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), @@ -1627,7 +1627,7 @@ static void pnv_chip_power9_realize(DeviceState *dev,= Error **errp) PNV9_XSCOM_I2CM_SIZE, &chip9->i2c[i].xscom_regs); qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, - qdev_get_gpio_in(DEVICE(&chip9->psi), + qdev_get_gpio_in(DEVICE(psi9), PSIHB9_IRQ_SBE_I2C)); } } diff --git a/hw/virtio/vhost-user-gpio.c b/hw/virtio/vhost-user-gpio.c index a83437a5da..6d4e9200ff 100644 --- a/hw/virtio/vhost-user-gpio.c +++ b/hw/virtio/vhost-user-gpio.c @@ -79,9 +79,9 @@ static int vu_gpio_start(VirtIODevice *vdev) * set needed for the vhost configuration. The backend may also * apply backend_features when the feature set is sent. */ - vhost_ack_features(&gpio->vhost_dev, feature_bits, vdev->guest_feature= s); + vhost_ack_features(vhost_dev, feature_bits, vdev->guest_features); =20 - ret =3D vhost_dev_start(&gpio->vhost_dev, vdev, false); + ret =3D vhost_dev_start(vhost_dev, vdev, false); if (ret < 0) { error_report("Error starting vhost-user-gpio: %d", ret); goto err_guest_notifiers; @@ -94,7 +94,7 @@ static int vu_gpio_start(VirtIODevice *vdev) * enabling/disabling irqfd. */ for (i =3D 0; i < gpio->vhost_dev.nvqs; i++) { - vhost_virtqueue_mask(&gpio->vhost_dev, vdev, i, false); + vhost_virtqueue_mask(vhost_dev, vdev, i, false); } =20 /* @@ -114,7 +114,7 @@ static int vu_gpio_start(VirtIODevice *vdev) err_guest_notifiers: k->set_guest_notifiers(qbus->parent, gpio->vhost_dev.nvqs, false); err_host_notifiers: - vhost_dev_disable_notifiers(&gpio->vhost_dev, vdev); + vhost_dev_disable_notifiers(vhost_dev, vdev); =20 return ret; } diff --git a/hw/virtio/vhost-user-scmi.c b/hw/virtio/vhost-user-scmi.c index 918bb7dcf7..300847e672 100644 --- a/hw/virtio/vhost-user-scmi.c +++ b/hw/virtio/vhost-user-scmi.c @@ -56,9 +56,9 @@ static int vu_scmi_start(VirtIODevice *vdev) goto err_host_notifiers; } =20 - vhost_ack_features(&scmi->vhost_dev, feature_bits, vdev->guest_feature= s); + vhost_ack_features(vhost_dev, feature_bits, vdev->guest_features); =20 - ret =3D vhost_dev_start(&scmi->vhost_dev, vdev, true); + ret =3D vhost_dev_start(vhost_dev, vdev, true); if (ret < 0) { error_report("Error starting vhost-user-scmi: %d", ret); goto err_guest_notifiers; @@ -71,7 +71,7 @@ static int vu_scmi_start(VirtIODevice *vdev) * enabling/disabling irqfd. */ for (i =3D 0; i < scmi->vhost_dev.nvqs; i++) { - vhost_virtqueue_mask(&scmi->vhost_dev, vdev, i, false); + vhost_virtqueue_mask(vhost_dev, vdev, i, false); } return 0; =20 diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 1a7039fb0c..cb6940fc0e 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1929,7 +1929,7 @@ static void virtio_pci_device_plugged(DeviceState *d,= Error **errp) bool modern_pio =3D proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY; uint8_t *config; uint32_t size; - VirtIODevice *vdev =3D virtio_bus_get_device(&proxy->bus); + VirtIODevice *vdev =3D virtio_bus_get_device(bus); =20 /* * Virtio capabilities present without diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c index 36e6f93c37..10ddf6bc91 100644 --- a/hw/xen/xen_pt.c +++ b/hw/xen/xen_pt.c @@ -710,7 +710,7 @@ static void xen_pt_destroy(PCIDevice *d) { uint8_t intx; int rc; =20 - if (machine_irq && !xen_host_pci_device_closed(&s->real_device)) { + if (machine_irq && !xen_host_pci_device_closed(host_dev)) { intx =3D xen_pt_pci_intx(s); rc =3D xc_domain_unbind_pt_irq(xen_xc, xen_domid, machine_irq, PT_IRQ_TYPE_PCI, @@ -759,8 +759,8 @@ static void xen_pt_destroy(PCIDevice *d) { memory_listener_unregister(&s->io_listener); s->listener_set =3D false; } - if (!xen_host_pci_device_closed(&s->real_device)) { - xen_host_pci_device_put(&s->real_device); + if (!xen_host_pci_device_closed(host_dev)) { + xen_host_pci_device_put(host_dev); } } /* init */ diff --git a/migration/multifd-zlib.c b/migration/multifd-zlib.c index 37ce48621e..237ee49928 100644 --- a/migration/multifd-zlib.c +++ b/migration/multifd-zlib.c @@ -75,7 +75,7 @@ static int zlib_send_setup(MultiFDSendParams *p, Error **= errp) err_free_zbuff: g_free(z->zbuff); err_deflate_end: - deflateEnd(&z->zs); + deflateEnd(zs); err_free_z: g_free(z); error_setg(errp, "multifd %u: %s", p->id, err_msg); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b60e103046..60ab8f3242 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2087,7 +2087,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * We rely on no XScale CPU having VFP so we can use the same bits in = the * TB flags field for VECSTRIDE and XSCALE_CPAR. */ - assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || + assert(arm_feature(env, ARM_FEATURE_AARCH64) || !cpu_isar_feature(aa32_vfp_simd, cpu) || !arm_feature(env, ARM_FEATURE_XSCALE)); =20 @@ -2129,7 +2129,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } =20 if (cpu->cfgend) { - if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { + if (arm_feature(env, ARM_FEATURE_V7)) { cpu->reset_sctlr |=3D SCTLR_EE; } else { cpu->reset_sctlr |=3D SCTLR_B; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 81813030a5..ab85d628a8 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1888,7 +1888,7 @@ int kvm_arch_init_vcpu(CPUState *cs) cpu->psci_version =3D QEMU_PSCI_VERSION_0_2; cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_PSCI_0_2; } - if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + if (!arm_feature(env, ARM_FEATURE_AARCH64)) { cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_EL1_32BIT; } if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) { diff --git a/target/arm/machine.c b/target/arm/machine.c index 9d7dbaea54..b2b39b2475 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -773,7 +773,7 @@ static int cpu_pre_load(void *opaque) env->irq_line_state =3D UINT32_MAX; =20 if (!kvm_enabled()) { - pmu_op_start(&cpu->env); + pmu_op_start(env); } =20 return 0; @@ -871,11 +871,11 @@ static int cpu_post_load(void *opaque, int version_id) } =20 if (!kvm_enabled()) { - pmu_op_finish(&cpu->env); + pmu_op_finish(env); } =20 if (tcg_enabled()) { - arm_rebuild_hflags(&cpu->env); + arm_rebuild_hflags(env); } =20 return 0; diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index 3b1ef5f49a..be2c46246e 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -408,7 +408,7 @@ bool hvf_inject_interrupts(CPUState *cs) if (!(env->hflags & HF_INHIBIT_IRQ_MASK) && (cs->interrupt_request & CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK) && !(info & VMCS_INTR_VALID)) { - int line =3D cpu_get_pic_interrupt(&x86cpu->env); + int line =3D cpu_get_pic_interrupt(env); cs->interrupt_request &=3D ~CPU_INTERRUPT_HARD; if (line >=3D 0) { wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, line | diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 14508dfa11..a812f328a1 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -972,7 +972,7 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, access_type |=3D ACCESS_SUPER; } =20 - ret =3D get_physical_address(&cpu->env, &physical, &prot, + ret =3D get_physical_address(env, &physical, &prot, address, access_type, &page_size); if (likely(ret =3D=3D 0)) { tlb_set_page(cs, address & TARGET_PAGE_MASK, diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 26fa9d0575..b95a0b4928 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -635,8 +635,8 @@ static int kvm_put_fp(CPUState *cs) =20 for (i =3D 0; i < 32; i++) { uint64_t vsr[2]; - uint64_t *fpr =3D cpu_fpr_ptr(&cpu->env, i); - uint64_t *vsrl =3D cpu_vsrl_ptr(&cpu->env, i); + uint64_t *fpr =3D cpu_fpr_ptr(env, i); + uint64_t *vsrl =3D cpu_vsrl_ptr(env, i); =20 #if HOST_BIG_ENDIAN vsr[0] =3D float64_val(*fpr); @@ -704,8 +704,8 @@ static int kvm_get_fp(CPUState *cs) =20 for (i =3D 0; i < 32; i++) { uint64_t vsr[2]; - uint64_t *fpr =3D cpu_fpr_ptr(&cpu->env, i); - uint64_t *vsrl =3D cpu_vsrl_ptr(&cpu->env, i); + uint64_t *fpr =3D cpu_fpr_ptr(env, i); + uint64_t *vsrl =3D cpu_vsrl_ptr(env, i); =20 reg.addr =3D (uintptr_t) &vsr; reg.id =3D vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c7cc7eb423..791435d628 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1200,7 +1200,7 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, va= ddr addr) CPURISCVState *env =3D &cpu->env; hwaddr phys_addr; int prot; - int mmu_idx =3D cpu_mmu_index(&cpu->env, false); + int mmu_idx =3D cpu_mmu_index(env, false); =20 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_id= x, true, env->virt_enabled, true)) { --=20 2.41.0 From nobody Tue Nov 26 14:27:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706546812; cv=none; d=zohomail.com; s=zohoarc; b=UJdm8GYc8SAZDqbgSnRwRGYuypLFqQ4vHQ6Ppb5i0CQKq4uurwmg9UsnQ1mEXqviQI/dZVieL4Mux6uN+GqUFA0wyNHQx6u0cDydS15tg69osmvqCDhmIAAogyGG41Nfqh2yfh3rhO/9GY9Q7ZL95m9gU5Bwsi9R6L0qjHDTBh0= ARC-Message-Signature: i=1; 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Mon, 29 Jan 2024 08:45:32 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , "Michael S. Tsirkin" , Song Gao , Nicholas Piggin , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson , Harsh Prateek Bora , Halil Pasic , Christian Borntraeger , Eric Farman , David Hildenbrand , Ilya Leoshkevich , Thomas Huth Subject: [PATCH v3 02/29] hw/core: Declare CPUArchId::cpu as CPUState instead of Object Date: Mon, 29 Jan 2024 17:44:44 +0100 Message-ID: <20240129164514.73104-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706546815086100007 Do not accept any Object for CPUArchId::cpu field, restrict it to CPUState type. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth --- include/hw/boards.h | 2 +- hw/core/machine.c | 4 ++-- hw/i386/x86.c | 2 +- hw/loongarch/virt.c | 2 +- hw/ppc/spapr.c | 5 ++--- hw/s390x/s390-virtio-ccw.c | 2 +- 6 files changed, 8 insertions(+), 9 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index bcfde8a84d..8b8f6d5c00 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -120,7 +120,7 @@ typedef struct CPUArchId { uint64_t arch_id; int64_t vcpus_count; CpuInstanceProperties props; - Object *cpu; + CPUState *cpu; const char *type; } CPUArchId; =20 diff --git a/hw/core/machine.c b/hw/core/machine.c index fb5afdcae4..854cf00a9b 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -716,7 +716,7 @@ HotpluggableCPUList *machine_query_hotpluggable_cpus(Ma= chineState *machine) mc->possible_cpu_arch_ids(machine); =20 for (i =3D 0; i < machine->possible_cpus->len; i++) { - Object *cpu; + CPUState *cpu; HotpluggableCPU *cpu_item =3D g_new0(typeof(*cpu_item), 1); =20 cpu_item->type =3D g_strdup(machine->possible_cpus->cpus[i].type); @@ -726,7 +726,7 @@ HotpluggableCPUList *machine_query_hotpluggable_cpus(Ma= chineState *machine) =20 cpu =3D machine->possible_cpus->cpus[i].cpu; if (cpu) { - cpu_item->qom_path =3D object_get_canonical_path(cpu); + cpu_item->qom_path =3D object_get_canonical_path(OBJECT(cpu)); } QAPI_LIST_PREPEND(head, cpu_item); } diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 2b6291ad8d..19464ea971 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -221,7 +221,7 @@ void x86_cpu_plug(HotplugHandler *hotplug_dev, } =20 found_cpu =3D x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); - found_cpu->cpu =3D OBJECT(dev); + found_cpu->cpu =3D CPU(dev); out: error_propagate(errp, local_err); } diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index c9a680e61a..524a53de06 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -811,7 +811,7 @@ static void loongarch_init(MachineState *machine) for (i =3D 0; i < possible_cpus->len; i++) { cpu =3D cpu_create(machine->cpu_type); cpu->cpu_index =3D i; - machine->possible_cpus->cpus[i].cpu =3D OBJECT(cpu); + machine->possible_cpus->cpus[i].cpu =3D cpu; lacpu =3D LOONGARCH_CPU(cpu); lacpu->phy_id =3D machine->possible_cpus->cpus[i].arch_id; } diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e8dabc8614..0b77aa5514 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3985,7 +3985,6 @@ static void spapr_core_plug(HotplugHandler *hotplug_d= ev, DeviceState *dev) SpaprMachineClass *smc =3D SPAPR_MACHINE_CLASS(mc); SpaprCpuCore *core =3D SPAPR_CPU_CORE(OBJECT(dev)); CPUCore *cc =3D CPU_CORE(dev); - CPUState *cs; SpaprDrc *drc; CPUArchId *core_slot; int index; @@ -4019,7 +4018,7 @@ static void spapr_core_plug(HotplugHandler *hotplug_d= ev, DeviceState *dev) } } =20 - core_slot->cpu =3D OBJECT(dev); + core_slot->cpu =3D CPU(dev); =20 /* * Set compatibility mode to match the boot CPU, which was either set @@ -4035,7 +4034,7 @@ static void spapr_core_plug(HotplugHandler *hotplug_d= ev, DeviceState *dev) =20 if (smc->pre_2_10_has_unused_icps) { for (i =3D 0; i < cc->nr_threads; i++) { - cs =3D CPU(core->threads[i]); + CPUState *cs =3D CPU(core->threads[i]); pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); } } diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index c99682b07d..69e39e13ff 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -324,7 +324,7 @@ static void s390_cpu_plug(HotplugHandler *hotplug_dev, ERRP_GUARD(); =20 g_assert(!ms->possible_cpus->cpus[cpu->env.core_id].cpu); - ms->possible_cpus->cpus[cpu->env.core_id].cpu =3D OBJECT(dev); + ms->possible_cpus->cpus[cpu->env.core_id].cpu =3D CPU(dev); =20 if (s390_has_topology()) { s390_topology_setup_cpu(ms, cpu, errp); --=20 2.41.0 From nobody Tue Nov 26 14:27:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Tsirkin" , Igor Mammedov , Ani Sinha Subject: [PATCH v3 03/29] hw/acpi/cpu: Use CPUState typedef Date: Mon, 29 Jan 2024 17:44:45 +0100 Message-ID: <20240129164514.73104-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706546839036100003 QEMU coding style recommend using structure typedefs: https://www.qemu.org/docs/master/devel/style.html#typedefs Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu --- include/hw/acpi/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index bc901660fb..209e1773f8 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -19,7 +19,7 @@ #include "hw/hotplug.h" =20 typedef struct AcpiCpuStatus { - struct CPUState *cpu; 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Mon, 29 Jan 2024 08:45:44 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , Reinoud Zandijk , Sunil Muthuswamy , Song Gao , Yoshinori Sato Subject: [PATCH v3 04/29] bulk: Call in place single use cpu_env() Date: Mon, 29 Jan 2024 17:44:46 +0100 Message-ID: <20240129164514.73104-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706546981342100001 Avoid CPUArchState local variable when cpu_env() is used once. Mechanical patch using the following Coccinelle spatch script: @@ type CPUArchState; identifier env; expression cs; @@ { - CPUArchState *env =3D cpu_env(cs); ... when !=3D env - env + cpu_env(cs) ... when !=3D env } Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec.c | 3 +-- linux-user/i386/cpu_loop.c | 4 ++-- target/hppa/mem_helper.c | 3 +-- target/hppa/translate.c | 3 +-- target/i386/nvmm/nvmm-all.c | 6 ++---- target/i386/whpx/whpx-all.c | 18 ++++++------------ target/loongarch/tcg/translate.c | 3 +-- target/rx/translate.c | 3 +-- target/sh4/op_helper.c | 4 +--- 9 files changed, 16 insertions(+), 31 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 67eda9865e..86206484f8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -445,7 +445,6 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) static inline TranslationBlock * QEMU_DISABLE_CFI cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) { - CPUArchState *env =3D cpu_env(cpu); uintptr_t ret; TranslationBlock *last_tb; const void *tb_ptr =3D itb->tc.ptr; @@ -455,7 +454,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *= tb_exit) } =20 qemu_thread_jit_execute(); - ret =3D tcg_qemu_tb_exec(env, tb_ptr); + ret =3D tcg_qemu_tb_exec(cpu_env(cpu), tb_ptr); cpu->neg.can_do_io =3D true; qemu_plugin_disable_mem_helpers(cpu); /* diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index 42ecb4bf0a..92beb6830c 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -323,8 +323,8 @@ void cpu_loop(CPUX86State *env) =20 static void target_cpu_free(void *obj) { - CPUArchState *env =3D cpu_env(obj); - target_munmap(env->gdt.base, sizeof(uint64_t) * TARGET_GDT_ENTRIES); + target_munmap(cpu_env(obj)->gdt.base, + sizeof(uint64_t) * TARGET_GDT_ENTRIES); g_free(obj); } =20 diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 4fcc612754..bb85962d50 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -518,7 +518,6 @@ void HELPER(iitlbt_pa20)(CPUHPPAState *env, target_ulon= g r1, target_ulong r2) /* Purge (Insn/Data) TLB. */ static void ptlb_work(CPUState *cpu, run_on_cpu_data data) { - CPUHPPAState *env =3D cpu_env(cpu); vaddr start =3D data.target_ptr; vaddr end; =20 @@ -532,7 +531,7 @@ static void ptlb_work(CPUState *cpu, run_on_cpu_data da= ta) end =3D (vaddr)TARGET_PAGE_SIZE << (2 * end); end =3D start + end - 1; =20 - hppa_flush_tlb_range(env, start, end); + hppa_flush_tlb_range(cpu_env(cpu), start, end); } =20 /* This is local to the current cpu. */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3ef39b1bd7..5735335254 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3805,8 +3805,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gat= e *a) =20 #ifndef CONFIG_USER_ONLY if (ctx->tb_flags & PSW_C) { - CPUHPPAState *env =3D cpu_env(ctx->cs); - int type =3D hppa_artype_for_page(env, ctx->base.pc_next); + int type =3D hppa_artype_for_page(cpu_env(ctx->cs), ctx->base.pc_n= ext); /* If we could not find a TLB entry, then we need to generate an ITLB miss exception so the kernel will provide it. The resulting TLB fill operation will invalidate this TB and diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index cfdca91123..49a3a3b916 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -340,7 +340,6 @@ nvmm_get_registers(CPUState *cpu) static bool nvmm_can_take_int(CPUState *cpu) { - CPUX86State *env =3D cpu_env(cpu); AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_machine *mach =3D get_nvmm_mach(); @@ -349,7 +348,7 @@ nvmm_can_take_int(CPUState *cpu) return false; } =20 - if (qcpu->int_shadow || !(env->eflags & IF_MASK)) { + if (qcpu->int_shadow || !(cpu_env(cpu)->eflags & IF_MASK)) { struct nvmm_x64_state *state =3D vcpu->state; =20 /* Exit on interrupt window. */ @@ -645,13 +644,12 @@ static int nvmm_handle_halted(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - CPUX86State *env =3D cpu_env(cpu); int ret =3D 0; =20 bql_lock(); =20 if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && - (env->eflags & IF_MASK)) && + (cpu_env(cpu)->eflags & IF_MASK)) && !(cpu->interrupt_request & CPU_INTERRUPT_NMI)) { cpu->exception_index =3D EXCP_HLT; cpu->halted =3D true; diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index a7262654ac..31eec7048c 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -300,7 +300,6 @@ static SegmentCache whpx_seg_h2q(const WHV_X64_SEGMENT_= REGISTER *hs) /* X64 Extended Control Registers */ static void whpx_set_xcrs(CPUState *cpu) { - CPUX86State *env =3D cpu_env(cpu); HRESULT hr; struct whpx_state *whpx =3D &whpx_global; WHV_REGISTER_VALUE xcr0; @@ -311,7 +310,7 @@ static void whpx_set_xcrs(CPUState *cpu) } =20 /* Only xcr0 is supported by the hypervisor currently */ - xcr0.Reg64 =3D env->xcr0; + xcr0.Reg64 =3D cpu_env(cpu)->xcr0; hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters( whpx->partition, cpu->cpu_index, &xcr0_name, 1, &xcr0); if (FAILED(hr)) { @@ -321,7 +320,6 @@ static void whpx_set_xcrs(CPUState *cpu) =20 static int whpx_set_tsc(CPUState *cpu) { - CPUX86State *env =3D cpu_env(cpu); WHV_REGISTER_NAME tsc_reg =3D WHvX64RegisterTsc; WHV_REGISTER_VALUE tsc_val; HRESULT hr; @@ -345,7 +343,7 @@ static int whpx_set_tsc(CPUState *cpu) } } =20 - tsc_val.Reg64 =3D env->tsc; + tsc_val.Reg64 =3D cpu_env(cpu)->tsc; hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters( whpx->partition, cpu->cpu_index, &tsc_reg, 1, &tsc_val); if (FAILED(hr)) { @@ -556,7 +554,6 @@ static void whpx_set_registers(CPUState *cpu, int level) =20 static int whpx_get_tsc(CPUState *cpu) { - CPUX86State *env =3D cpu_env(cpu); WHV_REGISTER_NAME tsc_reg =3D WHvX64RegisterTsc; WHV_REGISTER_VALUE tsc_val; HRESULT hr; @@ -569,14 +566,13 @@ static int whpx_get_tsc(CPUState *cpu) return -1; } =20 - env->tsc =3D tsc_val.Reg64; + cpu_env(cpu)->tsc =3D tsc_val.Reg64; return 0; } =20 /* X64 Extended Control Registers */ static void whpx_get_xcrs(CPUState *cpu) { - CPUX86State *env =3D cpu_env(cpu); HRESULT hr; struct whpx_state *whpx =3D &whpx_global; WHV_REGISTER_VALUE xcr0; @@ -594,7 +590,7 @@ static void whpx_get_xcrs(CPUState *cpu) return; } =20 - env->xcr0 =3D xcr0.Reg64; + cpu_env(cpu)->xcr0 =3D xcr0.Reg64; } =20 static void whpx_get_registers(CPUState *cpu) @@ -1400,8 +1396,7 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exi= t_context_valid) { if (cpu->vcpu_dirty) { /* The CPU registers have been modified by other parts of QEMU. */ - CPUArchState *env =3D cpu_env(cpu); - return env->eip; + return cpu_env(cpu)->eip; } else if (exit_context_valid) { /* * The CPU registers have not been modified by neither other parts @@ -1439,12 +1434,11 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool e= xit_context_valid) =20 static int whpx_handle_halt(CPUState *cpu) { - CPUX86State *env =3D cpu_env(cpu); int ret =3D 0; =20 bql_lock(); if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && - (env->eflags & IF_MASK)) && + (cpu_env(cpu)->eflags & IF_MASK)) && !(cpu->interrupt_request & CPU_INTERRUPT_NMI)) { cpu->exception_index =3D EXCP_HLT; cpu->halted =3D true; diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/transl= ate.c index 21f4db6fbd..7bb8cecab3 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -282,10 +282,9 @@ static uint64_t make_address_pc(DisasContext *ctx, uin= t64_t addr) =20 static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState= *cs) { - CPULoongArchState *env =3D cpu_env(cs); DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - ctx->opcode =3D translator_ldl(env, &ctx->base, ctx->base.pc_next); + ctx->opcode =3D translator_ldl(cpu_env(cs), &ctx->base, ctx->base.pc_n= ext); =20 if (!decode(ctx, ctx->opcode)) { qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. " diff --git a/target/rx/translate.c b/target/rx/translate.c index c6ce717a95..1829a0b1cd 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2195,9 +2195,8 @@ static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) =20 static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *c= s) { - CPURXState *env =3D cpu_env(cs); DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - ctx->env =3D env; + ctx->env =3D cpu_env(cs); ctx->tb_flags =3D ctx->base.tb->flags; } =20 diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 54d390fe1f..4559d0d376 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -29,9 +29,7 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - CPUSH4State *env =3D cpu_env(cs); - - env->tea =3D addr; + cpu_env(cs)->tea =3D addr; switch (access_type) { case MMU_INST_FETCH: case MMU_DATA_LOAD: --=20 2.41.0 From nobody Tue Nov 26 14:27:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 29 Jan 2024 08:45:49 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 05/29] scripts/coccinelle: Add cpu_env.cocci script Date: Mon, 29 Jan 2024 17:44:47 +0100 Message-ID: <20240129164514.73104-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706546891161100005 Add a Coccinelle script to convert the following slow path (due to the QOM cast macro): &ARCH_CPU(..)->env to the following fast path: cpu_env(..) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 1 + scripts/coccinelle/cpu_env.cocci | 100 +++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 scripts/coccinelle/cpu_env.cocci diff --git a/MAINTAINERS b/MAINTAINERS index dfaca8323e..ca3c8c18ab 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -157,6 +157,7 @@ F: accel/tcg/ F: accel/stubs/tcg-stub.c F: util/cacheinfo.c F: util/cacheflush.c +F: scripts/coccinelle/cpu_env.cocci F: scripts/decodetree.py F: docs/devel/decodetree.rst F: docs/devel/tcg* diff --git a/scripts/coccinelle/cpu_env.cocci b/scripts/coccinelle/cpu_env.= cocci new file mode 100644 index 0000000000..5a70c2211a --- /dev/null +++ b/scripts/coccinelle/cpu_env.cocci @@ -0,0 +1,100 @@ +/* + * Convert &ARCH_CPU(..)->env to use cpu_env(..). + * + * Rationale: ARCH_CPU() might be slow, being a QOM cast macro. + * cpu_env() is its fast equivalent. + * CPU() macro is a no-op. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * SPDX-FileCopyrightText: Linaro Ltd 2024 + * SPDX-FileContributor: Philippe Mathieu-Daud=C3=A9 + */ + +@@ +type ArchCPU =3D~ "CPU$"; +identifier cpu; +type CPUArchState =3D~ "^CPU"; +identifier env; +@@ + ArchCPU *cpu; + ... + CPUArchState *env =3D &cpu->env; + <... +- &cpu->env ++ env + ...> + + +/* + * Due to commit 8ce5c64499 ("semihosting: Return failure from + * softmmu-uaccess.h functions"), skip functions using softmmu-uaccess.h + * macros (they don't pass 'env' as argument). + */ +@ uaccess_api_used exists @ +identifier semihosting_func =3D~ "^(put|get)_user_[us](al|8|16|32)$"; +@@ + semihosting_func(...) + + +/* + * Argument is CPUState* + */ +@ cpustate_arg depends on !uaccess_api_used @ +identifier cpu; +type ArchCPU =3D~ "CPU$"; +type CPUArchState; +identifier ARCH_CPU =3D~ "CPU$"; +identifier env; +CPUState *cs; +@@ +- ArchCPU *cpu =3D ARCH_CPU(cs); + ... +- CPUArchState *env =3D &cpu->env; ++ CPUArchState *env =3D cpu_env(cs); + ... when !=3D cpu + + +/* + * Argument is not CPUState* but a related QOM object. + * CPU() is not a QOM macro but a cast (See commit 0d6d1ab499). + */ +@ depends on !uaccess_api_used && !cpustate_arg @ +identifier cpu; +type ArchCPU =3D~ "CPU$"; +type CPUArchState; +identifier ARCH_CPU =3D~ "CPU$"; +identifier env; +expression cs; +@@ +- ArchCPU *cpu =3D ARCH_CPU(cs); + ... +- CPUArchState *env =3D &cpu->env; ++ CPUArchState *env =3D cpu_env(CPU(cs)); + ... when !=3D cpu + + +/* When single use of 'env', call cpu_env() in place */ +@ depends on !uaccess_api_used @ +type CPUArchState; +identifier env; +expression cs; +@@ +- CPUArchState *env =3D cpu_env(cs); + ... when !=3D env +- env ++ cpu_env(cs) + ... when !=3D env + + +/* Both first_cpu/current_cpu are extern CPUState* */ +@@ +symbol first_cpu; +symbol current_cpu; +@@ +( +- CPU(first_cpu) ++ first_cpu +| +- CPU(current_cpu) ++ current_cpu +) --=20 2.41.0 From nobody Tue Nov 26 14:27:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Iglesias" , Brian Cain , Song Gao , Laurent Vivier , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Yoshinori Sato , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov Subject: [PATCH v3 06/29] target: Replace CPU_GET_CLASS(cpu -> obj) in cpu_reset_hold() handler Date: Mon, 29 Jan 2024 17:44:48 +0100 Message-ID: <20240129164514.73104-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706546897165100002 Since CPU() macro is a simple cast, the following are equivalent: Object *obj; CPUState *cs =3D CPU(obj) In order to ease static analysis when running scripts/coccinelle/cpu_env.cocci from the previous commit, replace: - CPU_GET_CLASS(cpu); + CPU_GET_CLASS(obj); Most code use the 'cs' variable name for CPUState handle. Replace few 's' -> 'cs' to unify cpu_reset_hold() style. No logical change in this patch. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Richard Henderson --- target/arm/cpu.c | 14 +++++++------- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hexagon/cpu.c | 2 +- target/i386/cpu.c | 14 +++++++------- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 6 +++--- target/microblaze/cpu.c | 6 +++--- target/mips/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 8 ++++---- target/ppc/cpu_init.c | 12 ++++++------ target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/sh4/cpu.c | 6 +++--- target/sparc/cpu.c | 6 +++--- target/tricore/cpu.c | 6 +++--- target/xtensa/cpu.c | 8 ++++---- 18 files changed, 51 insertions(+), 51 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 60ab8f3242..e5deb5195b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -209,9 +209,9 @@ static void cp_reg_check_reset(gpointer key, gpointer v= alue, gpointer opaque) =20 static void arm_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - ARMCPU *cpu =3D ARM_CPU(s); - ARMCPUClass *acc =3D ARM_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + ARMCPU *cpu =3D ARM_CPU(cs); + ARMCPUClass *acc =3D ARM_CPU_GET_CLASS(obj); CPUARMState *env =3D &cpu->env; =20 if (acc->parent_phases.hold) { @@ -228,7 +228,7 @@ static void arm_cpu_reset_hold(Object *obj) env->vfp.xregs[ARM_VFP_MVFR1] =3D cpu->isar.mvfr1; env->vfp.xregs[ARM_VFP_MVFR2] =3D cpu->isar.mvfr2; =20 - cpu->power_state =3D s->start_powered_off ? PSCI_OFF : PSCI_ON; + cpu->power_state =3D cs->start_powered_off ? PSCI_OFF : PSCI_ON; =20 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { env->iwmmxt.cregs[ARM_IWMMXT_wCID] =3D 0x69051000 | 'Q'; @@ -433,7 +433,7 @@ static void arm_cpu_reset_hold(Object *obj) =20 /* Load the initial SP and PC from offset 0 and 4 in the vector ta= ble */ vecbase =3D env->v7m.vecbase[env->v7m.secure]; - rom =3D rom_ptr_for_as(s->as, vecbase, 8); + rom =3D rom_ptr_for_as(cs->as, vecbase, 8); if (rom) { /* Address zero is covered by ROM which hasn't yet been * copied into physical memory. @@ -446,8 +446,8 @@ static void arm_cpu_reset_hold(Object *obj) * it got copied into memory. In the latter case, rom_ptr * will return a NULL pointer and we should use ldl_phys inste= ad. */ - initial_msp =3D ldl_phys(s->as, vecbase); - initial_pc =3D ldl_phys(s->as, vecbase + 4); + initial_msp =3D ldl_phys(cs->as, vecbase); + initial_pc =3D ldl_phys(cs->as, vecbase + 4); } =20 qemu_log_mask(CPU_LOG_INT, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index f5cbdc4a8c..0f191a4c9d 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -74,7 +74,7 @@ static void avr_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); AVRCPU *cpu =3D AVR_CPU(cs); - AVRCPUClass *mcc =3D AVR_CPU_GET_CLASS(cpu); + AVRCPUClass *mcc =3D AVR_CPU_GET_CLASS(obj); CPUAVRState *env =3D &cpu->env; =20 if (mcc->parent_phases.hold) { diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 9ba08e8b0c..4187e0ef3c 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -60,7 +60,7 @@ static void cris_cpu_reset_hold(Object *obj) { CPUState *s =3D CPU(obj); CRISCPU *cpu =3D CRIS_CPU(s); - CRISCPUClass *ccc =3D CRIS_CPU_GET_CLASS(cpu); + CRISCPUClass *ccc =3D CRIS_CPU_GET_CLASS(obj); CPUCRISState *env =3D &cpu->env; uint32_t vr; =20 diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index c0cd739e15..085d6c0115 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -289,7 +289,7 @@ static void hexagon_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); HexagonCPU *cpu =3D HEXAGON_CPU(cs); - HexagonCPUClass *mcc =3D HEXAGON_CPU_GET_CLASS(cpu); + HexagonCPUClass *mcc =3D HEXAGON_CPU_GET_CLASS(obj); CPUHexagonState *env =3D &cpu->env; =20 if (mcc->parent_phases.hold) { diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 03822d9ba8..66345c204a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6690,9 +6690,9 @@ static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *= env) =20 static void x86_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - X86CPU *cpu =3D X86_CPU(s); - X86CPUClass *xcc =3D X86_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + X86CPU *cpu =3D X86_CPU(cs); + X86CPUClass *xcc =3D X86_CPU_GET_CLASS(obj); CPUX86State *env =3D &cpu->env; target_ulong cr4; uint64_t xcr0; @@ -6780,8 +6780,8 @@ static void x86_cpu_reset_hold(Object *obj) memset(env->dr, 0, sizeof(env->dr)); env->dr[6] =3D DR6_FIXED_1; env->dr[7] =3D DR7_FIXED_1; - cpu_breakpoint_remove_all(s, BP_CPU); - cpu_watchpoint_remove_all(s, BP_CPU); + cpu_breakpoint_remove_all(cs, BP_CPU); + cpu_watchpoint_remove_all(cs, BP_CPU); =20 cr4 =3D 0; xcr0 =3D XSTATE_FP_MASK; @@ -6832,9 +6832,9 @@ static void x86_cpu_reset_hold(Object *obj) env->triple_fault_pending =3D false; #if !defined(CONFIG_USER_ONLY) /* We hard-wire the BSP to the first CPU. */ - apic_designate_bsp(cpu->apic_state, s->cpu_index =3D=3D 0); + apic_designate_bsp(cpu->apic_state, cs->cpu_index =3D=3D 0); =20 - s->halted =3D !cpu_is_bsp(cpu); + cs->halted =3D !cpu_is_bsp(cpu); =20 if (kvm_enabled()) { kvm_arch_reset_vcpu(cpu); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 064540397d..3094bbc0d9 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -500,7 +500,7 @@ static void loongarch_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - LoongArchCPUClass *lacc =3D LOONGARCH_CPU_GET_CLASS(cpu); + LoongArchCPUClass *lacc =3D LOONGARCH_CPU_GET_CLASS(obj); CPULoongArchState *env =3D &cpu->env; =20 if (lacc->parent_phases.hold) { diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 1421e77c2c..4d14d04c33 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -68,9 +68,9 @@ static void m68k_unset_feature(CPUM68KState *env, int fea= ture) =20 static void m68k_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - M68kCPU *cpu =3D M68K_CPU(s); - M68kCPUClass *mcc =3D M68K_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + M68kCPU *cpu =3D M68K_CPU(cs); + M68kCPUClass *mcc =3D M68K_CPU_GET_CLASS(obj); CPUM68KState *env =3D &cpu->env; floatx80 nan =3D floatx80_default_nan(NULL); int i; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bbb3335cad..6d4b7c2c8f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -167,9 +167,9 @@ static void microblaze_cpu_set_irq(void *opaque, int ir= q, int level) =20 static void mb_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(s); - MicroBlazeCPUClass *mcc =3D MICROBLAZE_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + MicroBlazeCPUClass *mcc =3D MICROBLAZE_CPU_GET_CLASS(obj); CPUMBState *env =3D &cpu->env; =20 if (mcc->parent_phases.hold) { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a0023edd43..6ced52f985 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -188,7 +188,7 @@ static void mips_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); MIPSCPU *cpu =3D MIPS_CPU(cs); - MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(cpu); + MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(obj); CPUMIPSState *env =3D &cpu->env; =20 if (mcc->parent_phases.hold) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index a27732bf2b..09b122e24d 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -61,7 +61,7 @@ static void nios2_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); Nios2CPU *cpu =3D NIOS2_CPU(cs); - Nios2CPUClass *ncc =3D NIOS2_CPU_GET_CLASS(cpu); + Nios2CPUClass *ncc =3D NIOS2_CPU_GET_CLASS(obj); CPUNios2State *env =3D &cpu->env; =20 if (ncc->parent_phases.hold) { diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 381ebe00d3..0fdadf9e55 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -75,9 +75,9 @@ static void openrisc_disas_set_info(CPUState *cpu, disass= emble_info *info) =20 static void openrisc_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - OpenRISCCPU *cpu =3D OPENRISC_CPU(s); - OpenRISCCPUClass *occ =3D OPENRISC_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); + OpenRISCCPUClass *occ =3D OPENRISC_CPU_GET_CLASS(obj); =20 if (occ->parent_phases.hold) { occ->parent_phases.hold(obj); @@ -88,7 +88,7 @@ static void openrisc_cpu_reset_hold(Object *obj) cpu->env.pc =3D 0x100; cpu->env.sr =3D SR_FO | SR_SM; cpu->env.lock_addr =3D -1; - s->exception_index =3D -1; + cs->exception_index =3D -1; cpu_set_fpcsr(&cpu->env, 0); =20 set_float_detect_tininess(float_tininess_before_rounding, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 344196a8ce..61b8495a90 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7107,9 +7107,9 @@ static bool ppc_cpu_has_work(CPUState *cs) =20 static void ppc_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - PowerPCCPU *cpu =3D POWERPC_CPU(s); - PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(obj); CPUPPCState *env =3D &cpu->env; target_ulong msr; int i; @@ -7158,8 +7158,8 @@ static void ppc_cpu_reset_hold(Object *obj) env->nip =3D env->hreset_vector | env->excp_prefix; =20 if (tcg_enabled()) { - cpu_breakpoint_remove_all(s, BP_CPU); - cpu_watchpoint_remove_all(s, BP_CPU); + cpu_breakpoint_remove_all(cs, BP_CPU); + cpu_watchpoint_remove_all(cs, BP_CPU); if (env->mmu_model !=3D POWERPC_MMU_REAL) { ppc_tlb_invalidate_all(env); } @@ -7173,7 +7173,7 @@ static void ppc_cpu_reset_hold(Object *obj) env->reserve_addr =3D (target_ulong)-1ULL; /* Be sure no exception or interrupt is pending */ env->pending_interrupts =3D 0; - s->exception_index =3D POWERPC_EXCP_NONE; + cs->exception_index =3D POWERPC_EXCP_NONE; env->error_code =3D 0; ppc_irq_reset(cpu); =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8cbfc7e781..1bd99bc5c6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -875,7 +875,7 @@ static void riscv_cpu_reset_hold(Object *obj) #endif CPUState *cs =3D CPU(obj); RISCVCPU *cpu =3D RISCV_CPU(cs); - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(obj); CPURISCVState *env =3D &cpu->env; =20 if (mcc->parent_phases.hold) { diff --git a/target/rx/cpu.c b/target/rx/cpu.c index c5ffeffe32..58ca26184d 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -67,7 +67,7 @@ static bool rx_cpu_has_work(CPUState *cs) static void rx_cpu_reset_hold(Object *obj) { RXCPU *cpu =3D RX_CPU(obj); - RXCPUClass *rcc =3D RX_CPU_GET_CLASS(cpu); + RXCPUClass *rcc =3D RX_CPU_GET_CLASS(obj); CPURXState *env =3D &cpu->env; uint32_t *resetvec; =20 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 806a0ef875..1b03c7bcb1 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -91,9 +91,9 @@ static bool superh_cpu_has_work(CPUState *cs) =20 static void superh_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - SuperHCPU *cpu =3D SUPERH_CPU(s); - SuperHCPUClass *scc =3D SUPERH_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + SuperHCPU *cpu =3D SUPERH_CPU(cs); + SuperHCPUClass *scc =3D SUPERH_CPU_GET_CLASS(obj); CPUSH4State *env =3D &cpu->env; =20 if (scc->parent_phases.hold) { diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index befa7fc4eb..152bee4f81 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -31,9 +31,9 @@ =20 static void sparc_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - SPARCCPU *cpu =3D SPARC_CPU(s); - SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + SPARCCPU *cpu =3D SPARC_CPU(cs); + SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(obj); CPUSPARCState *env =3D &cpu->env; =20 if (scc->parent_phases.hold) { diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 8acacdf0c0..9bdaa1593a 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -72,9 +72,9 @@ static void tricore_restore_state_to_opc(CPUState *cs, =20 static void tricore_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - TriCoreCPU *cpu =3D TRICORE_CPU(s); - TriCoreCPUClass *tcc =3D TRICORE_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + TriCoreCPU *cpu =3D TRICORE_CPU(cs); + TriCoreCPUClass *tcc =3D TRICORE_CPU_GET_CLASS(obj); CPUTriCoreState *env =3D &cpu->env; =20 if (tcc->parent_phases.hold) { diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 99c0ca130f..ce044466ad 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -90,9 +90,9 @@ bool xtensa_abi_call0(void) =20 static void xtensa_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - XtensaCPU *cpu =3D XTENSA_CPU(s); - XtensaCPUClass *xcc =3D XTENSA_CPU_GET_CLASS(cpu); + CPUState *cs =3D CPU(obj); + XtensaCPU *cpu =3D XTENSA_CPU(cs); + XtensaCPUClass *xcc =3D XTENSA_CPU_GET_CLASS(obj); CPUXtensaState *env =3D &cpu->env; bool dfpu =3D xtensa_option_enabled(env->config, XTENSA_OPTION_DFP_COPROCESSOR); @@ -127,7 +127,7 @@ static void xtensa_cpu_reset_hold(Object *obj) =20 #ifndef CONFIG_USER_ONLY reset_mmu(env); - s->halted =3D env->runstall; + cs->halted =3D env->runstall; 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Mon, 29 Jan 2024 08:46:03 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 07/29] target/alpha: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:44:49 +0100 Message-ID: <20240129164514.73104-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706547416452100003 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/cpu.c | 31 +++++++------------------------ target/alpha/gdbstub.c | 6 ++---- target/alpha/helper.c | 15 +++++---------- target/alpha/mem_helper.c | 11 +++-------- target/alpha/translate.c | 4 ++-- 5 files changed, 19 insertions(+), 48 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b8ed29e343..e21a8936c7 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -130,40 +130,27 @@ static ObjectClass *alpha_cpu_class_by_name(const cha= r *cpu_model) =20 static void ev4_cpu_initfn(Object *obj) { - AlphaCPU *cpu =3D ALPHA_CPU(obj); - CPUAlphaState *env =3D &cpu->env; - - env->implver =3D IMPLVER_2106x; + cpu_env(CPU(obj))->implver =3D IMPLVER_2106x; } =20 static void ev5_cpu_initfn(Object *obj) { - AlphaCPU *cpu =3D ALPHA_CPU(obj); - CPUAlphaState *env =3D &cpu->env; - - env->implver =3D IMPLVER_21164; + cpu_env(CPU(obj))->implver =3D IMPLVER_21164; } =20 static void ev56_cpu_initfn(Object *obj) { - AlphaCPU *cpu =3D ALPHA_CPU(obj); - CPUAlphaState *env =3D &cpu->env; - - env->amask |=3D AMASK_BWX; + cpu_env(CPU(obj))->amask |=3D AMASK_BWX; } =20 static void pca56_cpu_initfn(Object *obj) { - AlphaCPU *cpu =3D ALPHA_CPU(obj); - CPUAlphaState *env =3D &cpu->env; - - env->amask |=3D AMASK_MVI; + cpu_env(CPU(obj))->amask |=3D AMASK_MVI; } =20 static void ev6_cpu_initfn(Object *obj) { - AlphaCPU *cpu =3D ALPHA_CPU(obj); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(CPU(obj)); =20 env->implver =3D IMPLVER_21264; env->amask =3D AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP; @@ -171,16 +158,12 @@ static void ev6_cpu_initfn(Object *obj) =20 static void ev67_cpu_initfn(Object *obj) { - AlphaCPU *cpu =3D ALPHA_CPU(obj); - CPUAlphaState *env =3D &cpu->env; - - env->amask |=3D AMASK_CIX | AMASK_PREFETCH; + cpu_env(CPU(obj))->amask |=3D AMASK_CIX | AMASK_PREFETCH; } =20 static void alpha_cpu_initfn(Object *obj) { - AlphaCPU *cpu =3D ALPHA_CPU(obj); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(CPU(obj)); =20 env->lock_addr =3D -1; #if defined(CONFIG_USER_ONLY) diff --git a/target/alpha/gdbstub.c b/target/alpha/gdbstub.c index 0f8fa150f8..13694fd321 100644 --- a/target/alpha/gdbstub.c +++ b/target/alpha/gdbstub.c @@ -23,8 +23,7 @@ =20 int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); uint64_t val; CPU_DoubleU d; =20 @@ -59,8 +58,7 @@ int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) =20 int alpha_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); target_ulong tmp =3D ldtul_p(mem_buf); CPU_DoubleU d; =20 diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 970c869771..d6d4353edd 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -286,11 +286,10 @@ static int get_physical_address(CPUAlphaState *env, t= arget_ulong addr, =20 hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); target_ulong phys; int prot, fail; =20 - fail =3D get_physical_address(&cpu->env, addr, 0, 0, &phys, &prot); + fail =3D get_physical_address(cpu_env(cs), addr, 0, 0, &phys, &prot); return (fail >=3D 0 ? -1 : phys); } =20 @@ -298,8 +297,7 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int s= ize, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); target_ulong phys; int prot, fail; =20 @@ -325,8 +323,7 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int s= ize, =20 void alpha_cpu_do_interrupt(CPUState *cs) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); int i =3D cs->exception_index; =20 if (qemu_loglevel_mask(CPU_LOG_INT)) { @@ -435,8 +432,7 @@ void alpha_cpu_do_interrupt(CPUState *cs) =20 bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); int idx =3D -1; =20 /* We never take interrupts while in PALmode. */ @@ -487,8 +483,7 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", "t10", "t11", "ra", "t12", "at", "gp", "sp" }; - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); int i; =20 qemu_fprintf(f, "PC " TARGET_FMT_lx " PS %02x\n", diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index a39b52c5dd..872955f5e7 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -42,18 +42,14 @@ static void do_unaligned_access(CPUAlphaState *env, vad= dr addr, uintptr_t retadd void alpha_cpu_record_sigbus(CPUState *cs, vaddr addr, MMUAccessType access_type, uintptr_t retaddr) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; - - do_unaligned_access(env, addr, retaddr); + do_unaligned_access(cpu_env(cs), addr, retaddr); } #else void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); =20 do_unaligned_access(env, addr, retaddr); cs->exception_index =3D EXCP_UNALIGN; @@ -67,8 +63,7 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retad= dr) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; + CPUAlphaState *env =3D cpu_env(cs); =20 env->trap_arg0 =3D addr; env->trap_arg1 =3D access_type =3D=3D MMU_DATA_STORE ? 1 : 0; diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 32333081d8..d1188194ba 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2917,8 +2917,8 @@ static void alpha_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); 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Mon, 29 Jan 2024 08:46:09 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Alexander Graf Subject: [PATCH v3 08/29] target/arm: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:44:50 +0100 Message-ID: <20240129164514.73104-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22a; envelope-from=philmd@linaro.org; helo=mail-lj1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706547400880100005 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_cpuif.c | 7 ++----- hw/intc/arm_gicv3_cpuif_common.c | 5 +---- target/arm/cpu.c | 19 +++++-------------- target/arm/debug_helper.c | 8 ++------ target/arm/gdbstub.c | 6 ++---- target/arm/gdbstub64.c | 6 ++---- target/arm/helper.c | 9 +++------ target/arm/hvf/hvf.c | 12 ++++-------- target/arm/kvm.c | 3 +-- target/arm/ptw.c | 3 +-- target/arm/tcg/cpu32.c | 4 +--- target/arm/tcg/translate.c | 3 +-- 12 files changed, 25 insertions(+), 60 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index e1a60d8c15..80f64a5154 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -182,8 +182,6 @@ static int hppvi_index(GICv3CPUState *cs) * priority than the highest priority list register at every * callsite of HighestPriorityVirtualInterrupt; we check it here.) */ - ARMCPU *cpu =3D ARM_CPU(cs->cpu); - CPUARMState *env =3D &cpu->env; int idx =3D -1; int i; /* Note that a list register entry with a priority of 0xff will @@ -230,7 +228,7 @@ static int hppvi_index(GICv3CPUState *cs) * fails the priority check here. vLPIs are only considered * when we are in Non-Secure state. */ - if (cs->hppvlpi.prio < prio && !arm_is_secure(env)) { + if (cs->hppvlpi.prio < prio && !arm_is_secure(cpu_env(cs->cpu))) { if (cs->hppvlpi.grp =3D=3D GICV3_G0) { if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0) { return HPPVI_INDEX_VLPI; @@ -931,8 +929,7 @@ void gicv3_cpuif_update(GICv3CPUState *cs) /* Tell the CPU about its highest priority pending interrupt */ int irqlevel =3D 0; int fiqlevel =3D 0; - ARMCPU *cpu =3D ARM_CPU(cs->cpu); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs->cpu); =20 g_assert(bql_locked()); =20 diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_com= mon.c index ff1239f65d..bab3c3cdbd 100644 --- a/hw/intc/arm_gicv3_cpuif_common.c +++ b/hw/intc/arm_gicv3_cpuif_common.c @@ -15,8 +15,5 @@ =20 void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) { - ARMCPU *arm_cpu =3D ARM_CPU(cpu); - CPUARMState *env =3D &arm_cpu->env; - - env->gicv3state =3D (void *)s; + cpu_env(cpu)->gicv3state =3D (void *)s; }; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e5deb5195b..23f4de127f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -53,8 +53,7 @@ =20 static void arm_cpu_set_pc(CPUState *cs, vaddr value) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); =20 if (is_a64(env)) { env->pc =3D value; @@ -67,8 +66,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) =20 static vaddr arm_cpu_get_pc(CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); =20 if (is_a64(env)) { return env->pc; @@ -996,19 +994,15 @@ static void arm_cpu_kvm_set_irq(void *opaque, int irq= , int level) =20 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - cpu_synchronize_state(cs); - return arm_cpu_data_is_big_endian(env); + return arm_cpu_data_is_big_endian(cpu_env(cs)); } =20 #endif =20 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) { - ARMCPU *ac =3D ARM_CPU(cpu); - CPUARMState *env =3D &ac->env; + CPUARMState *env =3D cpu_env(cpu); bool sctlr_b; =20 if (is_a64(env)) { @@ -2435,10 +2429,7 @@ static Property arm_cpu_properties[] =3D { =20 static const gchar *arm_gdb_arch_name(CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { + if (arm_feature(cpu_env(cs), ARM_FEATURE_IWMMXT)) { return "iwmmxt"; } return "arm"; diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 7d856acddf..7bd5467414 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -468,8 +468,7 @@ void arm_debug_excp_handler(CPUState *cs) * Called by core code when a watchpoint or breakpoint fires; * need to check which one and raise the appropriate exception. */ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); CPUWatchpoint *wp_hit =3D cs->watchpoint_hit; =20 if (wp_hit) { @@ -757,9 +756,6 @@ void hw_breakpoint_update_all(ARMCPU *cpu) =20 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - /* * In BE32 system mode, target memory is stored byteswapped (on a * little-endian host system), and by the time we reach here (via an @@ -767,7 +763,7 @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr= addr, int len) * to account for that, which means that watchpoints will not match. * Undo the adjustment here. */ - if (arm_sctlr_b(env)) { + if (arm_sctlr_b(cpu_env(cs))) { if (len =3D=3D 1) { addr ^=3D 3; } else if (len =3D=3D 2) { diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 28f546a5ff..dc6c29669c 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -40,8 +40,7 @@ typedef struct RegisterSysregXmlParam { =20 int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); =20 if (n < 16) { /* Core integer register. */ @@ -61,8 +60,7 @@ int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *m= em_buf, int n) =20 int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); uint32_t tmp; =20 tmp =3D ldl_p(mem_buf); diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index d7b79a6589..b9f29b0a60 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -24,8 +24,7 @@ =20 int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); =20 if (n < 31) { /* Core integer register. */ @@ -45,8 +44,7 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArra= y *mem_buf, int n) =20 int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); uint64_t tmp; =20 tmp =3D ldq_p(mem_buf); diff --git a/target/arm/helper.c b/target/arm/helper.c index 945d8571a6..a9d2c23df2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10902,8 +10902,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUSta= te *cs) * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. */ uint32_t addr, mask; - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); =20 switch (cs->exception_index) { case EXCP_UDEF: @@ -10981,8 +10980,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUSta= te *cs) =20 static void arm_cpu_do_interrupt_aarch32(CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); uint32_t addr; uint32_t mask; int new_mode; @@ -11481,8 +11479,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) #ifdef CONFIG_TCG static void tcg_handle_semihosting(CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); =20 if (is_a64(env)) { qemu_log_mask(CPU_LOG_INT, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index e5f0f60093..849f0772e6 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1006,8 +1006,7 @@ void hvf_kick_vcpu_thread(CPUState *cpu) static void hvf_raise_exception(CPUState *cpu, uint32_t excp, uint32_t syndrome) { - ARMCPU *arm_cpu =3D ARM_CPU(cpu); - CPUARMState *env =3D &arm_cpu->env; + CPUARMState *env =3D cpu_env(cpu); =20 cpu->exception_index =3D excp; env->exception.target_el =3D 1; @@ -1485,8 +1484,7 @@ static bool hvf_sysreg_write_cp(CPUState *cpu, uint32= _t reg, uint64_t val) =20 static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) { - ARMCPU *arm_cpu =3D ARM_CPU(cpu); - CPUARMState *env =3D &arm_cpu->env; + CPUARMState *env =3D cpu_env(cpu); =20 trace_hvf_sysreg_write(reg, SYSREG_OP0(reg), @@ -2152,8 +2150,7 @@ static void hvf_put_gdbstub_debug_registers(CPUState = *cpu) */ static void hvf_put_guest_debug_registers(CPUState *cpu) { - ARMCPU *arm_cpu =3D ARM_CPU(cpu); - CPUARMState *env =3D &arm_cpu->env; + CPUARMState *env =3D cpu_env(cpu); hv_return_t r =3D HV_SUCCESS; int i; =20 @@ -2207,8 +2204,7 @@ static void hvf_arch_set_traps(void) =20 void hvf_arch_update_guest_debug(CPUState *cpu) { - ARMCPU *arm_cpu =3D ARM_CPU(cpu); - CPUARMState *env =3D &arm_cpu->env; + CPUARMState *env =3D cpu_env(cpu); =20 /* Check whether guest debugging is enabled */ cpu->accel->guest_debug_enabled =3D cpu->singlestep_enabled || diff --git a/target/arm/kvm.c b/target/arm/kvm.c index ab85d628a8..cccb512f23 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1958,8 +1958,7 @@ int kvm_arch_destroy_vcpu(CPUState *cs) /* Callers must hold the iothread mutex lock */ static void kvm_inject_arm_sea(CPUState *c) { - ARMCPU *cpu =3D ARM_CPU(c); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(c); uint32_t esr; bool same_el; =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5eb3577bcd..57a761ad68 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3528,8 +3528,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cpu_env(cs); ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); ARMSecuritySpace ss =3D arm_security_space(env); S1Translate ptw =3D { diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index d9e0e2a4dd..e96f1119c0 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -102,8 +102,6 @@ void aa32_max_features(ARMCPU *cpu) static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; bool ret =3D false; =20 /* @@ -115,7 +113,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, in= t interrupt_request) * currently active exception). */ if (interrupt_request & CPU_INTERRUPT_HARD - && (armv7m_nvic_can_take_pending_exception(env->nvic))) { + && (armv7m_nvic_can_take_pending_exception(cpu_env(cs)->nvic))) { cs->exception_index =3D EXCP_IRQ; cc->tcg_ops->do_interrupt(cs); ret =3D true; diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index b3660173d1..ab73250f04 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -9326,7 +9326,6 @@ static void arm_post_translate_insn(DisasContext *dc) static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUARMState *env =3D cpu_env(cpu); uint32_t pc =3D dc->base.pc_next; unsigned int insn; =20 @@ -9356,7 +9355,7 @@ static void arm_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cpu) } =20 dc->pc_curr =3D pc; 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Mon, 29 Jan 2024 08:46:15 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Michael Rolnik Subject: [PATCH v3 09/29] target/avr: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:44:51 +0100 Message-ID: <20240129164514.73104-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706547408329100007 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/avr/cpu.c | 27 +++++++-------------------- target/avr/gdbstub.c | 6 ++---- target/avr/helper.c | 10 +++------- target/avr/translate.c | 3 +-- 4 files changed, 13 insertions(+), 33 deletions(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 0f191a4c9d..50ded8538b 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -43,31 +43,22 @@ static vaddr avr_cpu_get_pc(CPUState *cs) =20 static bool avr_cpu_has_work(CPUState *cs) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; - return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RE= SET)) - && cpu_interrupts_enabled(env); + && cpu_interrupts_enabled(cpu_env(cs)); } =20 static void avr_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - env->pc_w =3D tb->pc / 2; /* internally PC points to words */ + cpu_env(cs)->pc_w =3D tb->pc / 2; /* internally PC points to words */ } =20 static void avr_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; - - env->pc_w =3D data[0]; + cpu_env(cs)->pc_w =3D data[0]; } =20 static void avr_cpu_reset_hold(Object *obj) @@ -165,8 +156,7 @@ static ObjectClass *avr_cpu_class_by_name(const char *c= pu_model) =20 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(cs); int i; =20 qemu_fprintf(f, "\n"); @@ -276,8 +266,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) */ static void avr_avr5_initfn(Object *obj) { - AVRCPU *cpu =3D AVR_CPU(obj); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(CPU(obj)); =20 set_avr_feature(env, AVR_FEATURE_LPM); set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); @@ -305,8 +294,7 @@ static void avr_avr5_initfn(Object *obj) */ static void avr_avr51_initfn(Object *obj) { - AVRCPU *cpu =3D AVR_CPU(obj); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(CPU(obj)); =20 set_avr_feature(env, AVR_FEATURE_LPM); set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); @@ -335,8 +323,7 @@ static void avr_avr51_initfn(Object *obj) */ static void avr_avr6_initfn(Object *obj) { - AVRCPU *cpu =3D AVR_CPU(obj); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(CPU(obj)); =20 set_avr_feature(env, AVR_FEATURE_LPM); set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); diff --git a/target/avr/gdbstub.c b/target/avr/gdbstub.c index 150344d8b9..2eeee2bf4e 100644 --- a/target/avr/gdbstub.c +++ b/target/avr/gdbstub.c @@ -23,8 +23,7 @@ =20 int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(cs); =20 /* R */ if (n < 32) { @@ -53,8 +52,7 @@ int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *m= em_buf, int n) =20 int avr_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(cs); =20 /* R */ if (n < 32) { diff --git a/target/avr/helper.c b/target/avr/helper.c index fdc9884ea0..eeca415c43 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -30,8 +30,7 @@ =20 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(cs); =20 /* * We cannot separate a skip from the next instruction, @@ -69,8 +68,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_r= equest) =20 void avr_cpu_do_interrupt(CPUState *cs) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(cs); =20 uint32_t ret =3D env->pc_w; int vector =3D 0; @@ -144,9 +142,7 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, if (probe) { page_size =3D 1; } else { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; - env->fullacc =3D 1; + cpu_env(cs)->fullacc =3D 1; cpu_loop_exit_restore(cs, retaddr); } } diff --git a/target/avr/translate.c b/target/avr/translate.c index cdffa04519..682a44139e 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2657,11 +2657,10 @@ static bool canonicalize_skip(DisasContext *ctx) static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUAVRState *env =3D cpu_env(cs); uint32_t tb_flags =3D ctx->base.tb->flags; =20 ctx->cs =3D cs; - ctx->env =3D env; + ctx->env =3D cpu_env(cs); ctx->npc =3D ctx->base.pc_first / 2; =20 ctx->skip_cond =3D TCG_COND_NEVER; --=20 2.41.0 From nobody Tue Nov 26 14:27:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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Iglesias" Subject: [PATCH v3 10/29] target/cris: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:44:52 +0100 Message-ID: <20240129164514.73104-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706546929282100002 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/cris/cpu.c | 10 +++------- target/cris/gdbstub.c | 9 +++------ target/cris/helper.c | 12 ++++-------- target/cris/translate.c | 6 ++---- 4 files changed, 12 insertions(+), 25 deletions(-) diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 4187e0ef3c..122071f142 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -58,10 +58,9 @@ static bool cris_cpu_has_work(CPUState *cs) =20 static void cris_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(obj); - CRISCPU *cpu =3D CRIS_CPU(s); + CPUState *cs =3D CPU(obj); CRISCPUClass *ccc =3D CRIS_CPU_GET_CLASS(obj); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); uint32_t vr; =20 if (ccc->parent_phases.hold) { @@ -142,10 +141,7 @@ static void cris_cpu_set_irq(void *opaque, int irq, in= t level) =20 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) { - CRISCPU *cc =3D CRIS_CPU(cpu); - CPUCRISState *env =3D &cc->env; - - if (env->pregs[PR_VR] !=3D 32) { + if (cpu_env(cpu)->pregs[PR_VR] !=3D 32) { info->mach =3D bfd_mach_cris_v0_v10; info->print_insn =3D print_insn_crisv10; } else { diff --git a/target/cris/gdbstub.c b/target/cris/gdbstub.c index 25c0ca33a5..9e87069da8 100644 --- a/target/cris/gdbstub.c +++ b/target/cris/gdbstub.c @@ -23,8 +23,7 @@ =20 int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); =20 if (n < 15) { return gdb_get_reg32(mem_buf, env->regs[n]); @@ -55,8 +54,7 @@ int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArra= y *mem_buf, int n) =20 int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); uint8_t srs; =20 srs =3D env->pregs[PR_SRS]; @@ -90,8 +88,7 @@ int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *= mem_buf, int n) =20 int cris_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); uint32_t tmp; =20 if (n > 49) { diff --git a/target/cris/helper.c b/target/cris/helper.c index c0bf987e3e..1c3f86876f 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -53,8 +53,7 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); struct cris_mmu_result res; int prot, miss; target_ulong phy; @@ -97,8 +96,7 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, =20 void crisv10_cpu_do_interrupt(CPUState *cs) { - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); int ex_vec =3D -1; =20 D_LOG("exception index=3D%d interrupt_req=3D%d\n", @@ -159,8 +157,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) =20 void cris_cpu_do_interrupt(CPUState *cs) { - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); int ex_vec =3D -1; =20 D_LOG("exception index=3D%d interrupt_req=3D%d\n", @@ -262,8 +259,7 @@ hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); bool ret =3D false; =20 if (interrupt_request & CPU_INTERRUPT_HARD diff --git a/target/cris/translate.c b/target/cris/translate.c index b3974ba0bb..5213db820b 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3006,7 +3006,6 @@ static void cris_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUCRISState *env =3D cpu_env(cs); unsigned int insn_len; =20 /* Pretty disas. */ @@ -3014,7 +3013,7 @@ static void cris_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) =20 dc->clear_x =3D 1; =20 - insn_len =3D dc->decoder(env, dc); + insn_len =3D dc->decoder(cpu_env(cs), dc); dc->ppc =3D dc->pc; dc->pc +=3D insn_len; dc->base.pc_next +=3D insn_len; @@ -3180,8 +3179,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int *max_insns, =20 void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); const char * const *regnames; const char * const *pregnames; int i; --=20 2.41.0 From nobody Tue Nov 26 14:27:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706546889; cv=none; d=zohomail.com; s=zohoarc; b=aN84QgDyburdVbKiX14EqKZbJ17dyOuodjFpbQVD/jgIGoHF6RHKsH8uFNGmKyrreTWcTktJ9uv922/Rpkag0sYOTKu64HI0F5J0oGyADPXip6pQyJfB4n/tX22q03+DK2CyvyKG/Y1dWrzI/EEZsx19HitiQH3LRAKN/lt1lA0= ARC-Message-Signature: i=1; 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Mon, 29 Jan 2024 08:46:27 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Brian Cain Subject: [PATCH v3 11/29] target/hexagon: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:44:53 +0100 Message-ID: <20240129164514.73104-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706546891122100004 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Brian Cain Reviewed-by: Richard Henderson --- target/hexagon/cpu.c | 25 ++++++------------------- target/hexagon/gdbstub.c | 6 ++---- 2 files changed, 8 insertions(+), 23 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 085d6c0115..17a22aa7a5 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -236,10 +236,7 @@ static void hexagon_dump(CPUHexagonState *env, FILE *f= , int flags) =20 static void hexagon_dump_state(CPUState *cs, FILE *f, int flags) { - HexagonCPU *cpu =3D HEXAGON_CPU(cs); - CPUHexagonState *env =3D &cpu->env; - - hexagon_dump(env, f, flags); + hexagon_dump(cpu_env(cs), f, flags); } =20 void hexagon_debug(CPUHexagonState *env) @@ -249,25 +246,19 @@ void hexagon_debug(CPUHexagonState *env) =20 static void hexagon_cpu_set_pc(CPUState *cs, vaddr value) { - HexagonCPU *cpu =3D HEXAGON_CPU(cs); - CPUHexagonState *env =3D &cpu->env; - env->gpr[HEX_REG_PC] =3D value; + cpu_env(cs)->gpr[HEX_REG_PC] =3D value; } =20 static vaddr hexagon_cpu_get_pc(CPUState *cs) { - HexagonCPU *cpu =3D HEXAGON_CPU(cs); - CPUHexagonState *env =3D &cpu->env; - return env->gpr[HEX_REG_PC]; + return cpu_env(cs)->gpr[HEX_REG_PC]; } =20 static void hexagon_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - HexagonCPU *cpu =3D HEXAGON_CPU(cs); - CPUHexagonState *env =3D &cpu->env; tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - env->gpr[HEX_REG_PC] =3D tb->pc; + cpu_env(cs)->gpr[HEX_REG_PC] =3D tb->pc; } =20 static bool hexagon_cpu_has_work(CPUState *cs) @@ -279,18 +270,14 @@ static void hexagon_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - HexagonCPU *cpu =3D HEXAGON_CPU(cs); - CPUHexagonState *env =3D &cpu->env; - - env->gpr[HEX_REG_PC] =3D data[0]; + cpu_env(cs)->gpr[HEX_REG_PC] =3D data[0]; } =20 static void hexagon_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); - HexagonCPU *cpu =3D HEXAGON_CPU(cs); HexagonCPUClass *mcc =3D HEXAGON_CPU_GET_CLASS(obj); - CPUHexagonState *env =3D &cpu->env; + CPUHexagonState *env =3D cpu_env(cs); =20 if (mcc->parent_phases.hold) { mcc->parent_phases.hold(obj); diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index 54d37e006e..f773f8ea4f 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -22,8 +22,7 @@ =20 int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - HexagonCPU *cpu =3D HEXAGON_CPU(cs); - CPUHexagonState *env =3D &cpu->env; + CPUHexagonState *env =3D cpu_env(cs); =20 if (n =3D=3D HEX_REG_P3_0_ALIASED) { uint32_t p3_0 =3D 0; @@ -42,8 +41,7 @@ int hexagon_gdb_read_register(CPUState *cs, GByteArray *m= em_buf, int n) =20 int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - HexagonCPU *cpu =3D HEXAGON_CPU(cs); - CPUHexagonState *env =3D &cpu->env; + CPUHexagonState *env =3D cpu_env(cs); =20 if (n =3D=3D HEX_REG_P3_0_ALIASED) { uint32_t p3_0 =3D ldtul_p(mem_buf); --=20 2.41.0 From nobody Tue Nov 26 14:27:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 29 Jan 2024 08:46:33 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 12/29] target/hppa: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:44:54 +0100 Message-ID: <20240129164514.73104-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706547185839100003 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.c | 8 ++------ target/hppa/int_helper.c | 8 ++------ target/hppa/mem_helper.c | 3 +-- 3 files changed, 5 insertions(+), 14 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 14e17fa9aa..3200de0998 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -106,11 +106,8 @@ void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - HPPACPU *cpu =3D HPPA_CPU(cs); - CPUHPPAState *env =3D &cpu->env; - cs->exception_index =3D EXCP_UNALIGN; - hppa_set_ior_and_isr(env, addr, MMU_IDX_MMU_DISABLED(mmu_idx)); + hppa_set_ior_and_isr(cpu_env(cs), addr, MMU_IDX_MMU_DISABLED(mmu_idx)); =20 cpu_loop_exit_restore(cs, retaddr); } @@ -145,8 +142,7 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error = **errp) static void hppa_cpu_initfn(Object *obj) { CPUState *cs =3D CPU(obj); - HPPACPU *cpu =3D HPPA_CPU(obj); - CPUHPPAState *env =3D &cpu->env; + CPUHPPAState *env =3D cpu_env(CPU(obj)); =20 cs->exception_index =3D -1; cpu_hppa_loaded_fr0(env); diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index efe638b36e..d072ad2af7 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -99,8 +99,7 @@ void HELPER(write_eiem)(CPUHPPAState *env, target_ulong v= al) =20 void hppa_cpu_do_interrupt(CPUState *cs) { - HPPACPU *cpu =3D HPPA_CPU(cs); - CPUHPPAState *env =3D &cpu->env; + CPUHPPAState *env =3D cpu_env(cs); int i =3D cs->exception_index; uint64_t old_psw; =20 @@ -268,9 +267,6 @@ void hppa_cpu_do_interrupt(CPUState *cs) =20 bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - HPPACPU *cpu =3D HPPA_CPU(cs); - CPUHPPAState *env =3D &cpu->env; - if (interrupt_request & CPU_INTERRUPT_NMI) { /* Raise TOC (NMI) interrupt */ cpu_reset_interrupt(cs, CPU_INTERRUPT_NMI); @@ -280,7 +276,7 @@ bool hppa_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) } =20 /* If interrupts are requested and enabled, raise them. */ - if ((env->psw & PSW_I) && (interrupt_request & CPU_INTERRUPT_HARD)) { + if ((cpu_env(cs)->psw & PSW_I) && (interrupt_request & CPU_INTERRUPT_H= ARD)) { cs->exception_index =3D EXCP_EXT_INTERRUPT; hppa_cpu_do_interrupt(cs); return true; diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index bb85962d50..7e73b80788 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -357,8 +357,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int si= ze, MMUAccessType type, int mmu_idx, bool probe, uintptr_t retaddr) { - HPPACPU *cpu =3D HPPA_CPU(cs); - CPUHPPAState *env =3D &cpu->env; + CPUHPPAState *env =3D cpu_env(cs); HPPATLBEntry *ent; int prot, excp, a_prot; hwaddr phys; --=20 2.41.0 From nobody Tue Nov 26 14:27:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706547406; cv=none; d=zohomail.com; s=zohoarc; b=eXBjjZOsSCpfmulfIBpXPjK4zkEWoiQe8T/dGFWMMOdxvYpSon4Akvw+mG7Kbl6zzmsMnHrEn/CN5MlqBNqe/1VNCLP2K6E4idh/y89/9ini2/nHxKRswBC6KSGES1oU3Y6QanqhfyBLgURPS9Qb5kUnkvfVktFgrRZoopjkXVM= ARC-Message-Signature: i=1; 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Mon, 29 Jan 2024 08:46:39 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Cameron Esfahani , Roman Bolshakov Subject: [PATCH v3 13/29] target/i386/hvf: Use CPUState typedef Date: Mon, 29 Jan 2024 17:44:55 +0100 Message-ID: <20240129164514.73104-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706547408357100008 QEMU coding style recommend using structure typedefs: https://www.qemu.org/docs/master/devel/style.html#typedefs Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu --- target/i386/hvf/x86.h | 26 +++++++++++++------------- target/i386/hvf/x86_descr.h | 14 +++++++------- target/i386/hvf/x86_emu.h | 4 ++-- target/i386/hvf/x86_mmu.h | 6 +++--- target/i386/hvf/x86.c | 26 +++++++++++++------------- target/i386/hvf/x86_descr.c | 8 ++++---- target/i386/hvf/x86_mmu.c | 14 +++++++------- 7 files changed, 49 insertions(+), 49 deletions(-) diff --git a/target/i386/hvf/x86.h b/target/i386/hvf/x86.h index 947b98da41..3570f29aa9 100644 --- a/target/i386/hvf/x86.h +++ b/target/i386/hvf/x86.h @@ -248,30 +248,30 @@ typedef struct x68_segment_selector { #define BH(cpu) RH(cpu, R_EBX) =20 /* deal with GDT/LDT descriptors in memory */ -bool x86_read_segment_descriptor(struct CPUState *cpu, +bool x86_read_segment_descriptor(CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel); -bool x86_write_segment_descriptor(struct CPUState *cpu, +bool x86_write_segment_descriptor(CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel); =20 -bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_de= sc, +bool x86_read_call_gate(CPUState *cpu, struct x86_call_gate *idt_desc, int gate); =20 /* helpers */ -bool x86_is_protected(struct CPUState *cpu); -bool x86_is_real(struct CPUState *cpu); -bool x86_is_v8086(struct CPUState *cpu); -bool x86_is_long_mode(struct CPUState *cpu); -bool x86_is_long64_mode(struct CPUState *cpu); -bool x86_is_paging_mode(struct CPUState *cpu); -bool x86_is_pae_enabled(struct CPUState *cpu); +bool x86_is_protected(CPUState *cpu); +bool x86_is_real(CPUState *cpu); +bool x86_is_v8086(CPUState *cpu); +bool x86_is_long_mode(CPUState *cpu); +bool x86_is_long64_mode(CPUState *cpu); +bool x86_is_paging_mode(CPUState *cpu); +bool x86_is_pae_enabled(CPUState *cpu); =20 enum X86Seg; -target_ulong linear_addr(struct CPUState *cpu, target_ulong addr, enum X86= Seg seg); -target_ulong linear_addr_size(struct CPUState *cpu, target_ulong addr, int= size, +target_ulong linear_addr(CPUState *cpu, target_ulong addr, enum X86Seg seg= ); +target_ulong linear_addr_size(CPUState *cpu, target_ulong addr, int size, enum X86Seg seg); -target_ulong linear_rip(struct CPUState *cpu, target_ulong rip); +target_ulong linear_rip(CPUState *cpu, target_ulong rip); =20 static inline uint64_t rdtscp(void) { diff --git a/target/i386/hvf/x86_descr.h b/target/i386/hvf/x86_descr.h index c356932fa4..9f06014b56 100644 --- a/target/i386/hvf/x86_descr.h +++ b/target/i386/hvf/x86_descr.h @@ -29,29 +29,29 @@ typedef struct vmx_segment { } vmx_segment; =20 /* deal with vmstate descriptors */ -void vmx_read_segment_descriptor(struct CPUState *cpu, +void vmx_read_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, enum X86Seg seg= ); void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, enum X86Seg seg); =20 -x68_segment_selector vmx_read_segment_selector(struct CPUState *cpu, +x68_segment_selector vmx_read_segment_selector(CPUState *cpu, enum X86Seg seg); -void vmx_write_segment_selector(struct CPUState *cpu, +void vmx_write_segment_selector(CPUState *cpu, x68_segment_selector selector, enum X86Seg seg); =20 -uint64_t vmx_read_segment_base(struct CPUState *cpu, enum X86Seg seg); -void vmx_write_segment_base(struct CPUState *cpu, enum X86Seg seg, +uint64_t vmx_read_segment_base(CPUState *cpu, enum X86Seg seg); +void vmx_write_segment_base(CPUState *cpu, enum X86Seg seg, uint64_t base); =20 -void x86_segment_descriptor_to_vmx(struct CPUState *cpu, +void x86_segment_descriptor_to_vmx(CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc); =20 uint32_t vmx_read_segment_limit(CPUState *cpu, enum X86Seg seg); uint32_t vmx_read_segment_ar(CPUState *cpu, enum X86Seg seg); -void vmx_segment_to_x86_descriptor(struct CPUState *cpu, +void vmx_segment_to_x86_descriptor(CPUState *cpu, struct vmx_segment *vmx_desc, struct x86_segment_descriptor *desc); =20 diff --git a/target/i386/hvf/x86_emu.h b/target/i386/hvf/x86_emu.h index 4b846ba80e..8bd97608c4 100644 --- a/target/i386/hvf/x86_emu.h +++ b/target/i386/hvf/x86_emu.h @@ -26,8 +26,8 @@ void init_emu(void); bool exec_instruction(CPUX86State *env, struct x86_decode *ins); =20 -void load_regs(struct CPUState *cpu); -void store_regs(struct CPUState *cpu); +void load_regs(CPUState *cpu); +void store_regs(CPUState *cpu); =20 void simulate_rdmsr(CPUX86State *env); void simulate_wrmsr(CPUX86State *env); diff --git a/target/i386/hvf/x86_mmu.h b/target/i386/hvf/x86_mmu.h index 9ae8a548de..9447ae072c 100644 --- a/target/i386/hvf/x86_mmu.h +++ b/target/i386/hvf/x86_mmu.h @@ -36,9 +36,9 @@ #define MMU_PAGE_US (1 << 2) #define MMU_PAGE_NX (1 << 3) =20 -bool mmu_gva_to_gpa(struct CPUState *cpu, target_ulong gva, uint64_t *gpa); +bool mmu_gva_to_gpa(CPUState *cpu, target_ulong gva, uint64_t *gpa); =20 -void vmx_write_mem(struct CPUState *cpu, target_ulong gva, void *data, int= bytes); -void vmx_read_mem(struct CPUState *cpu, void *data, target_ulong gva, int = bytes); +void vmx_write_mem(CPUState *cpu, target_ulong gva, void *data, int bytes); +void vmx_read_mem(CPUState *cpu, void *data, target_ulong gva, int bytes); =20 #endif /* X86_MMU_H */ diff --git a/target/i386/hvf/x86.c b/target/i386/hvf/x86.c index 8ceea6398e..80e36136d0 100644 --- a/target/i386/hvf/x86.c +++ b/target/i386/hvf/x86.c @@ -46,7 +46,7 @@ return ar; }*/ =20 -bool x86_read_segment_descriptor(struct CPUState *cpu, +bool x86_read_segment_descriptor(CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel) { @@ -76,7 +76,7 @@ bool x86_read_segment_descriptor(struct CPUState *cpu, return true; } =20 -bool x86_write_segment_descriptor(struct CPUState *cpu, +bool x86_write_segment_descriptor(CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel) { @@ -99,7 +99,7 @@ bool x86_write_segment_descriptor(struct CPUState *cpu, return true; } =20 -bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_de= sc, +bool x86_read_call_gate(CPUState *cpu, struct x86_call_gate *idt_desc, int gate) { target_ulong base =3D rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_BASE); @@ -115,30 +115,30 @@ bool x86_read_call_gate(struct CPUState *cpu, struct = x86_call_gate *idt_desc, return true; } =20 -bool x86_is_protected(struct CPUState *cpu) +bool x86_is_protected(CPUState *cpu) { uint64_t cr0 =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR0); return cr0 & CR0_PE_MASK; } =20 -bool x86_is_real(struct CPUState *cpu) +bool x86_is_real(CPUState *cpu) { return !x86_is_protected(cpu); } =20 -bool x86_is_v8086(struct CPUState *cpu) +bool x86_is_v8086(CPUState *cpu) { X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; return x86_is_protected(cpu) && (env->eflags & VM_MASK); } =20 -bool x86_is_long_mode(struct CPUState *cpu) +bool x86_is_long_mode(CPUState *cpu) { return rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA; } =20 -bool x86_is_long64_mode(struct CPUState *cpu) +bool x86_is_long64_mode(CPUState *cpu) { struct vmx_segment desc; vmx_read_segment_descriptor(cpu, &desc, R_CS); @@ -146,24 +146,24 @@ bool x86_is_long64_mode(struct CPUState *cpu) return x86_is_long_mode(cpu) && ((desc.ar >> 13) & 1); } =20 -bool x86_is_paging_mode(struct CPUState *cpu) +bool x86_is_paging_mode(CPUState *cpu) { uint64_t cr0 =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR0); return cr0 & CR0_PG_MASK; } =20 -bool x86_is_pae_enabled(struct CPUState *cpu) +bool x86_is_pae_enabled(CPUState *cpu) { uint64_t cr4 =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR4); return cr4 & CR4_PAE_MASK; } =20 -target_ulong linear_addr(struct CPUState *cpu, target_ulong addr, X86Seg s= eg) +target_ulong linear_addr(CPUState *cpu, target_ulong addr, X86Seg seg) { return vmx_read_segment_base(cpu, seg) + addr; } =20 -target_ulong linear_addr_size(struct CPUState *cpu, target_ulong addr, int= size, +target_ulong linear_addr_size(CPUState *cpu, target_ulong addr, int size, X86Seg seg) { switch (size) { @@ -179,7 +179,7 @@ target_ulong linear_addr_size(struct CPUState *cpu, tar= get_ulong addr, int size, return linear_addr(cpu, addr, seg); } =20 -target_ulong linear_rip(struct CPUState *cpu, target_ulong rip) +target_ulong linear_rip(CPUState *cpu, target_ulong rip) { return linear_addr(cpu, rip, R_CS); } diff --git a/target/i386/hvf/x86_descr.c b/target/i386/hvf/x86_descr.c index c2d2e9ee84..5a9e8d307c 100644 --- a/target/i386/hvf/x86_descr.c +++ b/target/i386/hvf/x86_descr.c @@ -67,12 +67,12 @@ x68_segment_selector vmx_read_segment_selector(CPUState= *cpu, X86Seg seg) return sel; } =20 -void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector= selector, X86Seg seg) +void vmx_write_segment_selector(CPUState *cpu, x68_segment_selector select= or, X86Seg seg) { wvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector, selector.sel); } =20 -void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment = *desc, X86Seg seg) +void vmx_read_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, = X86Seg seg) { desc->sel =3D rvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector); desc->base =3D rvmcs(cpu->accel->fd, vmx_segment_fields[seg].base); @@ -90,7 +90,7 @@ void vmx_write_segment_descriptor(CPUState *cpu, struct v= mx_segment *desc, X86Se wvmcs(cpu->accel->fd, sf->ar_bytes, desc->ar); } =20 -void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selec= tor selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_= desc) +void x86_segment_descriptor_to_vmx(CPUState *cpu, x68_segment_selector sel= ector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc) { vmx_desc->sel =3D selector.sel; vmx_desc->base =3D x86_segment_base(desc); @@ -107,7 +107,7 @@ void x86_segment_descriptor_to_vmx(struct CPUState *cpu= , x68_segment_selector se desc->type; } =20 -void vmx_segment_to_x86_descriptor(struct CPUState *cpu, struct vmx_segmen= t *vmx_desc, struct x86_segment_descriptor *desc) +void vmx_segment_to_x86_descriptor(CPUState *cpu, struct vmx_segment *vmx_= desc, struct x86_segment_descriptor *desc) { x86_set_segment_limit(desc, vmx_desc->limit); x86_set_segment_base(desc, vmx_desc->base); diff --git a/target/i386/hvf/x86_mmu.c b/target/i386/hvf/x86_mmu.c index 8cd08622a1..649074a7d2 100644 --- a/target/i386/hvf/x86_mmu.c +++ b/target/i386/hvf/x86_mmu.c @@ -49,7 +49,7 @@ struct gpt_translation { bool exec_access; }; =20 -static int gpt_top_level(struct CPUState *cpu, bool pae) +static int gpt_top_level(CPUState *cpu, bool pae) { if (!pae) { return 2; @@ -73,7 +73,7 @@ static inline int pte_size(bool pae) } =20 =20 -static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, +static bool get_pt_entry(CPUState *cpu, struct gpt_translation *pt, int level, bool pae) { int index; @@ -95,7 +95,7 @@ static bool get_pt_entry(struct CPUState *cpu, struct gpt= _translation *pt, } =20 /* test page table entry */ -static bool test_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, +static bool test_pt_entry(CPUState *cpu, struct gpt_translation *pt, int level, bool *is_large, bool pae) { uint64_t pte =3D pt->pte[level]; @@ -166,7 +166,7 @@ static inline uint64_t large_page_gpa(struct gpt_transl= ation *pt, bool pae) =20 =20 =20 -static bool walk_gpt(struct CPUState *cpu, target_ulong addr, int err_code, +static bool walk_gpt(CPUState *cpu, target_ulong addr, int err_code, struct gpt_translation *pt, bool pae) { int top_level, level; @@ -205,7 +205,7 @@ static bool walk_gpt(struct CPUState *cpu, target_ulong= addr, int err_code, } =20 =20 -bool mmu_gva_to_gpa(struct CPUState *cpu, target_ulong gva, uint64_t *gpa) +bool mmu_gva_to_gpa(CPUState *cpu, target_ulong gva, uint64_t *gpa) { bool res; struct gpt_translation pt; @@ -225,7 +225,7 @@ bool mmu_gva_to_gpa(struct CPUState *cpu, target_ulong = gva, uint64_t *gpa) return false; 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Mon, 29 Jan 2024 08:46:46 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Eduardo Habkost , Stefano Stabellini , Anthony Perard , Paul Durrant , Cameron Esfahani , Roman Bolshakov , Marcelo Tosatti , David Woodhouse , xen-devel@lists.xenproject.org Subject: [PATCH v3 14/29] target/i386: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:44:56 +0100 Message-ID: <20240129164514.73104-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706546827105100001 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: David Woodhouse Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu --- target/i386/hvf/vmx.h | 13 ++------- hw/i386/fw_cfg.c | 3 +- hw/i386/vmmouse.c | 6 ++-- hw/i386/xen/xen-hvm.c | 3 +- target/i386/arch_dump.c | 11 ++------ target/i386/arch_memory_mapping.c | 3 +- target/i386/cpu-dump.c | 3 +- target/i386/cpu.c | 37 ++++++++---------------- target/i386/helper.c | 42 ++++++++-------------------- target/i386/hvf/hvf.c | 8 ++---- target/i386/hvf/x86.c | 4 +-- target/i386/hvf/x86_emu.c | 6 ++-- target/i386/hvf/x86_task.c | 10 ++----- target/i386/hvf/x86hvf.c | 9 ++---- target/i386/kvm/kvm.c | 6 ++-- target/i386/kvm/xen-emu.c | 32 +++++++-------------- target/i386/tcg/sysemu/bpt_helper.c | 3 +- target/i386/tcg/sysemu/excp_helper.c | 3 +- target/i386/tcg/tcg-cpu.c | 14 +++------- target/i386/tcg/user/excp_helper.c | 6 ++-- target/i386/tcg/user/seg_helper.c | 3 +- 21 files changed, 67 insertions(+), 158 deletions(-) diff --git a/target/i386/hvf/vmx.h b/target/i386/hvf/vmx.h index 0fffcfa46c..1ad042269b 100644 --- a/target/i386/hvf/vmx.h +++ b/target/i386/hvf/vmx.h @@ -175,8 +175,7 @@ static inline void macvm_set_cr4(hv_vcpuid_t vcpu, uint= 64_t cr4) =20 static inline void macvm_set_rip(CPUState *cpu, uint64_t rip) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; + CPUX86State *env =3D cpu_env(cpu); uint64_t val; =20 /* BUG, should take considering overlap.. */ @@ -196,10 +195,7 @@ static inline void macvm_set_rip(CPUState *cpu, uint64= _t rip) =20 static inline void vmx_clear_nmi_blocking(CPUState *cpu) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; - - env->hflags2 &=3D ~HF2_NMI_MASK; + cpu_env(cpu)->hflags2 &=3D ~HF2_NMI_MASK; uint32_t gi =3D (uint32_t) rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTI= BILITY); gi &=3D ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING; wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); @@ -207,10 +203,7 @@ static inline void vmx_clear_nmi_blocking(CPUState *cp= u) =20 static inline void vmx_set_nmi_blocking(CPUState *cpu) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; - - env->hflags2 |=3D HF2_NMI_MASK; + cpu_env(cpu)->hflags2 |=3D HF2_NMI_MASK; uint32_t gi =3D (uint32_t)rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIB= ILITY); gi |=3D VMCS_INTERRUPTIBILITY_NMI_BLOCKING; wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index 7362daa45a..5239cd40fa 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -155,8 +155,7 @@ FWCfgState *fw_cfg_arch_create(MachineState *ms, =20 void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg) { - X86CPU *cpu =3D X86_CPU(ms->possible_cpus->cpus[0].cpu); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(ms->possible_cpus->cpus[0].cpu); uint32_t unused, ebx, ecx, edx; uint64_t feature_control_bits =3D 0; uint64_t *val; diff --git a/hw/i386/vmmouse.c b/hw/i386/vmmouse.c index a8d014d09a..f292a14a15 100644 --- a/hw/i386/vmmouse.c +++ b/hw/i386/vmmouse.c @@ -74,8 +74,7 @@ struct VMMouseState { =20 static void vmmouse_get_data(uint32_t *data) { - X86CPU *cpu =3D X86_CPU(current_cpu); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(current_cpu); =20 data[0] =3D env->regs[R_EAX]; data[1] =3D env->regs[R_EBX]; data[2] =3D env->regs[R_ECX]; data[3] =3D env->regs[R_EDX]; @@ -84,8 +83,7 @@ static void vmmouse_get_data(uint32_t *data) =20 static void vmmouse_set_data(const uint32_t *data) { - X86CPU *cpu =3D X86_CPU(current_cpu); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(current_cpu); =20 env->regs[R_EAX] =3D data[0]; env->regs[R_EBX] =3D data[1]; env->regs[R_ECX] =3D data[2]; env->regs[R_EDX] =3D data[3]; diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index f42621e674..61e5060117 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -487,8 +487,7 @@ static void regs_to_cpu(vmware_regs_t *vmport_regs, ior= eq_t *req) =20 static void regs_from_cpu(vmware_regs_t *vmport_regs) { - X86CPU *cpu =3D X86_CPU(current_cpu); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(current_cpu); =20 vmport_regs->ebx =3D env->regs[R_EBX]; vmport_regs->ecx =3D env->regs[R_ECX]; diff --git a/target/i386/arch_dump.c b/target/i386/arch_dump.c index c290910a04..8939ff9fa9 100644 --- a/target/i386/arch_dump.c +++ b/target/i386/arch_dump.c @@ -203,7 +203,6 @@ int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, C= PUState *cs, int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, DumpState *s) { - X86CPU *cpu =3D X86_CPU(cs); x86_elf_prstatus prstatus; Elf32_Nhdr *note; char *buf; @@ -211,7 +210,7 @@ int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, C= PUState *cs, const char *name =3D "CORE"; int ret; =20 - x86_fill_elf_prstatus(&prstatus, &cpu->env, cpuid); + x86_fill_elf_prstatus(&prstatus, cpu_env(cs), cpuid); descsz =3D sizeof(x86_elf_prstatus); note_size =3D ELF_NOTE_SIZE(sizeof(Elf32_Nhdr), name_size, descsz); note =3D g_malloc0(note_size); @@ -381,17 +380,13 @@ static inline int cpu_write_qemu_note(WriteCoreDumpFu= nction f, int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cs, DumpState *s) { - X86CPU *cpu =3D X86_CPU(cs); - - return cpu_write_qemu_note(f, &cpu->env, s, 1); + return cpu_write_qemu_note(f, cpu_env(cs), s, 1); } =20 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cs, DumpState *s) { - X86CPU *cpu =3D X86_CPU(cs); - - return cpu_write_qemu_note(f, &cpu->env, s, 0); + return cpu_write_qemu_note(f, cpu_env(cs), s, 0); } =20 int cpu_get_dump_info(ArchDumpInfo *info, diff --git a/target/i386/arch_memory_mapping.c b/target/i386/arch_memory_ma= pping.c index d1ff659128..c0604d5956 100644 --- a/target/i386/arch_memory_mapping.c +++ b/target/i386/arch_memory_mapping.c @@ -269,8 +269,7 @@ static void walk_pml5e(MemoryMappingList *list, Address= Space *as, bool x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list, Error **errp) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); int32_t a20_mask; =20 if (!cpu_paging_enabled(cs)) { diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c index 40697064d9..5459d84abd 100644 --- a/target/i386/cpu-dump.c +++ b/target/i386/cpu-dump.c @@ -343,8 +343,7 @@ void x86_cpu_dump_local_apic_state(CPUState *cs, int fl= ags) =20 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); int eflags, i, nb; char cc_op_name[32]; static const char *seg_name[6] =3D { "ES", "CS", "SS", "DS", "FS", "GS= " }; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 66345c204a..5d7a266d27 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5062,8 +5062,7 @@ static void x86_cpuid_version_get_family(Object *obj,= Visitor *v, const char *name, void *opaque, Error **errp) { - X86CPU *cpu =3D X86_CPU(obj); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(CPU(obj)); int64_t value; =20 value =3D (env->cpuid_version >> 8) & 0xf; @@ -5077,8 +5076,7 @@ static void x86_cpuid_version_set_family(Object *obj,= Visitor *v, const char *name, void *opaque, Error **errp) { - X86CPU *cpu =3D X86_CPU(obj); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(CPU(obj)); const int64_t min =3D 0; const int64_t max =3D 0xff + 0xf; int64_t value; @@ -5104,8 +5102,7 @@ static void x86_cpuid_version_get_model(Object *obj, = Visitor *v, const char *name, void *opaque, Error **errp) { - X86CPU *cpu =3D X86_CPU(obj); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(CPU(obj)); int64_t value; =20 value =3D (env->cpuid_version >> 4) & 0xf; @@ -5117,8 +5114,7 @@ static void x86_cpuid_version_set_model(Object *obj, = Visitor *v, const char *name, void *opaque, Error **errp) { - X86CPU *cpu =3D X86_CPU(obj); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(CPU(obj)); const int64_t min =3D 0; const int64_t max =3D 0xff; int64_t value; @@ -5140,11 +5136,9 @@ static void x86_cpuid_version_get_stepping(Object *o= bj, Visitor *v, const char *name, void *opaque, Error **errp) { - X86CPU *cpu =3D X86_CPU(obj); - CPUX86State *env =3D &cpu->env; int64_t value; =20 - value =3D env->cpuid_version & 0xf; + value =3D cpu_env(CPU(obj))->cpuid_version & 0xf; visit_type_int(v, name, &value, errp); } =20 @@ -5152,8 +5146,7 @@ static void x86_cpuid_version_set_stepping(Object *ob= j, Visitor *v, const char *name, void *opaque, Error **errp) { - X86CPU *cpu =3D X86_CPU(obj); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(CPU(obj)); const int64_t min =3D 0; const int64_t max =3D 0xf; int64_t value; @@ -5173,8 +5166,7 @@ static void x86_cpuid_version_set_stepping(Object *ob= j, Visitor *v, =20 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) { - X86CPU *cpu =3D X86_CPU(obj); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(CPU(obj)); char *value; =20 value =3D g_malloc(CPUID_VENDOR_SZ + 1); @@ -5186,8 +5178,7 @@ static char *x86_cpuid_get_vendor(Object *obj, Error = **errp) static void x86_cpuid_set_vendor(Object *obj, const char *value, Error **errp) { - X86CPU *cpu =3D X86_CPU(obj); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(CPU(obj)); int i; =20 if (strlen(value) !=3D CPUID_VENDOR_SZ) { @@ -5208,8 +5199,7 @@ static void x86_cpuid_set_vendor(Object *obj, const c= har *value, =20 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) { - X86CPU *cpu =3D X86_CPU(obj); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(CPU(obj)); char *value; int i; =20 @@ -5224,8 +5214,7 @@ static char *x86_cpuid_get_model_id(Object *obj, Erro= r **errp) static void x86_cpuid_set_model_id(Object *obj, const char *model_id, Error **errp) { - X86CPU *cpu =3D X86_CPU(obj); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(CPU(obj)); int c, len, i; =20 if (model_id =3D=3D NULL) { @@ -7673,8 +7662,7 @@ static vaddr x86_cpu_get_pc(CPUState *cs) =20 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 #if !defined(CONFIG_USER_ONLY) if (interrupt_request & CPU_INTERRUPT_POLL) { @@ -7722,8 +7710,7 @@ static bool x86_cpu_has_work(CPUState *cs) =20 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 info->mach =3D (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 diff --git a/target/i386/helper.c b/target/i386/helper.c index 2070dd0dda..4c11ef70f0 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -230,8 +230,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_= cr4) hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); target_ulong pde_addr, pte_addr; uint64_t pte; int32_t a20_mask; @@ -373,8 +372,7 @@ static void emit_guest_memory_failure(MemoryFailureActi= on action, bool ar, static void do_inject_x86_mce(CPUState *cs, run_on_cpu_data data) { MCEInjectionParams *params =3D data.host_ptr; - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *cenv =3D &cpu->env; + CPUX86State *cenv =3D cpu_env(cs); uint64_t *banks =3D cenv->mce_banks + 4 * params->bank; g_autofree char *msg =3D NULL; bool need_reset =3D false; @@ -625,9 +623,7 @@ void cpu_load_efer(CPUX86State *env, uint64_t val) =20 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - MemTxAttrs attrs =3D cpu_get_mem_attrs(env); + MemTxAttrs attrs =3D cpu_get_mem_attrs(cpu_env(cs)); AddressSpace *as =3D cpu_addressspace(cs, attrs); =20 return address_space_ldub(as, addr, attrs, NULL); @@ -635,9 +631,7 @@ uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr) =20 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - MemTxAttrs attrs =3D cpu_get_mem_attrs(env); + MemTxAttrs attrs =3D cpu_get_mem_attrs(cpu_env(cs)); AddressSpace *as =3D cpu_addressspace(cs, attrs); =20 return address_space_lduw(as, addr, attrs, NULL); @@ -645,9 +639,7 @@ uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr) =20 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - MemTxAttrs attrs =3D cpu_get_mem_attrs(env); + MemTxAttrs attrs =3D cpu_get_mem_attrs(cpu_env(cs)); AddressSpace *as =3D cpu_addressspace(cs, attrs); =20 return address_space_ldl(as, addr, attrs, NULL); @@ -655,9 +647,7 @@ uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr) =20 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - MemTxAttrs attrs =3D cpu_get_mem_attrs(env); + MemTxAttrs attrs =3D cpu_get_mem_attrs(cpu_env(cs)); AddressSpace *as =3D cpu_addressspace(cs, attrs); =20 return address_space_ldq(as, addr, attrs, NULL); @@ -665,9 +655,7 @@ uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr) =20 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - MemTxAttrs attrs =3D cpu_get_mem_attrs(env); + MemTxAttrs attrs =3D cpu_get_mem_attrs(cpu_env(cs)); AddressSpace *as =3D cpu_addressspace(cs, attrs); =20 address_space_stb(as, addr, val, attrs, NULL); @@ -675,9 +663,7 @@ void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t va= l) =20 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - MemTxAttrs attrs =3D cpu_get_mem_attrs(env); + MemTxAttrs attrs =3D cpu_get_mem_attrs(cpu_env(cs)); AddressSpace *as =3D cpu_addressspace(cs, attrs); =20 address_space_stl_notdirty(as, addr, val, attrs, NULL); @@ -685,9 +671,7 @@ void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, u= int32_t val) =20 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - MemTxAttrs attrs =3D cpu_get_mem_attrs(env); + MemTxAttrs attrs =3D cpu_get_mem_attrs(cpu_env(cs)); AddressSpace *as =3D cpu_addressspace(cs, attrs); =20 address_space_stw(as, addr, val, attrs, NULL); @@ -695,9 +679,7 @@ void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t v= al) =20 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - MemTxAttrs attrs =3D cpu_get_mem_attrs(env); + MemTxAttrs attrs =3D cpu_get_mem_attrs(cpu_env(cs)); AddressSpace *as =3D cpu_addressspace(cs, attrs); =20 address_space_stl(as, addr, val, attrs, NULL); @@ -705,9 +687,7 @@ void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t v= al) =20 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - MemTxAttrs attrs =3D cpu_get_mem_attrs(env); + MemTxAttrs attrs =3D cpu_get_mem_attrs(cpu_env(cs)); AddressSpace *as =3D cpu_addressspace(cs, attrs); =20 address_space_stq(as, addr, val, attrs, NULL); diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 11ffdd4c69..772578e3f4 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -159,10 +159,7 @@ static bool ept_emulation_fault(hvf_slot *slot, uint64= _t gpa, uint64_t ept_qual) =20 void hvf_arch_vcpu_destroy(CPUState *cpu) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; - - g_free(env->hvf_mmio_buf); + g_free(cpu_env(cpu)->hvf_mmio_buf); } =20 static void init_tsc_freq(CPUX86State *env) @@ -313,8 +310,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) =20 static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idt= vec_info) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; + CPUX86State *env =3D cpu_env(cpu); =20 env->exception_nr =3D -1; env->exception_pending =3D 0; diff --git a/target/i386/hvf/x86.c b/target/i386/hvf/x86.c index 80e36136d0..932635232b 100644 --- a/target/i386/hvf/x86.c +++ b/target/i386/hvf/x86.c @@ -128,9 +128,7 @@ bool x86_is_real(CPUState *cpu) =20 bool x86_is_v8086(CPUState *cpu) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; - return x86_is_protected(cpu) && (env->eflags & VM_MASK); + return x86_is_protected(cpu) && (cpu_env(cpu)->eflags & VM_MASK); } =20 bool x86_is_long_mode(CPUState *cpu) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 3a3f0a50d0..0d13b32f91 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -1419,8 +1419,7 @@ static void init_cmd_handler() =20 void load_regs(CPUState *cs) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 int i =3D 0; RRX(env, R_EAX) =3D rreg(cs->accel->fd, HV_X86_RAX); @@ -1442,8 +1441,7 @@ void load_regs(CPUState *cs) =20 void store_regs(CPUState *cs) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 int i =3D 0; wreg(cs->accel->fd, HV_X86_RAX, RAX(env)); diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c index f09bfbdda5..c173e9d883 100644 --- a/target/i386/hvf/x86_task.c +++ b/target/i386/hvf/x86_task.c @@ -33,8 +33,7 @@ // TODO: taskswitch handling static void save_state_to_tss32(CPUState *cpu, struct x86_tss_segment32 *t= ss) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; + CPUX86State *env =3D cpu_env(cpu); =20 /* CR3 and ldt selector are not saved intentionally */ tss->eip =3D (uint32_t)env->eip; @@ -58,8 +57,7 @@ static void save_state_to_tss32(CPUState *cpu, struct x86= _tss_segment32 *tss) =20 static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 = *tss) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; + CPUX86State *env =3D cpu_env(cpu); =20 wvmcs(cpu->accel->fd, VMCS_GUEST_CR3, tss->cr3); =20 @@ -128,9 +126,7 @@ void vmx_handle_task_switch(CPUState *cpu, x68_segment_= selector tss_sel, int rea uint32_t desc_limit; struct x86_call_gate task_gate_desc; struct vmx_segment vmx_seg; - - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; + CPUX86State *env =3D cpu_env(cpu); =20 x86_read_segment_descriptor(cpu, &next_tss_desc, tss_sel); x86_read_segment_descriptor(cpu, &curr_tss_desc, old_tss_sel); diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index be2c46246e..10f79849b3 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -238,8 +238,7 @@ void hvf_get_msrs(CPUState *cs) =20 int hvf_put_registers(CPUState *cs) { - X86CPU *x86cpu =3D X86_CPU(cs); - CPUX86State *env =3D &x86cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 wreg(cs->accel->fd, HV_X86_RAX, env->regs[R_EAX]); wreg(cs->accel->fd, HV_X86_RBX, env->regs[R_EBX]); @@ -282,8 +281,7 @@ int hvf_put_registers(CPUState *cs) =20 int hvf_get_registers(CPUState *cs) { - X86CPU *x86cpu =3D X86_CPU(cs); - CPUX86State *env =3D &x86cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 env->regs[R_EAX] =3D rreg(cs->accel->fd, HV_X86_RAX); env->regs[R_EBX] =3D rreg(cs->accel->fd, HV_X86_RBX); @@ -342,8 +340,7 @@ void vmx_clear_int_window_exiting(CPUState *cs) =20 bool hvf_inject_interrupts(CPUState *cs) { - X86CPU *x86cpu =3D X86_CPU(cs); - CPUX86State *env =3D &x86cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 uint8_t vector; uint64_t intr_type; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 76a66246eb..e4f1c62888 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -754,8 +754,7 @@ static inline bool freq_within_bounds(int freq, int tar= get_freq) =20 static int kvm_arch_set_tsc_khz(CPUState *cs) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); int r, cur_freq; bool set_ioctl =3D false; =20 @@ -5369,8 +5368,7 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run= *run) =20 bool kvm_arch_stop_on_emulation_error(CPUState *cs) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 kvm_cpu_synchronize_state(cs); return !(env->cr[0] & CR0_PE_MASK) || diff --git a/target/i386/kvm/xen-emu.c b/target/i386/kvm/xen-emu.c index fc2c2321ac..10350a22d1 100644 --- a/target/i386/kvm/xen-emu.c +++ b/target/i386/kvm/xen-emu.c @@ -313,10 +313,7 @@ static int kvm_xen_set_vcpu_callback_vector(CPUState *= cs) =20 static void do_set_vcpu_callback_vector(CPUState *cs, run_on_cpu_data data) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - - env->xen_vcpu_callback_vector =3D data.host_int; + cpu_env(cs)->xen_vcpu_callback_vector =3D data.host_int; =20 if (kvm_xen_has_cap(EVTCHN_SEND)) { kvm_xen_set_vcpu_callback_vector(cs); @@ -325,8 +322,7 @@ static void do_set_vcpu_callback_vector(CPUState *cs, r= un_on_cpu_data data) =20 static int set_vcpu_info(CPUState *cs, uint64_t gpa) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); MemoryRegionSection mrs =3D { .mr =3D NULL }; void *vcpu_info_hva =3D NULL; int ret; @@ -362,8 +358,7 @@ static int set_vcpu_info(CPUState *cs, uint64_t gpa) =20 static void do_set_vcpu_info_default_gpa(CPUState *cs, run_on_cpu_data dat= a) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 env->xen_vcpu_info_default_gpa =3D data.host_ulong; =20 @@ -375,8 +370,7 @@ static void do_set_vcpu_info_default_gpa(CPUState *cs, = run_on_cpu_data data) =20 static void do_set_vcpu_info_gpa(CPUState *cs, run_on_cpu_data data) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 env->xen_vcpu_info_gpa =3D data.host_ulong; =20 @@ -479,8 +473,7 @@ void kvm_xen_inject_vcpu_callback_vector(uint32_t vcpu_= id, int type) /* Must always be called with xen_timers_lock held */ static int kvm_xen_set_vcpu_timer(CPUState *cs) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 struct kvm_xen_vcpu_attr va =3D { .type =3D KVM_XEN_VCPU_ATTR_TYPE_TIMER, @@ -527,8 +520,7 @@ int kvm_xen_set_vcpu_virq(uint32_t vcpu_id, uint16_t vi= rq, uint16_t port) =20 static void do_set_vcpu_time_info_gpa(CPUState *cs, run_on_cpu_data data) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 env->xen_vcpu_time_info_gpa =3D data.host_ulong; =20 @@ -538,8 +530,7 @@ static void do_set_vcpu_time_info_gpa(CPUState *cs, run= _on_cpu_data data) =20 static void do_set_vcpu_runstate_gpa(CPUState *cs, run_on_cpu_data data) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 env->xen_vcpu_runstate_gpa =3D data.host_ulong; =20 @@ -549,8 +540,7 @@ static void do_set_vcpu_runstate_gpa(CPUState *cs, run_= on_cpu_data data) =20 static void do_vcpu_soft_reset(CPUState *cs, run_on_cpu_data data) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 env->xen_vcpu_info_gpa =3D INVALID_GPA; env->xen_vcpu_info_default_gpa =3D INVALID_GPA; @@ -1813,8 +1803,7 @@ uint16_t kvm_xen_get_evtchn_max_pirq(void) =20 int kvm_put_xen_state(CPUState *cs) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); uint64_t gpa; int ret; =20 @@ -1887,8 +1876,7 @@ int kvm_put_xen_state(CPUState *cs) =20 int kvm_get_xen_state(CPUState *cs) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); uint64_t gpa; int ret; =20 diff --git a/target/i386/tcg/sysemu/bpt_helper.c b/target/i386/tcg/sysemu/b= pt_helper.c index 4d96a48a3c..90d6117497 100644 --- a/target/i386/tcg/sysemu/bpt_helper.c +++ b/target/i386/tcg/sysemu/bpt_helper.c @@ -208,8 +208,7 @@ bool check_hw_breakpoints(CPUX86State *env, bool force_= dr6_update) =20 void breakpoint_handler(CPUState *cs) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 5b86f439ad..1afa177551 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -639,6 +639,5 @@ G_NORETURN void x86_cpu_do_unaligned_access(CPUState *c= s, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - X86CPU *cpu =3D X86_CPU(cs); - handle_unaligned_access(&cpu->env, vaddr, access_type, retaddr); + handle_unaligned_access(cpu_env(cs), vaddr, access_type, retaddr); } diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index e1405b7be9..8f8fd6529d 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -29,8 +29,7 @@ =20 static void x86_cpu_exec_enter(CPUState *cs) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 CC_SRC =3D env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); env->df =3D 1 - (2 * ((env->eflags >> 10) & 1)); @@ -40,8 +39,7 @@ static void x86_cpu_exec_enter(CPUState *cs) =20 static void x86_cpu_exec_exit(CPUState *cs) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 env->eflags =3D cpu_compute_eflags(env); } @@ -65,8 +63,7 @@ static void x86_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); int cc_op =3D data[1]; uint64_t new_pc; =20 @@ -96,11 +93,8 @@ static void x86_restore_state_to_opc(CPUState *cs, #ifndef CONFIG_USER_ONLY static bool x86_debug_check_breakpoint(CPUState *cs) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - /* RF disables all architectural breakpoints. */ - return !(env->eflags & RF_MASK); + return !(cpu_env(cs)->eflags & RF_MASK); } #endif =20 diff --git a/target/i386/tcg/user/excp_helper.c b/target/i386/tcg/user/excp= _helper.c index b3bdb7831a..9ea5566149 100644 --- a/target/i386/tcg/user/excp_helper.c +++ b/target/i386/tcg/user/excp_helper.c @@ -26,8 +26,7 @@ void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t ra) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 /* * The error_code that hw reports as part of the exception frame @@ -52,6 +51,5 @@ void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, void x86_cpu_record_sigbus(CPUState *cs, vaddr addr, MMUAccessType access_type, uintptr_t ra) { - X86CPU *cpu =3D X86_CPU(cs); - handle_unaligned_access(&cpu->env, addr, access_type, ra); + handle_unaligned_access(cpu_env(cs), addr, access_type, ra); } diff --git a/target/i386/tcg/user/seg_helper.c b/target/i386/tcg/user/seg_h= elper.c index c45f2ac2ba..2f89dbb51e 100644 --- a/target/i386/tcg/user/seg_helper.c +++ b/target/i386/tcg/user/seg_helper.c @@ -78,8 +78,7 @@ static void do_interrupt_user(CPUX86State *env, int intno= , int is_int, =20 void x86_cpu_do_interrupt(CPUState *cs) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cpu_env(cs); =20 /* if user mode only, we simulate a fake exception which will be handled outside the cpu execution --=20 2.41.0 From nobody Tue Nov 26 14:27:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 29 Jan 2024 08:46:52 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Song Gao Subject: [PATCH v3 15/29] target/loongarch: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:44:57 +0100 Message-ID: <20240129164514.73104-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706546971047100001 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/loongarch/cpu.c | 39 ++++++++--------------------- target/loongarch/gdbstub.c | 6 ++--- target/loongarch/kvm/kvm.c | 41 +++++++++---------------------- target/loongarch/tcg/tlb_helper.c | 6 ++--- 4 files changed, 26 insertions(+), 66 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 3094bbc0d9..d1c907b2a7 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -91,18 +91,12 @@ void G_NORETURN do_raise_exception(CPULoongArchState *e= nv, =20 static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; - - set_pc(env, value); + set_pc(cpu_env(cs), value); } =20 static vaddr loongarch_cpu_get_pc(CPUState *cs) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; - - return env->pc; + return cpu_env(cs)->pc; } =20 #ifndef CONFIG_USER_ONLY @@ -157,8 +151,7 @@ static inline bool cpu_loongarch_hw_interrupts_pending(= CPULoongArchState *env) #ifndef CONFIG_USER_ONLY static void loongarch_cpu_do_interrupt(CPUState *cs) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); bool update_badinstr =3D 1; int cause =3D -1; const char *name; @@ -308,8 +301,7 @@ static void loongarch_cpu_do_transaction_failed(CPUStat= e *cs, hwaddr physaddr, MemTxResult response, uintptr_t retaddr) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); =20 if (access_type =3D=3D MMU_INST_FETCH) { do_raise_exception(env, EXCCODE_ADEF, retaddr); @@ -321,8 +313,7 @@ static void loongarch_cpu_do_transaction_failed(CPUStat= e *cs, hwaddr physaddr, static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_reque= st) { if (interrupt_request & CPU_INTERRUPT_HARD) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); =20 if (cpu_loongarch_hw_interrupts_enabled(env) && cpu_loongarch_hw_interrupts_pending(env)) { @@ -339,21 +330,15 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs= , int interrupt_request) static void loongarch_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - set_pc(env, tb->pc); + set_pc(cpu_env(cs), tb->pc); } =20 static void loongarch_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; - - set_pc(env, data[0]); + set_pc(cpu_env(cs), data[0]); } #endif /* CONFIG_TCG */ =20 @@ -362,12 +347,10 @@ static bool loongarch_cpu_has_work(CPUState *cs) #ifdef CONFIG_USER_ONLY return true; #else - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; bool has_work =3D false; =20 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && - cpu_loongarch_hw_interrupts_pending(env)) { + cpu_loongarch_hw_interrupts_pending(cpu_env(cs))) { has_work =3D true; } =20 @@ -499,9 +482,8 @@ static void loongarch_max_initfn(Object *obj) static void loongarch_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); LoongArchCPUClass *lacc =3D LOONGARCH_CPU_GET_CLASS(obj); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); =20 if (lacc->parent_phases.hold) { lacc->parent_phases.hold(obj); @@ -684,8 +666,7 @@ static ObjectClass *loongarch_cpu_class_by_name(const c= har *cpu_model) =20 void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); int i; =20 qemu_fprintf(f, " PC=3D%016" PRIx64 " ", env->pc); diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c index 5fc2f19e96..91a16183b0 100644 --- a/target/loongarch/gdbstub.c +++ b/target/loongarch/gdbstub.c @@ -33,8 +33,7 @@ void write_fcc(CPULoongArchState *env, uint64_t val) =20 int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int= n) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); uint64_t val; =20 if (0 <=3D n && n < 32) { @@ -60,8 +59,7 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteAr= ray *mem_buf, int n) =20 int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); target_ulong tmp; int read_length; int length =3D 0; diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index c19978a970..df5e199860 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -38,8 +38,7 @@ static int kvm_loongarch_get_regs_core(CPUState *cs) int ret =3D 0; int i; struct kvm_regs regs; - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); =20 /* Get the current register set as KVM seems it */ ret =3D kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); @@ -62,8 +61,7 @@ static int kvm_loongarch_put_regs_core(CPUState *cs) int ret =3D 0; int i; struct kvm_regs regs; - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); =20 /* Set the registers based on QEMU's view of things */ for (i =3D 0; i < 32; i++) { @@ -82,8 +80,7 @@ static int kvm_loongarch_put_regs_core(CPUState *cs) static int kvm_loongarch_get_csr(CPUState *cs) { int ret =3D 0; - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CRMD), &env->CSR_CRMD); @@ -253,8 +250,7 @@ static int kvm_loongarch_get_csr(CPUState *cs) static int kvm_loongarch_put_csr(CPUState *cs, int level) { int ret =3D 0; - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CRMD), &env->CSR_CRMD); @@ -430,9 +426,7 @@ static int kvm_loongarch_get_regs_fp(CPUState *cs) { int ret, i; struct kvm_fpu fpu; - - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); =20 ret =3D kvm_vcpu_ioctl(cs, KVM_GET_FPU, &fpu); if (ret < 0) { @@ -456,9 +450,7 @@ static int kvm_loongarch_put_regs_fp(CPUState *cs) { int ret, i; struct kvm_fpu fpu; - - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); =20 fpu.fcsr =3D env->fcsr0; fpu.fcc =3D 0; @@ -487,8 +479,7 @@ static int kvm_loongarch_get_mpstate(CPUState *cs) { int ret =3D 0; struct kvm_mp_state mp_state; - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); =20 if (cap_has_mp_state) { ret =3D kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state); @@ -505,12 +496,8 @@ static int kvm_loongarch_get_mpstate(CPUState *cs) static int kvm_loongarch_put_mpstate(CPUState *cs) { int ret =3D 0; - - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; - struct kvm_mp_state mp_state =3D { - .mp_state =3D env->mp_state + .mp_state =3D cpu_env(cs)->mp_state }; =20 if (cap_has_mp_state) { @@ -527,8 +514,7 @@ static int kvm_loongarch_get_cpucfg(CPUState *cs) { int i, ret =3D 0; uint64_t val; - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); =20 for (i =3D 0; i < 21; i++) { ret =3D kvm_get_one_reg(cs, KVM_IOC_CPUCFG(i), &val); @@ -549,8 +535,7 @@ static int kvm_check_cpucfg2(CPUState *cs) .attr =3D 2, .addr =3D (uint64_t)&val, }; - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); =20 ret =3D kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr); =20 @@ -575,8 +560,7 @@ static int kvm_check_cpucfg2(CPUState *cs) static int kvm_loongarch_put_cpucfg(CPUState *cs) { int i, ret =3D 0; - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); uint64_t val; =20 for (i =3D 0; i < 21; i++) { @@ -758,8 +742,7 @@ bool kvm_arch_cpu_check_are_resettable(void) int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) { int ret =3D 0; - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); MemTxAttrs attrs =3D {}; =20 attrs.requester_id =3D env_cpu(env)->cpu_index; diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 449043c68b..2df0bced4c 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -235,8 +235,7 @@ static int get_physical_address(CPULoongArchState *env,= hwaddr *physical, =20 hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); - CPULoongArchState *env =3D &cpu->env; + CPULoongArchState *env =3D cpu_env(cs); hwaddr phys_addr; int prot; =20 @@ -679,8 +678,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address= , int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); 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Mon, 29 Jan 2024 08:46:58 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Laurent Vivier Subject: [PATCH v3 16/29] target/m68k: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:44:58 +0100 Message-ID: <20240129164514.73104-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706546921218100002 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/m68k/cpu.c | 33 +++++++++++---------------------- target/m68k/gdbstub.c | 6 ++---- target/m68k/helper.c | 6 ++---- target/m68k/m68k-semi.c | 6 ++---- target/m68k/op_helper.c | 11 +++-------- target/m68k/translate.c | 3 +-- 6 files changed, 21 insertions(+), 44 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 4d14d04c33..4be0f0f33a 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -69,9 +69,8 @@ static void m68k_unset_feature(CPUM68KState *env, int fea= ture) static void m68k_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); - M68kCPU *cpu =3D M68K_CPU(cs); M68kCPUClass *mcc =3D M68K_CPU_GET_CLASS(obj); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(cs); floatx80 nan =3D floatx80_default_nan(NULL); int i; =20 @@ -117,8 +116,7 @@ static ObjectClass *m68k_cpu_class_by_name(const char *= cpu_model) =20 static void m5206_cpu_initfn(Object *obj) { - M68kCPU *cpu =3D M68K_CPU(obj); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(CPU(obj)); =20 m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); m68k_set_feature(env, M68K_FEATURE_MOVEFROMSR_PRIV); @@ -127,8 +125,7 @@ static void m5206_cpu_initfn(Object *obj) /* Base feature set, including isns. for m68k family */ static void m68000_cpu_initfn(Object *obj) { - M68kCPU *cpu =3D M68K_CPU(obj); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(CPU(obj)); =20 m68k_set_feature(env, M68K_FEATURE_M68K); m68k_set_feature(env, M68K_FEATURE_USP); @@ -141,8 +138,7 @@ static void m68000_cpu_initfn(Object *obj) */ static void m68010_cpu_initfn(Object *obj) { - M68kCPU *cpu =3D M68K_CPU(obj); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(CPU(obj)); =20 m68000_cpu_initfn(obj); m68k_set_feature(env, M68K_FEATURE_M68010); @@ -161,8 +157,7 @@ static void m68010_cpu_initfn(Object *obj) */ static void m68020_cpu_initfn(Object *obj) { - M68kCPU *cpu =3D M68K_CPU(obj); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(CPU(obj)); =20 m68010_cpu_initfn(obj); m68k_unset_feature(env, M68K_FEATURE_M68010); @@ -192,8 +187,7 @@ static void m68020_cpu_initfn(Object *obj) */ static void m68030_cpu_initfn(Object *obj) { - M68kCPU *cpu =3D M68K_CPU(obj); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(CPU(obj)); =20 m68020_cpu_initfn(obj); m68k_unset_feature(env, M68K_FEATURE_M68020); @@ -219,8 +213,7 @@ static void m68030_cpu_initfn(Object *obj) */ static void m68040_cpu_initfn(Object *obj) { - M68kCPU *cpu =3D M68K_CPU(obj); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(CPU(obj)); =20 m68030_cpu_initfn(obj); m68k_unset_feature(env, M68K_FEATURE_M68030); @@ -240,8 +233,7 @@ static void m68040_cpu_initfn(Object *obj) */ static void m68060_cpu_initfn(Object *obj) { - M68kCPU *cpu =3D M68K_CPU(obj); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(CPU(obj)); =20 m68040_cpu_initfn(obj); m68k_unset_feature(env, M68K_FEATURE_M68040); @@ -254,8 +246,7 @@ static void m68060_cpu_initfn(Object *obj) =20 static void m5208_cpu_initfn(Object *obj) { - M68kCPU *cpu =3D M68K_CPU(obj); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(CPU(obj)); =20 m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC); @@ -267,8 +258,7 @@ static void m5208_cpu_initfn(Object *obj) =20 static void cfv4e_cpu_initfn(Object *obj) { - M68kCPU *cpu =3D M68K_CPU(obj); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(CPU(obj)); =20 m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); m68k_set_feature(env, M68K_FEATURE_CF_ISA_B); @@ -281,8 +271,7 @@ static void cfv4e_cpu_initfn(Object *obj) =20 static void any_cpu_initfn(Object *obj) { - M68kCPU *cpu =3D M68K_CPU(obj); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(CPU(obj)); =20 m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); m68k_set_feature(env, M68K_FEATURE_CF_ISA_B); diff --git a/target/m68k/gdbstub.c b/target/m68k/gdbstub.c index 1e5f033a12..15547e2313 100644 --- a/target/m68k/gdbstub.c +++ b/target/m68k/gdbstub.c @@ -23,8 +23,7 @@ =20 int m68k_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - M68kCPU *cpu =3D M68K_CPU(cs); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(cs); =20 if (n < 8) { /* D0-D7 */ @@ -50,8 +49,7 @@ int m68k_cpu_gdb_read_register(CPUState *cs, GByteArray *= mem_buf, int n) =20 int m68k_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - M68kCPU *cpu =3D M68K_CPU(cs); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(cs); uint32_t tmp; =20 tmp =3D ldl_p(mem_buf); diff --git a/target/m68k/helper.c b/target/m68k/helper.c index a812f328a1..3ec835293a 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -894,8 +894,7 @@ txfail: =20 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - M68kCPU *cpu =3D M68K_CPU(cs); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(cs); hwaddr phys_addr; int prot; int access_type; @@ -943,8 +942,7 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, MMUAccessType qemu_access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - M68kCPU *cpu =3D M68K_CPU(cs); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(cs); hwaddr physical; int prot; int access_type; diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c index b4ffb70f8b..546cff2246 100644 --- a/target/m68k/m68k-semi.c +++ b/target/m68k/m68k-semi.c @@ -77,8 +77,7 @@ static int host_to_gdb_errno(int err) =20 static void m68k_semi_u32_cb(CPUState *cs, uint64_t ret, int err) { - M68kCPU *cpu =3D M68K_CPU(cs); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(cs); =20 target_ulong args =3D env->dregs[1]; if (put_user_u32(ret, args) || @@ -95,8 +94,7 @@ static void m68k_semi_u32_cb(CPUState *cs, uint64_t ret, = int err) =20 static void m68k_semi_u64_cb(CPUState *cs, uint64_t ret, int err) { - M68kCPU *cpu =3D M68K_CPU(cs); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(cs); =20 target_ulong args =3D env->dregs[1]; if (put_user_u32(ret >> 32, args) || diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 1ce850bbc5..851cca640d 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -441,10 +441,7 @@ static void do_interrupt_all(CPUM68KState *env, int is= _hw) =20 void m68k_cpu_do_interrupt(CPUState *cs) { - M68kCPU *cpu =3D M68K_CPU(cs); - CPUM68KState *env =3D &cpu->env; - - do_interrupt_all(env, 0); + do_interrupt_all(cpu_env(cs), 0); } =20 static inline void do_interrupt_m68k_hardirq(CPUM68KState *env) @@ -457,8 +454,7 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr p= hysaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr) { - M68kCPU *cpu =3D M68K_CPU(cs); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(cs); =20 cpu_restore_state(cs, retaddr); =20 @@ -511,8 +507,7 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr p= hysaddr, vaddr addr, =20 bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - M68kCPU *cpu =3D M68K_CPU(cs); - CPUM68KState *env =3D &cpu->env; + CPUM68KState *env =3D cpu_env(cs); =20 if (interrupt_request & CPU_INTERRUPT_HARD && ((env->sr & SR_I) >> SR_I_SHIFT) < env->pending_level) { diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 4a0b0b2703..9688476a7b 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6108,8 +6108,7 @@ static double floatx80_to_double(CPUM68KState *env, u= int16_t high, uint64_t low) =20 void m68k_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - M68kCPU *cpu =3D M68K_CPU(cs); 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Mon, 29 Jan 2024 08:47:03 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Edgar E. Iglesias" Subject: [PATCH v3 17/29] target/microblaze: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:44:59 +0100 Message-ID: <20240129164514.73104-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22f; envelope-from=philmd@linaro.org; helo=mail-lj1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706546949313100001 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/microblaze/gdbstub.c | 3 +-- target/microblaze/helper.c | 3 +-- target/microblaze/translate.c | 6 ++---- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 29ac6e9c0f..98660ed950 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -113,9 +113,8 @@ int mb_cpu_gdb_read_stack_protect(CPUMBState *env, GByt= eArray *mem_buf, int n) =20 int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); CPUClass *cc =3D CPU_GET_CLASS(cs); - CPUMBState *env =3D &cpu->env; + CPUMBState *env =3D cpu_env(cs); uint32_t tmp; =20 if (n > cc->gdb_num_core_regs) { diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 98bdb82de8..bf955dd425 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -253,8 +253,7 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, v= addr addr, =20 bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); - CPUMBState *env =3D &cpu->env; + CPUMBState *env =3D cpu_env(cs); =20 if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->msr & MSR_IE) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 49bfb4a0ea..354897c4a2 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1630,7 +1630,6 @@ static void mb_tr_insn_start(DisasContextBase *dcb, C= PUState *cs) static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc =3D container_of(dcb, DisasContext, base); - CPUMBState *env =3D cpu_env(cs); uint32_t ir; =20 /* TODO: This should raise an exception, not terminate qemu. */ @@ -1641,7 +1640,7 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) =20 dc->tb_flags_to_set =3D 0; =20 - ir =3D cpu_ldl_code(env, dc->base.pc_next); + ir =3D cpu_ldl_code(cpu_env(cs), dc->base.pc_next); if (!decode(dc, ir)) { trap_illegal(dc, true); } @@ -1800,8 +1799,7 @@ void gen_intermediate_code(CPUState *cpu, Translation= Block *tb, int *max_insns, =20 void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); 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Mon, 29 Jan 2024 08:47:10 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v3 18/29] target/mips: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:45:00 +0100 Message-ID: <20240129164514.73104-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/cpu.c | 15 ++++---------- target/mips/gdbstub.c | 6 ++---- target/mips/kvm.c | 27 +++++++++---------------- target/mips/sysemu/physaddr.c | 3 +-- target/mips/tcg/exception.c | 3 +-- target/mips/tcg/op_helper.c | 8 +++----- target/mips/tcg/sysemu/special_helper.c | 3 +-- target/mips/tcg/sysemu/tlb_helper.c | 6 ++---- target/mips/tcg/translate.c | 3 +-- 9 files changed, 24 insertions(+), 50 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 6ced52f985..1bea76e40a 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -80,8 +80,7 @@ static void fpu_dump_state(CPUMIPSState *env, FILE *f, in= t flags) =20 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); int i; =20 qemu_fprintf(f, "pc=3D0x" TARGET_FMT_lx " HI=3D0x" TARGET_FMT_lx @@ -123,9 +122,7 @@ void cpu_set_exception_base(int vp_index, target_ulong = address) =20 static void mips_cpu_set_pc(CPUState *cs, vaddr value) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - - mips_env_set_pc(&cpu->env, value); + mips_env_set_pc(cpu_env(cs), value); } =20 static vaddr mips_cpu_get_pc(CPUState *cs) @@ -137,8 +134,7 @@ static vaddr mips_cpu_get_pc(CPUState *cs) =20 static bool mips_cpu_has_work(CPUState *cs) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); bool has_work =3D false; =20 /* @@ -428,10 +424,7 @@ static void mips_cpu_reset_hold(Object *obj) =20 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) { - MIPSCPU *cpu =3D MIPS_CPU(s); - CPUMIPSState *env =3D &cpu->env; - - if (!(env->insn_flags & ISA_NANOMIPS32)) { + if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) { #if TARGET_BIG_ENDIAN info->print_insn =3D print_insn_big_mips; #else diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index 62d7b72407..169d47416a 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -25,8 +25,7 @@ =20 int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); =20 if (n < 32) { return gdb_get_regl(mem_buf, env->active_tc.gpr[n]); @@ -78,8 +77,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *= mem_buf, int n) =20 int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); target_ulong tmp; =20 tmp =3D ldtul_p(mem_buf); diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 15d0cf9adb..6c52e59f55 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -63,8 +63,7 @@ int kvm_arch_irqchip_create(KVMState *s) =20 int kvm_arch_init_vcpu(CPUState *cs) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); int ret =3D 0; =20 qemu_add_vm_change_state_handler(kvm_mips_update_state, cs); @@ -460,8 +459,7 @@ static inline int kvm_mips_change_one_reg(CPUState *cs,= uint64_t reg_id, */ static int kvm_mips_save_count(CPUState *cs) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); uint64_t count_ctl; int err, ret =3D 0; =20 @@ -502,8 +500,7 @@ static int kvm_mips_save_count(CPUState *cs) */ static int kvm_mips_restore_count(CPUState *cs) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); uint64_t count_ctl; int err_dc, err, ret =3D 0; =20 @@ -590,8 +587,7 @@ static void kvm_mips_update_state(void *opaque, bool ru= nning, RunState state) =20 static int kvm_mips_put_fpu_registers(CPUState *cs, int level) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); int err, ret =3D 0; unsigned int i; =20 @@ -670,8 +666,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int= level) =20 static int kvm_mips_get_fpu_registers(CPUState *cs) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); int err, ret =3D 0; unsigned int i; =20 @@ -751,8 +746,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs) =20 static int kvm_mips_put_cp0_registers(CPUState *cs, int level) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); int err, ret =3D 0; =20 (void)level; @@ -974,8 +968,7 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int= level) =20 static int kvm_mips_get_cp0_registers(CPUState *cs) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); int err, ret =3D 0; =20 err =3D kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Ind= ex); @@ -1181,8 +1174,7 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) =20 int kvm_arch_put_registers(CPUState *cs, int level) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); struct kvm_regs regs; int ret; int i; @@ -1217,8 +1209,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) =20 int kvm_arch_get_registers(CPUState *cs) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); int ret =3D 0; struct kvm_regs regs; int i; diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c index 05990aa5bb..56380dfe6c 100644 --- a/target/mips/sysemu/physaddr.c +++ b/target/mips/sysemu/physaddr.c @@ -230,8 +230,7 @@ int get_physical_address(CPUMIPSState *env, hwaddr *phy= sical, =20 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); hwaddr phys_addr; int prot; =20 diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index da49a93912..13275d1ded 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -79,8 +79,7 @@ void helper_wait(CPUMIPSState *env) =20 void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); =20 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); env->active_tc.PC =3D tb->pc; diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index 98935b5e64..65403f1a87 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -279,8 +279,7 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); int error_code =3D 0; int excp; =20 @@ -306,9 +305,8 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwadd= r physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retadd= r) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(cpu); - CPUMIPSState *env =3D &cpu->env; + MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(cs); + CPUMIPSState *env =3D cpu_env(cs); =20 if (access_type =3D=3D MMU_INST_FETCH) { do_raise_exception(env, EXCP_IBE, retaddr); diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/syse= mu/special_helper.c index 93276f789d..7934f2ea41 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -90,8 +90,7 @@ static void debug_post_eret(CPUMIPSState *env) =20 bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock = *tb) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); =20 if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 && !(cs->tcg_cflags & CF_PCREL) && env->active_tc.PC !=3D tb->pc) { diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index 4ede904800..6c48c4fa80 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -910,8 +910,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); hwaddr physical; int prot; int ret =3D TLBRET_BADADDR; @@ -1346,8 +1345,7 @@ void mips_cpu_do_interrupt(CPUState *cs) bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; + CPUMIPSState *env =3D cpu_env(cs); =20 if (cpu_mips_hw_interrupts_enabled(env) && cpu_mips_hw_interrupts_pending(env)) { diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 13e43fa3b6..e74b98de1c 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15628,8 +15628,7 @@ void mips_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - MIPSCPU *cpu =3D MIPS_CPU(cs); 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Mon, 29 Jan 2024 08:47:16 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Chris Wulff , Marek Vasut Subject: [PATCH v3 19/29] target/nios2: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:45:01 +0100 Message-ID: <20240129164514.73104-20-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706547400277100003 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/nios2/cpu.c | 15 +++------------ target/nios2/helper.c | 3 +-- target/nios2/nios2-semi.c | 6 ++---- target/nios2/translate.c | 3 +-- 4 files changed, 7 insertions(+), 20 deletions(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 09b122e24d..b5b3773fb8 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -28,28 +28,19 @@ =20 static void nios2_cpu_set_pc(CPUState *cs, vaddr value) { - Nios2CPU *cpu =3D NIOS2_CPU(cs); - CPUNios2State *env =3D &cpu->env; - - env->pc =3D value; + cpu_env(cs)->pc =3D value; } =20 static vaddr nios2_cpu_get_pc(CPUState *cs) { - Nios2CPU *cpu =3D NIOS2_CPU(cs); - CPUNios2State *env =3D &cpu->env; - - return env->pc; + return cpu_env(cs)->pc; } =20 static void nios2_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - Nios2CPU *cpu =3D NIOS2_CPU(cs); - CPUNios2State *env =3D &cpu->env; - - env->pc =3D data[0]; + cpu_env(cs)->pc =3D data[0]; } =20 static bool nios2_cpu_has_work(CPUState *cs) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index bb3b09e5a7..ac57121afc 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -287,8 +287,7 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - Nios2CPU *cpu =3D NIOS2_CPU(cs); - CPUNios2State *env =3D &cpu->env; + CPUNios2State *env =3D cpu_env(cs); =20 env->ctrl[CR_BADADDR] =3D addr; cs->exception_index =3D EXCP_UNALIGN; diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c index 0b84fcb6b6..420702e293 100644 --- a/target/nios2/nios2-semi.c +++ b/target/nios2/nios2-semi.c @@ -75,8 +75,7 @@ static int host_to_gdb_errno(int err) =20 static void nios2_semi_u32_cb(CPUState *cs, uint64_t ret, int err) { - Nios2CPU *cpu =3D NIOS2_CPU(cs); - CPUNios2State *env =3D &cpu->env; + CPUNios2State *env =3D cpu_env(cs); target_ulong args =3D env->regs[R_ARG1]; =20 if (put_user_u32(ret, args) || @@ -93,8 +92,7 @@ static void nios2_semi_u32_cb(CPUState *cs, uint64_t ret,= int err) =20 static void nios2_semi_u64_cb(CPUState *cs, uint64_t ret, int err) { - Nios2CPU *cpu =3D NIOS2_CPU(cs); - CPUNios2State *env =3D &cpu->env; + CPUNios2State *env =3D cpu_env(cs); target_ulong args =3D env->regs[R_ARG1]; =20 if (put_user_u32(ret >> 32, args) || diff --git a/target/nios2/translate.c b/target/nios2/translate.c index e806623594..30beb303f9 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -970,7 +970,6 @@ static void nios2_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cs) static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUNios2State *env =3D cpu_env(cs); const Nios2Instruction *instr; uint32_t code, pc; uint8_t op; @@ -980,7 +979,7 @@ static void nios2_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cs) dc->base.pc_next =3D pc + 4; =20 /* Decode an instruction */ - code =3D cpu_ldl_code(env, pc); + code =3D cpu_ldl_code(cpu_env(cs), pc); op =3D get_opcode(code); =20 if (unlikely(op >=3D ARRAY_SIZE(i_type_instructions))) { --=20 2.41.0 From nobody Tue Nov 26 14:27:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 29 Jan 2024 08:47:21 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Stafford Horne Subject: [PATCH v3 20/29] target/openrisc: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:45:02 +0100 Message-ID: <20240129164514.73104-21-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; 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Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/openrisc/gdbstub.c | 6 ++---- target/openrisc/interrupt.c | 6 ++---- target/openrisc/translate.c | 6 ++---- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index d1074a0581..c2a77d5d4d 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -23,8 +23,7 @@ =20 int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int = n) { - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - CPUOpenRISCState *env =3D &cpu->env; + CPUOpenRISCState *env =3D cpu_env(cs); =20 if (n < 32) { return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n)); @@ -48,9 +47,8 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArr= ay *mem_buf, int n) =20 int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); CPUClass *cc =3D CPU_GET_CLASS(cs); - CPUOpenRISCState *env =3D &cpu->env; + CPUOpenRISCState *env =3D cpu_env(cs); uint32_t tmp; =20 if (n > cc->gdb_num_core_regs) { diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index d4fdb8ce8e..b3b5b40577 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -29,8 +29,7 @@ =20 void openrisc_cpu_do_interrupt(CPUState *cs) { - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - CPUOpenRISCState *env =3D &cpu->env; + CPUOpenRISCState *env =3D cpu_env(cs); int exception =3D cs->exception_index; =20 env->epcr =3D env->pc; @@ -105,8 +104,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) =20 bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - CPUOpenRISCState *env =3D &cpu->env; + CPUOpenRISCState *env =3D cpu_env(cs); int idx =3D -1; =20 if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) { diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index ecff4412b7..12899c911d 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1564,8 +1564,7 @@ static void openrisc_tr_insn_start(DisasContextBase *= dcbase, CPUState *cs) static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState = *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - uint32_t insn =3D translator_ldl(&cpu->env, &dc->base, dc->base.pc_nex= t); + uint32_t insn =3D translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_n= ext); =20 if (!decode(dc, insn)) { gen_illegal_exception(dc); @@ -1668,8 +1667,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int *max_insns, =20 void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - CPUOpenRISCState *env =3D &cpu->env; + CPUOpenRISCState *env =3D cpu_env(cs); int i; =20 qemu_fprintf(f, "PC=3D%08x\n", env->pc); --=20 2.41.0 From nobody Tue Nov 26 14:27:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706547030; cv=none; d=zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706547031242100003 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/ppc/mpc8544_guts.c | 3 +-- hw/ppc/pnv.c | 3 +-- hw/ppc/pnv_xscom.c | 5 +---- hw/ppc/ppce500_spin.c | 3 +-- hw/ppc/spapr.c | 3 +-- hw/ppc/spapr_caps.c | 7 ++----- target/ppc/cpu_init.c | 11 +++-------- target/ppc/excp_helper.c | 3 +-- target/ppc/gdbstub.c | 12 ++++-------- target/ppc/kvm.c | 12 ++++-------- target/ppc/ppc-qmp-cmds.c | 3 +-- target/ppc/user_only_helper.c | 3 +-- 12 files changed, 21 insertions(+), 47 deletions(-) diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mpc8544_guts.c index a26e83d048..e3540b0281 100644 --- a/hw/ppc/mpc8544_guts.c +++ b/hw/ppc/mpc8544_guts.c @@ -71,8 +71,7 @@ static uint64_t mpc8544_guts_read(void *opaque, hwaddr ad= dr, unsigned size) { uint32_t value =3D 0; - PowerPCCPU *cpu =3D POWERPC_CPU(current_cpu); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(current_cpu); =20 addr &=3D MPC8544_GUTS_MMIO_SIZE - 1; switch (addr) { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 202a569e27..77ee278a98 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2294,8 +2294,7 @@ static void pnv_machine_set_hb(Object *obj, bool valu= e, Error **errp) =20 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); =20 cpu_synchronize_state(cs); ppc_cpu_do_system_reset(cs); diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 805b1d0c87..a17816d072 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -44,15 +44,12 @@ static void xscom_complete(CPUState *cs, uint64_t hmer_= bits) * passed for the cpu, and no CPU completion is generated. */ if (cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; - /* * TODO: Need a CPU helper to set HMER, also handle generation * of HMIs */ cpu_synchronize_state(cs); - env->spr[SPR_HMER] |=3D hmer_bits; + cpu_env(cs)->spr[SPR_HMER] |=3D hmer_bits; } } =20 diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index bbce63e8a4..dfbe759481 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -90,8 +90,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *= env, =20 static void spin_kick(CPUState *cs, run_on_cpu_data data) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); SpinInfo *curspin =3D data.host_ptr; hwaddr map_size =3D 64 * MiB; hwaddr map_start; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 0b77aa5514..55d0fcb583 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3487,8 +3487,7 @@ static void spapr_machine_finalizefn(Object *obj) void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) { SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); =20 cpu_synchronize_state(cs); /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 = */ diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index e889244e52..cc91d59c57 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -194,8 +194,7 @@ static void cap_htm_apply(SpaprMachineState *spapr, uin= t8_t val, Error **errp) static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **e= rrp) { ERRP_GUARD(); - PowerPCCPU *cpu =3D POWERPC_CPU(first_cpu); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(first_cpu); =20 if (!val) { /* TODO: We don't support disabling vsx yet */ @@ -213,14 +212,12 @@ static void cap_vsx_apply(SpaprMachineState *spapr, u= int8_t val, Error **errp) static void cap_dfp_apply(SpaprMachineState *spapr, uint8_t val, Error **e= rrp) { ERRP_GUARD(); - PowerPCCPU *cpu =3D POWERPC_CPU(first_cpu); - CPUPPCState *env =3D &cpu->env; =20 if (!val) { /* TODO: We don't support disabling dfp yet */ return; } - if (!(env->insns_flags2 & PPC2_DFP)) { + if (!(cpu_env(first_cpu)->insns_flags2 & PPC2_DFP)) { error_setg(errp, "DFP support not available"); error_append_hint(errp, "Try appending -machine cap-dfp=3Doff\n"); } diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 61b8495a90..5d23b32c0e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7195,12 +7195,9 @@ static void ppc_cpu_reset_hold(Object *obj) =20 static bool ppc_cpu_is_big_endian(CPUState *cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; - cpu_synchronize_state(cs); =20 - return !FIELD_EX64(env->msr, MSR, LE); + return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE); } =20 static bool ppc_get_irq_stats(InterruptStatsProvider *obj, @@ -7287,8 +7284,7 @@ static bool ppc_pvr_match_default(PowerPCCPUClass *pc= c, uint32_t pvr, bool best) =20 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); =20 if ((env->hflags >> MSR_LE) & 1) { info->endian =3D BFD_ENDIAN_LITTLE; @@ -7446,8 +7442,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) #define RGPL 4 #define RFPL 4 =20 - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); int i; =20 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 2ec6429e36..fccfefa88e 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -2588,8 +2588,7 @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, tar= get_ulong vector) =20 bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); int interrupt; =20 if ((interrupt_request & CPU_INTERRUPT_HARD) =3D=3D 0) { diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index ec5731e5d6..fd986b1922 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -108,8 +108,7 @@ void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t= *mem_buf, int len) =20 int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); uint8_t *mem_buf; int r =3D ppc_gdb_register_len(n); =20 @@ -152,8 +151,7 @@ int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray = *buf, int n) =20 int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); uint8_t *mem_buf; int r =3D ppc_gdb_register_len_apple(n); =20 @@ -206,8 +204,7 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByte= Array *buf, int n) =20 int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); int r =3D ppc_gdb_register_len(n); =20 if (!r) { @@ -253,8 +250,7 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) } int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); int r =3D ppc_gdb_register_len_apple(n); =20 if (!r) { diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index b95a0b4928..b0e35b31a6 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -546,8 +546,7 @@ static void kvm_sw_tlb_put(PowerPCCPU *cpu) =20 static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); /* Init 'val' to avoid "uninitialised value" Valgrind warnings */ union { uint32_t u32; @@ -581,8 +580,7 @@ static void kvm_get_one_spr(CPUState *cs, uint64_t id, = int spr) =20 static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); union { uint32_t u32; uint64_t u64; @@ -615,8 +613,7 @@ static void kvm_put_one_spr(CPUState *cs, uint64_t id, = int spr) =20 static int kvm_put_fp(CPUState *cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); struct kvm_one_reg reg; int i; int ret; @@ -682,8 +679,7 @@ static int kvm_put_fp(CPUState *cs) =20 static int kvm_get_fp(CPUState *cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); struct kvm_one_reg reg; int i; int ret; diff --git a/target/ppc/ppc-qmp-cmds.c b/target/ppc/ppc-qmp-cmds.c index c0c137d9d7..9ac74f5c04 100644 --- a/target/ppc/ppc-qmp-cmds.c +++ b/target/ppc/ppc-qmp-cmds.c @@ -133,8 +133,7 @@ static int ppc_cpu_get_reg_num(const char *numstr, int = maxnum, int *pregnum) int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval) { int i, regnum; - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); =20 /* General purpose registers */ if ((qemu_tolower(name[0]) =3D=3D 'r') && diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index 7ff76f7a06..a4d07a0d0d 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -27,8 +27,7 @@ void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, bool maperr, uintptr_t retaddr) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; + CPUPPCState *env =3D cpu_env(cs); int exception, error_code; =20 /* --=20 2.41.0 From nobody Tue Nov 26 14:27:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706547029; cv=none; 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Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/arch_dump.c | 6 ++---- target/riscv/cpu.c | 17 +++++------------ target/riscv/cpu_helper.c | 17 +++++------------ target/riscv/debug.c | 9 +++------ target/riscv/gdbstub.c | 6 ++---- target/riscv/kvm/kvm-cpu.c | 11 +++-------- target/riscv/tcg/tcg-cpu.c | 10 +++------- target/riscv/translate.c | 6 ++---- 8 files changed, 25 insertions(+), 57 deletions(-) diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c index 434c8a3dbb..994709647f 100644 --- a/target/riscv/arch_dump.c +++ b/target/riscv/arch_dump.c @@ -68,8 +68,7 @@ int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, C= PUState *cs, int cpuid, DumpState *s) { struct riscv64_note note; - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); int ret, i =3D 0; const char name[] =3D "CORE"; =20 @@ -137,8 +136,7 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f,= CPUState *cs, int cpuid, DumpState *s) { struct riscv32_note note; - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); int ret, i; const char name[] =3D "CORE"; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1bd99bc5c6..8af4f7a088 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -419,8 +419,7 @@ static void riscv_any_cpu_init(Object *obj) =20 static void riscv_max_cpu_init(Object *obj) { - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(CPU(obj)); RISCVMXL mlx =3D MXL_RV64; =20 #ifdef TARGET_RISCV32 @@ -828,8 +827,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) =20 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); =20 if (env->xl =3D=3D MXL_RV32) { env->pc =3D (int32_t)value; @@ -840,8 +838,7 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value) =20 static vaddr riscv_cpu_get_pc(CPUState *cs) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); =20 /* Match cpu_get_tb_cpu_state. */ if (env->xl =3D=3D MXL_RV32) { @@ -853,8 +850,7 @@ static vaddr riscv_cpu_get_pc(CPUState *cs) static bool riscv_cpu_has_work(CPUState *cs) { #ifndef CONFIG_USER_ONLY - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); /* * Definition of the WFI instruction requires it to ignore the privile= ge * mode and delegation registers, but respect individual enables @@ -1642,10 +1638,7 @@ static void rva22s64_profile_cpu_init(Object *obj) =20 static const gchar *riscv_gdb_arch_name(CPUState *cs) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - - switch (riscv_cpu_mxl(env)) { + switch (riscv_cpu_mxl(cpu_env(cs))) { case MXL_RV32: return "riscv:rv32"; case MXL_RV64: diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 791435d628..01b32a3f83 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -493,9 +493,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *e= nv) bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - int interruptno =3D riscv_cpu_local_irq_pending(env); + int interruptno =3D riscv_cpu_local_irq_pending(cpu_env(cs)); if (interruptno >=3D 0) { cs->exception_index =3D RISCV_EXCP_INT_FLAG | interruptno; riscv_cpu_do_interrupt(cs); @@ -1196,8 +1194,7 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, =20 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); hwaddr phys_addr; int prot; int mmu_idx =3D cpu_mmu_index(env, false); @@ -1223,8 +1220,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hw= addr physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retad= dr) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); =20 if (access_type =3D=3D MMU_DATA_STORE) { cs->exception_index =3D RISCV_EXCP_STORE_AMO_ACCESS_FAULT; @@ -1244,8 +1240,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); switch (access_type) { case MMU_INST_FETCH: cs->exception_index =3D RISCV_EXCP_INST_ADDR_MIS; @@ -1631,9 +1626,7 @@ static target_ulong riscv_transformed_insn(CPURISCVSt= ate *env, void riscv_cpu_do_interrupt(CPUState *cs) { #if !defined(CONFIG_USER_ONLY) - - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); bool write_gva =3D false; uint64_t s; =20 diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 4945d1a1f2..c8df9812be 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -757,8 +757,7 @@ target_ulong tinfo_csr_read(CPURISCVState *env) =20 void riscv_cpu_debug_excp_handler(CPUState *cs) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); =20 if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { @@ -773,8 +772,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) =20 bool riscv_cpu_debug_check_breakpoint(CPUState *cs) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); CPUBreakpoint *bp; target_ulong ctrl; target_ulong pc; @@ -832,8 +830,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) =20 bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); target_ulong ctrl; target_ulong addr; int trigger_type; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 58b3ace0fe..999d815b34 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -49,8 +49,7 @@ static const struct TypeSize vec_lanes[] =3D { =20 int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); target_ulong tmp; =20 if (n < 32) { @@ -75,8 +74,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) =20 int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); int length =3D 0; target_ulong tmp; =20 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 680a729cd8..563b371ec9 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -171,9 +171,7 @@ static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visit= or *v, { KVMCPUConfig *misa_ext_cfg =3D opaque; target_ulong misa_bit =3D misa_ext_cfg->offset; - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - bool value =3D env->misa_ext_mask & misa_bit; + bool value =3D cpu_env(CPU(obj))->misa_ext_mask & misa_bit; =20 visit_type_bool(v, name, &value, errp); } @@ -184,15 +182,13 @@ static void kvm_cpu_set_misa_ext_cfg(Object *obj, Vis= itor *v, { KVMCPUConfig *misa_ext_cfg =3D opaque; target_ulong misa_bit =3D misa_ext_cfg->offset; - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; bool value, host_bit; =20 if (!visit_type_bool(v, name, &value, errp)) { return; } =20 - host_bit =3D env->misa_ext_mask & misa_bit; + host_bit =3D cpu_env(CPU(obj))->misa_ext_mask & misa_bit; =20 if (value =3D=3D host_bit) { return; @@ -1583,10 +1579,9 @@ static void kvm_cpu_instance_init(CPUState *cs) */ static bool kvm_cpu_realize(CPUState *cs, Error **errp) { - RISCVCPU *cpu =3D RISCV_CPU(cs); int ret; =20 - if (riscv_has_ext(&cpu->env, RVV)) { + if (riscv_has_ext(cpu_env(cs), RVV)) { ret =3D prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); if (ret) { error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code:= %s", diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 994ca1cdf9..e0f05d898c 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -92,8 +92,7 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { if (!(tb_cflags(tb) & CF_PCREL)) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); =20 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); @@ -110,8 +109,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); target_ulong pc; =20 @@ -1030,11 +1028,9 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visito= r *v, const char *name, { const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; target_ulong misa_bit =3D misa_ext_cfg->misa_bit; - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; bool value; =20 - value =3D env->misa_ext & misa_bit; + value =3D cpu_env(CPU(obj))->misa_ext & misa_bit; =20 visit_type_bool(v, name, &value, errp); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 071fbad7ef..24db9f3882 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1074,9 +1074,8 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUState *cpu =3D ctx->cs; - CPURISCVState *env =3D cpu_env(cpu); =20 - return cpu_ldl_code(env, pc); + return cpu_ldl_code(cpu_env(cpu), pc); } =20 /* Include insn module translation function */ @@ -1265,8 +1264,7 @@ static void riscv_tr_disas_log(const DisasContextBase= *dcbase, CPUState *cpu, FILE *logfile) { #ifndef CONFIG_USER_ONLY - RISCVCPU *rvcpu =3D RISCV_CPU(cpu); - CPURISCVState *env =3D &rvcpu->env; + CPURISCVState *env =3D cpu_env(cpu); #endif =20 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); --=20 2.41.0 From nobody Tue Nov 26 14:27:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706547453; cv=none; d=zohomail.com; s=zohoarc; b=SyUNY+Y2mWaX3yOUgfBlqyRCUVCOG3x7kzaQNgatmUygE7+s2aTKKPrhiWDV4HxG/xBYWHEwY7a3Wtb5w9EcgC0nHWa1Cj8XjoHXLhVUyvZ2E3YqgcXOBSccyp+2wkfLYUvDqps7ZGUvhaUPohU0Ev1tXYnAfcDaJNHrWsF02Ww= ARC-Message-Signature: i=1; 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Mon, 29 Jan 2024 08:47:40 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato Subject: [PATCH v3 23/29] target/rx: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:45:05 +0100 Message-ID: <20240129164514.73104-24-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706547454456100003 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/rx/cpu.c | 4 ++-- target/rx/gdbstub.c | 6 ++---- target/rx/helper.c | 6 ++---- target/rx/translate.c | 3 +-- 4 files changed, 7 insertions(+), 12 deletions(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 58ca26184d..4689587fa9 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -66,9 +66,9 @@ static bool rx_cpu_has_work(CPUState *cs) =20 static void rx_cpu_reset_hold(Object *obj) { - RXCPU *cpu =3D RX_CPU(obj); + CPUState *cs =3D CPU(obj); RXCPUClass *rcc =3D RX_CPU_GET_CLASS(obj); - CPURXState *env =3D &cpu->env; + CPURXState *env =3D cpu_env(cs); uint32_t *resetvec; =20 if (rcc->parent_phases.hold) { diff --git a/target/rx/gdbstub.c b/target/rx/gdbstub.c index d7e0e6689b..f222bf003b 100644 --- a/target/rx/gdbstub.c +++ b/target/rx/gdbstub.c @@ -21,8 +21,7 @@ =20 int rx_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - RXCPU *cpu =3D RX_CPU(cs); - CPURXState *env =3D &cpu->env; + CPURXState *env =3D cpu_env(cs); =20 switch (n) { case 0 ... 15: @@ -53,8 +52,7 @@ int rx_cpu_gdb_read_register(CPUState *cs, GByteArray *me= m_buf, int n) =20 int rx_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - RXCPU *cpu =3D RX_CPU(cs); - CPURXState *env =3D &cpu->env; + CPURXState *env =3D cpu_env(cs); uint32_t psw; switch (n) { case 0 ... 15: diff --git a/target/rx/helper.c b/target/rx/helper.c index dad5fb4976..80912e8dcb 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -45,8 +45,7 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int= rte) #define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR) void rx_cpu_do_interrupt(CPUState *cs) { - RXCPU *cpu =3D RX_CPU(cs); - CPURXState *env =3D &cpu->env; + CPURXState *env =3D cpu_env(cs); int do_irq =3D cs->interrupt_request & INT_FLAGS; uint32_t save_psw; =20 @@ -122,8 +121,7 @@ void rx_cpu_do_interrupt(CPUState *cs) =20 bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - RXCPU *cpu =3D RX_CPU(cs); - CPURXState *env =3D &cpu->env; + CPURXState *env =3D cpu_env(cs); int accept =3D 0; /* hardware interrupt (Normal) */ if ((interrupt_request & CPU_INTERRUPT_HARD) && diff --git a/target/rx/translate.c b/target/rx/translate.c index 1829a0b1cd..26aaf7a6b5 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -131,8 +131,7 @@ static int bdsp_s(DisasContext *ctx, int d) =20 void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - RXCPU *cpu =3D RX_CPU(cs); - CPURXState *env =3D &cpu->env; + CPURXState *env =3D cpu_env(cs); int i; uint32_t psw; =20 --=20 2.41.0 From nobody Tue Nov 26 14:27:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706547040; cv=none; d=zohomail.com; s=zohoarc; b=D63pEpuF3u7nkafGu5MSr8QJ/9kwKFMtj5RL6jGNZlPoGRy7n2baJIW+lDbIpSSaXB4nk1B7QMyU09ocoeZQWmq7gwOOOwKuwCEZF2mOCODPX0tXJmJIHGStGjisNAlSeNY9leBtt0OVG//iqRdgW+NFJugZqLG0eSMQTV4t1RQ= ARC-Message-Signature: i=1; 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Mon, 29 Jan 2024 08:47:45 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , David Hildenbrand , Ilya Leoshkevich , Halil Pasic , Christian Borntraeger Subject: [PATCH v3 24/29] target/s390x: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:45:06 +0100 Message-ID: <20240129164514.73104-25-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth --- target/s390x/cpu-dump.c | 3 +-- target/s390x/gdbstub.c | 6 ++---- target/s390x/helper.c | 3 +-- target/s390x/kvm/kvm.c | 6 ++---- target/s390x/tcg/excp_helper.c | 11 +++-------- target/s390x/tcg/misc_helper.c | 4 +--- target/s390x/tcg/translate.c | 3 +-- 7 files changed, 11 insertions(+), 25 deletions(-) diff --git a/target/s390x/cpu-dump.c b/target/s390x/cpu-dump.c index ffa9e94d84..69cc9f7746 100644 --- a/target/s390x/cpu-dump.c +++ b/target/s390x/cpu-dump.c @@ -27,8 +27,7 @@ =20 void s390_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - S390CPU *cpu =3D S390_CPU(cs); - CPUS390XState *env =3D &cpu->env; + CPUS390XState *env =3D cpu_env(cs); int i; =20 qemu_fprintf(f, "PSW=3Dmask %016" PRIx64 " addr %016" PRIx64, diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 6fbfd41bc8..f02fa316e5 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -30,8 +30,7 @@ =20 int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - S390CPU *cpu =3D S390_CPU(cs); - CPUS390XState *env =3D &cpu->env; + CPUS390XState *env =3D cpu_env(cs); =20 switch (n) { case S390_PSWM_REGNUM: @@ -46,8 +45,7 @@ int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *= mem_buf, int n) =20 int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - S390CPU *cpu =3D S390_CPU(cs); - CPUS390XState *env =3D &cpu->env; + CPUS390XState *env =3D cpu_env(cs); target_ulong tmpl =3D ldtul_p(mem_buf); =20 switch (n) { diff --git a/target/s390x/helper.c b/target/s390x/helper.c index d76c06381b..00d5d403f3 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -139,8 +139,7 @@ void do_restart_interrupt(CPUS390XState *env) void s390_cpu_recompute_watchpoints(CPUState *cs) { const int wp_flags =3D BP_CPU | BP_MEM_WRITE | BP_STOP_BEFORE_ACCESS; - S390CPU *cpu =3D S390_CPU(cs); - CPUS390XState *env =3D &cpu->env; + CPUS390XState *env =3D cpu_env(cs); =20 /* We are called when the watchpoints have changed. First remove them all. */ diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 888d6c1a1c..4ce809c5d4 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -474,8 +474,7 @@ static int can_sync_regs(CPUState *cs, int regs) =20 int kvm_arch_put_registers(CPUState *cs, int level) { - S390CPU *cpu =3D S390_CPU(cs); - CPUS390XState *env =3D &cpu->env; + CPUS390XState *env =3D cpu_env(cs); struct kvm_fpu fpu =3D {}; int r; int i; @@ -601,8 +600,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) =20 int kvm_arch_get_registers(CPUState *cs) { - S390CPU *cpu =3D S390_CPU(cs); - CPUS390XState *env =3D &cpu->env; + CPUS390XState *env =3D cpu_env(cs); struct kvm_fpu fpu; int i, r; =20 diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index b875bf14e5..f1c33f7967 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -90,10 +90,7 @@ void HELPER(data_exception)(CPUS390XState *env, uint32_t= dxc) static G_NORETURN void do_unaligned_access(CPUState *cs, uintptr_t retaddr) { - S390CPU *cpu =3D S390_CPU(cs); - CPUS390XState *env =3D &cpu->env; - - tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr); + tcg_s390_program_interrupt(cpu_env(cs), PGM_SPECIFICATION, retaddr); } =20 #if defined(CONFIG_USER_ONLY) @@ -146,8 +143,7 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - S390CPU *cpu =3D S390_CPU(cs); - CPUS390XState *env =3D &cpu->env; + CPUS390XState *env =3D cpu_env(cs); target_ulong vaddr, raddr; uint64_t asc, tec; int prot, excp; @@ -600,8 +596,7 @@ bool s390_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) =20 void s390x_cpu_debug_excp_handler(CPUState *cs) { - S390CPU *cpu =3D S390_CPU(cs); - CPUS390XState *env =3D &cpu->env; + CPUS390XState *env =3D cpu_env(cs); CPUWatchpoint *wp_hit =3D cs->watchpoint_hit; =20 if (wp_hit && wp_hit->flags & BP_CPU) { diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 89b5268fd4..8764846ce8 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -214,9 +214,7 @@ void HELPER(sckc)(CPUS390XState *env, uint64_t ckc) =20 void tcg_s390_tod_updated(CPUState *cs, run_on_cpu_data opaque) { - S390CPU *cpu =3D S390_CPU(cs); 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Mon, 29 Jan 2024 08:47:51 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato Subject: [PATCH v3 25/29] target/sh4: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:45:07 +0100 Message-ID: <20240129164514.73104-26-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; 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Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/sh4/cpu.c | 18 ++++++------------ target/sh4/gdbstub.c | 6 ++---- target/sh4/helper.c | 14 ++++---------- target/sh4/translate.c | 6 ++---- 4 files changed, 14 insertions(+), 30 deletions(-) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 1b03c7bcb1..3308a2be07 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -71,8 +71,7 @@ static void superh_restore_state_to_opc(CPUState *cs, static bool superh_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(cs); =20 if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND)) && !(cs->tcg_cflags & CF_PCREL) && env->pc !=3D tb->pc) { @@ -92,9 +91,8 @@ static bool superh_cpu_has_work(CPUState *cs) static void superh_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); - SuperHCPU *cpu =3D SUPERH_CPU(cs); SuperHCPUClass *scc =3D SUPERH_CPU_GET_CLASS(obj); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(cs); =20 if (scc->parent_phases.hold) { scc->parent_phases.hold(obj); @@ -144,8 +142,7 @@ out: =20 static void sh7750r_cpu_initfn(Object *obj) { - SuperHCPU *cpu =3D SUPERH_CPU(obj); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(CPU(obj)); =20 env->id =3D SH_CPU_SH7750R; env->features =3D SH_FEATURE_BCR3_AND_BCR4; @@ -162,8 +159,7 @@ static void sh7750r_class_init(ObjectClass *oc, void *d= ata) =20 static void sh7751r_cpu_initfn(Object *obj) { - SuperHCPU *cpu =3D SUPERH_CPU(obj); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(CPU(obj)); =20 env->id =3D SH_CPU_SH7751R; env->features =3D SH_FEATURE_BCR3_AND_BCR4; @@ -180,8 +176,7 @@ static void sh7751r_class_init(ObjectClass *oc, void *d= ata) =20 static void sh7785_cpu_initfn(Object *obj) { - SuperHCPU *cpu =3D SUPERH_CPU(obj); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(CPU(obj)); =20 env->id =3D SH_CPU_SH7785; env->features =3D SH_FEATURE_SH4A; @@ -216,8 +211,7 @@ static void superh_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 static void superh_cpu_initfn(Object *obj) { - SuperHCPU *cpu =3D SUPERH_CPU(obj); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(CPU(obj)); =20 env->movcal_backup_tail =3D &(env->movcal_backup); } diff --git a/target/sh4/gdbstub.c b/target/sh4/gdbstub.c index d8e199fc06..75926d4e04 100644 --- a/target/sh4/gdbstub.c +++ b/target/sh4/gdbstub.c @@ -26,8 +26,7 @@ =20 int superh_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(cs); =20 switch (n) { case 0 ... 7: @@ -76,8 +75,7 @@ int superh_cpu_gdb_read_register(CPUState *cs, GByteArray= *mem_buf, int n) =20 int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(cs); =20 switch (n) { case 0 ... 7: diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 5a6f653c12..7c6f9d374a 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -55,8 +55,7 @@ int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr) =20 void superh_cpu_do_interrupt(CPUState *cs) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(cs); int do_irq =3D cs->interrupt_request & CPU_INTERRUPT_HARD; int do_exp, irq_vector =3D cs->exception_index; =20 @@ -432,11 +431,10 @@ static int get_physical_address(CPUSH4State * env, ta= rget_ulong * physical, =20 hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); target_ulong physical; int prot; =20 - if (get_physical_address(&cpu->env, &physical, &prot, addr, MMU_DATA_L= OAD) + if (get_physical_address(cpu_env(cs), &physical, &prot, addr, MMU_DATA= _LOAD) =3D=3D MMU_OK) { return physical; } @@ -782,11 +780,8 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong = addr) bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; - /* Delay slots are indivisible, ignore interrupts */ - if (env->flags & TB_FLAG_DELAY_SLOT_MASK) { + if (cpu_env(cs)->flags & TB_FLAG_DELAY_SLOT_MASK) { return false; } else { superh_cpu_do_interrupt(cs); @@ -800,8 +795,7 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(cs); int ret; =20 target_ulong physical; diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 81f825f125..d9f222bd15 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -159,8 +159,7 @@ void sh4_translate_init(void) =20 void superh_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; + CPUSH4State *env =3D cpu_env(cs); int i; =20 qemu_fprintf(f, "pc=3D0x%08x sr=3D0x%08x pr=3D0x%08x fpscr=3D0x%08x\n", @@ -2186,7 +2185,6 @@ static void decode_gusa(DisasContext *ctx, CPUSH4Stat= e *env) static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUSH4State *env =3D cpu_env(cs); uint32_t tbflags; int bound; =20 @@ -2196,7 +2194,7 @@ static void sh4_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) /* We don't know if the delayed pc came from a dynamic or static branc= h, so assume it is a dynamic branch. */ ctx->delayed_pc =3D -1; /* use delayed pc from env pointer */ - ctx->features =3D env->features; + ctx->features =3D cpu_env(cs)->features; ctx->has_movcal =3D (tbflags & TB_FLAG_PENDING_MOVCA); ctx->gbank =3D ((tbflags & (1 << SR_MD)) && (tbflags & (1 << SR_RB))) * 0x10; --=20 2.41.0 From nobody Tue Nov 26 14:27:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706547235; cv=none; d=zohomail.com; s=zohoarc; b=iVRT4fEJ1aozGoA959oh6V1D8dQCtPmVVGCwio4R6JucWX3TKgxdcOy4YbQ/fKgeBbAROvJOOAdq3C3khqALcotDqDXw7yoEp1SUd1GA9JKiWvgJVFEg7qssNudoYN7nNy0x7p72cJH3fkbgTbJp2h76mO5s98xQjaDFryPO72o= ARC-Message-Signature: i=1; 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Mon, 29 Jan 2024 08:47:57 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH v3 26/29] target/sparc: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:45:08 +0100 Message-ID: <20240129164514.73104-27-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706547235856100001 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Mark Cave-Ayland --- target/sparc/cpu.c | 17 +++++------------ target/sparc/gdbstub.c | 3 +-- target/sparc/int32_helper.c | 3 +-- target/sparc/int64_helper.c | 3 +-- target/sparc/ldst_helper.c | 6 ++---- target/sparc/mmu_helper.c | 15 +++++---------- target/sparc/translate.c | 9 +++------ 7 files changed, 18 insertions(+), 38 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 152bee4f81..72a9b9a285 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -32,9 +32,8 @@ static void sparc_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); - SPARCCPU *cpu =3D SPARC_CPU(cs); SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(obj); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); =20 if (scc->parent_phases.hold) { scc->parent_phases.hold(obj); @@ -83,8 +82,7 @@ static void sparc_cpu_reset_hold(Object *obj) static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); =20 if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) { int pil =3D env->interrupt_index & 0xf; @@ -613,8 +611,7 @@ static void cpu_print_cc(FILE *f, uint32_t cc) =20 static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); int i, x; =20 qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env= ->pc, @@ -711,11 +708,8 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, =20 static bool sparc_cpu_has_work(CPUState *cs) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; - return (cs->interrupt_request & CPU_INTERRUPT_HARD) && - cpu_interrupts_enabled(env); + cpu_interrupts_enabled(cpu_env(cs)); } =20 static char *sparc_cpu_type_name(const char *cpu_model) @@ -749,8 +743,7 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error= **errp) CPUState *cs =3D CPU(dev); SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(dev); Error *local_err =3D NULL; - SPARCCPU *cpu =3D SPARC_CPU(dev); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); =20 #if defined(CONFIG_USER_ONLY) /* We are emulating the kernel, which will trap and emulate float128. = */ diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index a1c8fdc4d5..5257c49a0d 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -29,8 +29,7 @@ =20 int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); =20 if (n < 8) { /* g0..g7 */ diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index 058dd712b5..6b7d65b031 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -99,8 +99,7 @@ void cpu_check_irqs(CPUSPARCState *env) =20 void sparc_cpu_do_interrupt(CPUState *cs) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); int cwp, intno =3D cs->exception_index; =20 if (qemu_loglevel_mask(CPU_LOG_INT)) { diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c index 27df9dba89..bd14c7a0db 100644 --- a/target/sparc/int64_helper.c +++ b/target/sparc/int64_helper.c @@ -130,8 +130,7 @@ void cpu_check_irqs(CPUSPARCState *env) =20 void sparc_cpu_do_interrupt(CPUState *cs) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); int intno =3D cs->exception_index; trap_state *tsptr; =20 diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 09066d5487..203441bfb2 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -421,8 +421,7 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr = addr, bool is_write, bool is_exec, int is_asi, unsigned size, uintptr_t retaddr) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); int fault_type; =20 #ifdef DEBUG_UNASSIGNED @@ -483,8 +482,7 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr = addr, bool is_write, bool is_exec, int is_asi, unsigned size, uintptr_t retaddr) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); =20 #ifdef DEBUG_UNASSIGNED printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_= lx diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 453498c670..a05ee22315 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -206,8 +206,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); CPUTLBEntryFull full =3D {}; target_ulong vaddr; int error_code =3D 0, access_index; @@ -391,8 +390,7 @@ void dump_mmu(CPUSPARCState *env) int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, int len, bool is_write) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); target_ulong addr =3D address; int i; int len1; @@ -759,8 +757,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); CPUTLBEntryFull full =3D {}; int error_code =3D 0, access_index; =20 @@ -898,8 +895,7 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, ta= rget_ulong addr, =20 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); hwaddr phys_addr; int mmu_idx =3D cpu_mmu_index(env, false); =20 @@ -916,8 +912,7 @@ G_NORETURN void sparc_cpu_do_unaligned_access(CPUState = *cs, vaddr addr, int mmu_idx, uintptr_t retaddr) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; + CPUSPARCState *env =3D cpu_env(cs); =20 #ifdef TARGET_SPARC64 env->dmmu.sfsr =3D build_sfsr(env, mmu_idx, access_type); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9387299559..769418d6b0 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5154,13 +5154,12 @@ TRANS(FCMPEq, ALL, do_fcmpq, a, true) static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUSPARCState *env =3D cpu_env(cs); int bound; =20 dc->pc =3D dc->base.pc_first; dc->npc =3D (target_ulong)dc->base.tb->cs_base; dc->mem_idx =3D dc->base.tb->flags & TB_FLAG_MMU_MASK; - dc->def =3D &env->def; + dc->def =3D &cpu_env(cs)->def; dc->fpu_enabled =3D tb_fpu_enabled(dc->base.tb->flags); dc->address_mask_32bit =3D tb_am_enabled(dc->base.tb->flags); #ifndef CONFIG_USER_ONLY @@ -5210,10 +5209,9 @@ static void sparc_tr_insn_start(DisasContextBase *dc= base, CPUState *cs) static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); 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Mon, 29 Jan 2024 08:48:03 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bastian Koppelmann Subject: [PATCH v3 27/29] target/tricore: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:45:09 +0100 Message-ID: <20240129164514.73104-28-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706547412573100015 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Bastian Koppelmann --- target/tricore/cpu.c | 24 +++++------------------- target/tricore/gdbstub.c | 6 ++---- target/tricore/helper.c | 3 +-- target/tricore/translate.c | 3 +-- 4 files changed, 9 insertions(+), 27 deletions(-) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 9bdaa1593a..7c4a9b41a3 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -36,52 +36,38 @@ static const gchar *tricore_gdb_arch_name(CPUState *cs) =20 static void tricore_cpu_set_pc(CPUState *cs, vaddr value) { - TriCoreCPU *cpu =3D TRICORE_CPU(cs); - CPUTriCoreState *env =3D &cpu->env; - - env->PC =3D value & ~(target_ulong)1; + cpu_env(cs)->PC =3D value & ~(target_ulong)1; } =20 static vaddr tricore_cpu_get_pc(CPUState *cs) { - TriCoreCPU *cpu =3D TRICORE_CPU(cs); - CPUTriCoreState *env =3D &cpu->env; - - return env->PC; + return cpu_env(cs)->PC; } =20 static void tricore_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - TriCoreCPU *cpu =3D TRICORE_CPU(cs); - CPUTriCoreState *env =3D &cpu->env; - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - env->PC =3D tb->pc; + cpu_env(cs)->PC =3D tb->pc; } =20 static void tricore_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - TriCoreCPU *cpu =3D TRICORE_CPU(cs); - CPUTriCoreState *env =3D &cpu->env; - - env->PC =3D data[0]; + cpu_env(cs)->PC =3D data[0]; } =20 static void tricore_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); - TriCoreCPU *cpu =3D TRICORE_CPU(cs); TriCoreCPUClass *tcc =3D TRICORE_CPU_GET_CLASS(obj); - CPUTriCoreState *env =3D &cpu->env; =20 if (tcc->parent_phases.hold) { tcc->parent_phases.hold(obj); } =20 - cpu_state_reset(env); + cpu_state_reset(cpu_env(cs)); } =20 static bool tricore_cpu_has_work(CPUState *cs) diff --git a/target/tricore/gdbstub.c b/target/tricore/gdbstub.c index e8f8e5e6ea..f9309c5e27 100644 --- a/target/tricore/gdbstub.c +++ b/target/tricore/gdbstub.c @@ -106,8 +106,7 @@ static void tricore_cpu_gdb_write_csfr(CPUTriCoreState = *env, int n, =20 int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - TriCoreCPU *cpu =3D TRICORE_CPU(cs); - CPUTriCoreState *env =3D &cpu->env; + CPUTriCoreState *env =3D cpu_env(cs); =20 if (n < 16) { /* data registers */ return gdb_get_reg32(mem_buf, env->gpr_d[n]); @@ -121,8 +120,7 @@ int tricore_cpu_gdb_read_register(CPUState *cs, GByteAr= ray *mem_buf, int n) =20 int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - TriCoreCPU *cpu =3D TRICORE_CPU(cs); - CPUTriCoreState *env =3D &cpu->env; + CPUTriCoreState *env =3D cpu_env(cs); uint32_t tmp; =20 tmp =3D ldl_p(mem_buf); diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 174f666e1e..d328414c99 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -67,8 +67,7 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, MMUAccessType rw, int mmu_idx, bool probe, uintptr_t retaddr) { - TriCoreCPU *cpu =3D TRICORE_CPU(cs); - CPUTriCoreState *env =3D &cpu->env; + CPUTriCoreState *env =3D cpu_env(cs); hwaddr physical; int prot; int ret =3D 0; diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 66553d1be0..ad314bdf3c 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -95,8 +95,7 @@ enum { =20 void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - TriCoreCPU *cpu =3D TRICORE_CPU(cs); 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Mon, 29 Jan 2024 08:48:10 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Max Filippov Subject: [PATCH v3 28/29] target/xtensa: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Mon, 29 Jan 2024 17:45:10 +0100 Message-ID: <20240129164514.73104-29-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129164514.73104-1-philmd@linaro.org> References: <20240129164514.73104-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12f; 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Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/xtensa/cpu.c | 3 +-- target/xtensa/dbg_helper.c | 3 +-- target/xtensa/exc_helper.c | 3 +-- target/xtensa/gdbstub.c | 6 ++---- target/xtensa/helper.c | 9 +++------ target/xtensa/translate.c | 6 ++---- 6 files changed, 10 insertions(+), 20 deletions(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index ce044466ad..47fd7c7ca9 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -91,9 +91,8 @@ bool xtensa_abi_call0(void) static void xtensa_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); - XtensaCPU *cpu =3D XTENSA_CPU(cs); XtensaCPUClass *xcc =3D XTENSA_CPU_GET_CLASS(obj); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); bool dfpu =3D xtensa_option_enabled(env->config, XTENSA_OPTION_DFP_COPROCESSOR); =20 diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index 497dafca71..5546c82ecd 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -66,8 +66,7 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i,= uint32_t v) =20 bool xtensa_debug_check_breakpoint(CPUState *cs) { - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); unsigned int i; =20 if (xtensa_get_cintlevel(env) >=3D env->config->debug_level) { diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index 168419a505..0514c2c1f3 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -205,8 +205,7 @@ static void handle_interrupt(CPUXtensaState *env) /* Called from cpu_handle_interrupt with BQL held */ void xtensa_cpu_do_interrupt(CPUState *cs) { - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); =20 if (cs->exception_index =3D=3D EXC_IRQ) { qemu_log_mask(CPU_LOG_INT, diff --git a/target/xtensa/gdbstub.c b/target/xtensa/gdbstub.c index 4b3bfb7e59..4748fb6532 100644 --- a/target/xtensa/gdbstub.c +++ b/target/xtensa/gdbstub.c @@ -65,8 +65,7 @@ void xtensa_count_regs(const XtensaConfig *config, =20 int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); const XtensaGdbReg *reg =3D env->config->gdb_regmap.reg + n; #ifdef CONFIG_USER_ONLY int num_regs =3D env->config->gdb_regmap.num_core_regs; @@ -120,8 +119,7 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArr= ay *mem_buf, int n) =20 int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); uint32_t tmp; const XtensaGdbReg *reg =3D env->config->gdb_regmap.reg + n; #ifdef CONFIG_USER_ONLY diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index a9f8907083..ca214b948a 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -217,8 +217,7 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *en= v) =20 void xtensa_breakpoint_handler(CPUState *cs) { - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); =20 if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { @@ -266,8 +265,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); uint32_t paddr; uint32_t page_size; unsigned access; @@ -297,8 +295,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t reta= ddr) { - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); =20 cpu_restore_state(cs, retaddr); HELPER(exception_cause_vaddr)(env, env->pc, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 87947236ca..e646e016df 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1127,10 +1127,9 @@ static void xtensa_tr_init_disas_context(DisasContex= tBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706547087375100003 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Warner Losh --- bsd-user/signal.c | 3 +-- linux-user/signal.c | 6 ++---- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/bsd-user/signal.c b/bsd-user/signal.c index ca31470772..c6f0b1be38 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -463,14 +463,13 @@ static int fatal_signal(int sig) void force_sig_fault(int sig, int code, abi_ulong addr) { CPUState *cpu =3D thread_cpu; - CPUArchState *env =3D cpu_env(cpu); target_siginfo_t info =3D {}; =20 info.si_signo =3D sig; info.si_errno =3D 0; info.si_code =3D code; info.si_addr =3D addr; - queue_signal(env, sig, QEMU_SI_FAULT, &info); + queue_signal(cpu_env(cpu), sig, QEMU_SI_FAULT, &info); } =20 static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) diff --git a/linux-user/signal.c b/linux-user/signal.c index c9527adfa3..f78f7fc476 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -623,7 +623,6 @@ void signal_init(void) void force_sig(int sig) { CPUState *cpu =3D thread_cpu; - CPUArchState *env =3D cpu_env(cpu); target_siginfo_t info =3D {}; =20 info.si_signo =3D sig; @@ -631,7 +630,7 @@ void force_sig(int sig) info.si_code =3D TARGET_SI_KERNEL; info._sifields._kill._pid =3D 0; info._sifields._kill._uid =3D 0; - queue_signal(env, info.si_signo, QEMU_SI_KILL, &info); + queue_signal(cpu_env(cpu), info.si_signo, QEMU_SI_KILL, &info); } =20 /* @@ -641,14 +640,13 @@ void force_sig(int sig) void force_sig_fault(int sig, int code, abi_ulong addr) { CPUState *cpu =3D thread_cpu; - CPUArchState *env =3D cpu_env(cpu); target_siginfo_t info =3D {}; =20 info.si_signo =3D sig; info.si_errno =3D 0; info.si_code =3D code; info._sifields._sigfault._addr =3D addr; - queue_signal(env, sig, QEMU_SI_FAULT, &info); + queue_signal(cpu_env(cpu), sig, QEMU_SI_FAULT, &info); } =20 /* Force a SIGSEGV if we couldn't write to memory trying to set --=20 2.41.0