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Iglesias" , Peter Maydell , Rob Herring , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PATCH v3 1/9] hw/arm/exynos: Add missing QOM parent for CPU cores Date: Mon, 29 Jan 2024 16:18:20 +0100 Message-ID: <20240129151828.59544-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706541573025100001 QDev objects created with qdev_new() need to manually add their parent relationship with object_property_add_child(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan --- hw/arm/exynos4210.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 6c428d8eeb..57c77b140c 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -556,6 +556,7 @@ static void exynos4210_realize(DeviceState *socdev, Err= or **errp) for (n =3D 0; n < EXYNOS4210_NCPUS; n++) { Object *cpuobj =3D object_new(ARM_CPU_TYPE_NAME("cortex-a9")); =20 + object_property_add_child(OBJECT(s), "cpu[*]", cpuobj); /* By default A9 CPUs have EL3 enabled. This board does not curre= ntly * support EL3 so the CPU EL3 property is disabled before realizat= ion. */ --=20 2.41.0