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Iglesias" , Peter Maydell , Rob Herring , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PATCH v3 1/9] hw/arm/exynos: Add missing QOM parent for CPU cores Date: Mon, 29 Jan 2024 16:18:20 +0100 Message-ID: <20240129151828.59544-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706541573025100001 QDev objects created with qdev_new() need to manually add their parent relationship with object_property_add_child(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan --- hw/arm/exynos4210.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 6c428d8eeb..57c77b140c 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -556,6 +556,7 @@ static void exynos4210_realize(DeviceState *socdev, Err= or **errp) for (n =3D 0; n < EXYNOS4210_NCPUS; n++) { Object *cpuobj =3D object_new(ARM_CPU_TYPE_NAME("cortex-a9")); =20 + object_property_add_child(OBJECT(s), "cpu[*]", cpuobj); /* By default A9 CPUs have EL3 enabled. This board does not curre= ntly * support EL3 so the CPU EL3 property is disabled before realizat= ion. */ --=20 2.41.0 From nobody Tue Nov 26 15:16:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706541572; cv=none; d=zohomail.com; s=zohoarc; b=ZgqNEjio0D7rvreucjFWv6ciSSQI/Un88soTxgo7Xx6Dm4lEUpKfQ8qJRHgEvGE5UcBXsj9EoCVzMgaNXPbBhkoF10NZx2V8cmcEhf29P/Tswv6r9d40dlY/SnPpMcNter+WZUGYe4ym0jlK/NT7eGOm/U1Sarvfye8D9ZAOkNM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706541572; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=r+KuOhvBtJ6ncQuNPO3pijGi7HTXapiP3L5g0Ir3MJk=; b=SDAJ38gKNa3+Dl765vGCPARKZ06JNAwf79dHP3tL0RFmhJ2CLgjdjihwXSMmu+PSB/EI1nfBHnMogfXYILBe2o6MKxD4eETxw8uNBtuRNe5wmJPpfo3xjePLNdwcWmgoiZnnNtLNADt4y5UOt7YhPNx2WYsLAyxhkrVJc2NqHwI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706541572596286.7329096226226; Mon, 29 Jan 2024 07:19:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUTPY-0007VQ-UQ; Mon, 29 Jan 2024 10:19:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUTPL-0007He-7E for qemu-devel@nongnu.org; Mon, 29 Jan 2024 10:18:47 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUTPJ-0007R9-Lq for qemu-devel@nongnu.org; Mon, 29 Jan 2024 10:18:46 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-33926ccbc80so1804778f8f.0 for ; Mon, 29 Jan 2024 07:18:45 -0800 (PST) Received: from m1x-phil.lan ([176.187.219.39]) by smtp.gmail.com with ESMTPSA id bs14-20020a056000070e00b0033aeba36b7csm3661786wrb.57.2024.01.29.07.18.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Jan 2024 07:18:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706541524; x=1707146324; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r+KuOhvBtJ6ncQuNPO3pijGi7HTXapiP3L5g0Ir3MJk=; b=R4kZi0YQ+OmsBqq0ExBud+W+VOfWZjR8vOe2UAXGyPNZwkJRKEdoC9GQbZcW26Fk24 qK0KPhV0KT7Mt20IqiG5b/gUdMKT3YmagLCx84goOTr30Ktn21PSYB7HcHHbaXYSayX2 497ugYmH8bRSfU319pjqB7e1j7rXaK9RRfA5siB7GwI92s9w2iUskQ8hXWDvdHUgXS0l Ah+NY1kNpmmxtumPPXwoa/g7wzOELrVgNSCVJNLXJ6FezLV3XRYacazV7WaMhiAMmv2H dL+0jYh58+YQ4UlDzuyzOZ+yZRJq/ut1Pdz1oiLl4L/yOqA5RTiDewDXtVNEhp495TQ+ PjJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706541524; x=1707146324; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r+KuOhvBtJ6ncQuNPO3pijGi7HTXapiP3L5g0Ir3MJk=; b=pW0geze4a0muR3/Hu7xKRruLG50qcQaedMk5TruywrclU5+9vnDpo3QhflyaxJmJAB ra+njZ5esHr23zVjBfbS+pRJXZSIR/XIot1nZTbh8b3vUfD1VNam4xyFjJ2f3GaoNrvj DSe8rDFpq9Is9g5CjGf/NfdmXP3TcfY5WQL/fmgeUZJJrwm0e5SkSPfKcexTIWRKESIo iGjvVKMxibUc/L4IxFFx2Bveb7ury3nu5eTThS81FDcu3VaGFZEBAYQ8LTckswuy8Bi/ 0BIGPSA2fEtl/Ey650ZguxAGUL3+DW5vvoYjZIxgGlmE4nQAc6KbMe+cgbcXChSmBhpl i4GA== X-Gm-Message-State: AOJu0Yw6a1+5Rs30NWW1QBRbwwUKqMsQ6CjSF9UljtZip7KEe6EgSd/R EDobqNtDfOwd11c/mAUWH/6FuehfJTxlYGzxLdBhGUqZO1FWbcKcFwqPqyiMIM4XtsB6dDyYYNC Z X-Google-Smtp-Source: AGHT+IEeODkxxpbrCPljFNWp1VHM8RuudqPMG2/D1j2eRJm7r3D1RA1bzUyhPy5F55qoCSDy8cpa7A== X-Received: by 2002:a05:6000:184d:b0:33a:f2a8:fcc4 with SMTP id c13-20020a056000184d00b0033af2a8fcc4mr1572589wri.59.1706541523722; Mon, 29 Jan 2024 07:18:43 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Tyrone Ting , Subbaraya Sundeep , Alistair Francis , Igor Mitsyanko , Hao Wu , "Edgar E. Iglesias" , Peter Maydell , Rob Herring , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PATCH v3 2/9] hw/arm/exynos: Check for CPU types in machine_run_board_init() Date: Mon, 29 Jan 2024 16:18:21 +0100 Message-ID: <20240129151828.59544-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706541575119100013 Restrict MachineClass::valid_cpu_types[] to the single valid CPU type. Instead of ignoring invalid CPU type requested by the user: $ qemu-system-arm -M nuri -cpu cortex-a7 -S -monitor stdio QEMU 8.2.50 monitor - type 'help' for more information (qemu) info qom-tree /machine (nuri-machine) /soc (exynos4210) /cpu[0] (cortex-a9-arm-cpu) ... We now display an error: $ qemu-system-arm -M nuri -cpu cortex-a7 qemu-system-arm: Invalid CPU model: cortex-a7 The only valid type is: cortex-a9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan --- hw/arm/exynos4_boards.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index b0e13eb4f0..01c7618a67 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -34,6 +34,7 @@ #include "hw/qdev-properties.h" #include "hw/boards.h" #include "hw/irq.h" +#include "target/arm/cpu-qom.h" =20 #define SMDK_LAN9118_BASE_ADDR 0x05000000 =20 @@ -150,12 +151,18 @@ static void smdkc210_init(MachineState *machine) arm_load_kernel(s->soc.cpu[0], machine, &exynos4_board_binfo); } =20 +static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a9"), + NULL +}; + static void nuri_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "Samsung NURI board (Exynos4210)"; mc->init =3D nuri_init; + mc->valid_cpu_types =3D valid_cpu_types; mc->max_cpus =3D EXYNOS4210_NCPUS; mc->min_cpus =3D EXYNOS4210_NCPUS; mc->default_cpus =3D EXYNOS4210_NCPUS; @@ -174,6 +181,7 @@ static void smdkc210_class_init(ObjectClass *oc, void *= data) =20 mc->desc =3D "Samsung SMDKC210 board (Exynos4210)"; mc->init =3D smdkc210_init; + mc->valid_cpu_types =3D valid_cpu_types; mc->max_cpus =3D EXYNOS4210_NCPUS; mc->min_cpus =3D EXYNOS4210_NCPUS; mc->default_cpus =3D EXYNOS4210_NCPUS; --=20 2.41.0 From nobody Tue Nov 26 15:16:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706541662; cv=none; d=zohomail.com; s=zohoarc; b=dFYWhZgbS3wb6zxjqZUXNdJ/eEp8q+jc6uDAxqZmIHPYHuxT0T52bMgczjpnnJF05pl+KZuoKJBkO3tP0aHTgHW0PHD0Q8VgAJxQBX1oyJCRrd1oOzhuHtzSictWeXkLlp3LiwXgM19AbFxMG0WrQDQx/VUfmxKZG/lR010OObA= ARC-Message-Signature: i=1; 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Mon, 29 Jan 2024 07:18:49 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Tyrone Ting , Subbaraya Sundeep , Alistair Francis , Igor Mitsyanko , Hao Wu , "Edgar E. Iglesias" , Peter Maydell , Rob Herring , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PATCH v3 3/9] hw/arm/highbank: Add missing QOM parent for CPU cores Date: Mon, 29 Jan 2024 16:18:22 +0100 Message-ID: <20240129151828.59544-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706541663163100001 QDev objects created with qdev_new() need to manually add their parent relationship with object_property_add_child(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan --- hw/arm/highbank.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index e6e27d69af..b8d702c82c 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -209,6 +209,7 @@ static void calxeda_init(MachineState *machine, enum cx= machines machine_id) cpuobj =3D object_new(machine->cpu_type); cpu =3D ARM_CPU(cpuobj); =20 + object_property_add_child(OBJECT(machine), "cpu[*]", cpuobj); object_property_set_int(cpuobj, "psci-conduit", QEMU_PSCI_CONDUIT_= SMC, &error_abort); =20 --=20 2.41.0 From nobody Tue Nov 26 15:16:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706541672; 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Iglesias" , Peter Maydell , Rob Herring , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PATCH v3 4/9] hw/arm/highbank: Check for CPU types in machine_run_board_init() Date: Mon, 29 Jan 2024 16:18:23 +0100 Message-ID: <20240129151828.59544-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philmd@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706541673204100001 Restrict MachineClass::valid_cpu_types[] to the single valid CPU types. Instead of ignoring invalid CPU type requested by the user: $ qemu-system-arm -M midway -cpu cortex-a7 -S -monitor stdio QEMU 8.2.50 monitor - type 'help' for more information (qemu) info qom-tree /machine (midway-machine) /cpu[0] (cortex-a15-arm-cpu) ... we now display an error: $ qemu-system-arm -M midway -cpu cortex-a7 qemu-system-arm: Invalid CPU model: cortex-a7 The only valid type is: cortex-a15 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan --- hw/arm/highbank.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index b8d702c82c..0367050697 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -345,10 +345,15 @@ static void midway_init(MachineState *machine) =20 static void highbank_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a9"), + NULL + }; MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "Calxeda Highbank (ECX-1000)"; mc->init =3D highbank_init; + mc->valid_cpu_types =3D valid_cpu_types; mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; mc->max_cpus =3D 4; @@ -364,10 +369,15 @@ static const TypeInfo highbank_type =3D { =20 static void midway_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a15"), + NULL + }; MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "Calxeda Midway (ECX-2000)"; mc->init =3D midway_init; + mc->valid_cpu_types =3D valid_cpu_types; mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; mc->max_cpus =3D 4; --=20 2.41.0 From nobody Tue Nov 26 15:16:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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Iglesias" , Peter Maydell , Rob Herring , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v3 5/9] hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[] Date: Mon, 29 Jan 2024 16:18:24 +0100 Message-ID: <20240129151828.59544-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706541653177100001 The M2Sxxx SoC family can only be used with Cortex-M3. Propagating the CPU type from the board level is pointless. Hard-code the CPU type at the SoC level. Remove the now ignored MachineClass::default_cpu_type field. Use the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for valid CPU type at the board level. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/msf2-soc.h | 3 --- hw/arm/msf2-soc.c | 3 +-- hw/arm/msf2-som.c | 4 ---- 3 files changed, 1 insertion(+), 9 deletions(-) diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h index ce417a6266..9300664e8e 100644 --- a/include/hw/arm/msf2-soc.h +++ b/include/hw/arm/msf2-soc.h @@ -47,13 +47,10 @@ OBJECT_DECLARE_SIMPLE_TYPE(MSF2State, MSF2_SOC) #define MSF2_NUM_TIMERS 2 =20 struct MSF2State { - /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ =20 ARMv7MState armv7m; =20 - char *cpu_type; char *part_name; uint64_t envm_size; uint64_t esram_size; diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index b5fe9f364d..d6eb9ec9ac 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -134,7 +134,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Er= ror **errp) =20 armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 81); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"= )); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->m3clk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -231,7 +231,6 @@ static Property m2sxxx_soc_properties[] =3D { * part name specifies the type of SmartFusion2 device variant(this * property is for information purpose only. */ - DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type), DEFINE_PROP_STRING("part-name", MSF2State, part_name), DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SI= ZE), DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index a269cf044b..5c415abe85 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -47,7 +47,6 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) DeviceState *dev; DeviceState *spi_flash; MSF2State *soc; - MachineClass *mc =3D MACHINE_GET_CLASS(machine); DriveInfo *dinfo =3D drive_get(IF_MTD, 0, 0); qemu_irq cs_line; BusState *spi_bus; @@ -62,8 +61,6 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) dev =3D qdev_new(TYPE_MSF2_SOC); object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); qdev_prop_set_string(dev, "part-name", "M2S010"); - qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type); - qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE); qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE); =20 @@ -108,7 +105,6 @@ static void emcraft_sf2_machine_init(MachineClass *mc) =20 mc->desc =3D "SmartFusion2 SOM kit from Emcraft (M2S010)"; mc->init =3D emcraft_sf2_s2s010_init; - mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m3"); mc->valid_cpu_types =3D valid_cpu_types; } =20 --=20 2.41.0 From nobody Tue Nov 26 15:16:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Iglesias" , Peter Maydell , Rob Herring , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v3 6/9] hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[] Date: Mon, 29 Jan 2024 16:18:25 +0100 Message-ID: <20240129151828.59544-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706541617039100001 Musca boards use the embedded subsystems (SSE) tied to a specific Cortex core. Our models only use the Cortex-M33. Use the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for valid CPU type at the board level. Remove the now unused MachineClass::default_cpu_type field. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/musca.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 770ec1a15c..e2c9d49af5 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -605,7 +605,6 @@ static void musca_class_init(ObjectClass *oc, void *dat= a) mc->default_cpus =3D 2; mc->min_cpus =3D mc->default_cpus; mc->max_cpus =3D mc->default_cpus; - mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); mc->valid_cpu_types =3D valid_cpu_types; mc->init =3D musca_init; } --=20 2.41.0 From nobody Tue Nov 26 15:16:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706541572; cv=none; d=zohomail.com; s=zohoarc; b=MD4T14bfvnIIkMCBtUfxtt/SCBmIGUBAaY2VCZKhLmayJYV1sqsZNaYQt7ogYFO0fAbE09m2qoWsNc+TxxtwzZWlYg44CBK31f2dtl3lf9isZTddtSvK7KlS6No8a3SHYKls0WbUWxOJC92b6ZyOofLYwcCDgWkBtJHO//jZ6tc= ARC-Message-Signature: i=1; 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Mon, 29 Jan 2024 07:19:15 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Tyrone Ting , Subbaraya Sundeep , Alistair Francis , Igor Mitsyanko , Hao Wu , "Edgar E. Iglesias" , Peter Maydell , Rob Herring , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v3 7/9] hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[] Date: Mon, 29 Jan 2024 16:18:26 +0100 Message-ID: <20240129151828.59544-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=philmd@linaro.org; helo=mail-lf1-x130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706541575114100011 The npcm7xx Soc is created with a Cortex-A9 core, see in hw/arm/npcm7xx.c: static void npcm7xx_init(Object *obj) { NPCM7xxState *s =3D NPCM7XX(obj); for (int i =3D 0; i < NPCM7XX_MAX_NUM_CPUS; i++) { object_initialize_child(obj, "cpu[*]", &s->cpu[i], ARM_CPU_TYPE_NAME("cortex-a9")); } The MachineClass::default_cpu_type field is ignored: delete it. Use the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for valid CPU type at the board level. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/npcm7xx_boards.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 2999b8b96d..e229efb447 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -465,7 +465,6 @@ static void npcm7xx_machine_class_init(ObjectClass *oc,= void *data) mc->no_cdrom =3D 1; mc->no_parallel =3D 1; mc->default_ram_id =3D "ram"; - mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a9"); mc->valid_cpu_types =3D valid_cpu_types; } =20 --=20 2.41.0 From nobody Tue Nov 26 15:16:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706541587; cv=none; d=zohomail.com; s=zohoarc; b=Vz3QT6uYjigYzELwfQcgcGwnFFkl/sud/0A5W9LqWHRkemNF3VInSp/t8X9ngPsMxGaqurgw9iMnt/RjgWF6OkFcX7i+QfVZeLOIws/IIuBsey9axO78u64oqTm5/4XAjaxEuZkysBvcw6NSlMjdXh1LQ2uAAbF58pfHEZin3hs= ARC-Message-Signature: i=1; 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Mon, 29 Jan 2024 07:19:20 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Tyrone Ting , Subbaraya Sundeep , Alistair Francis , Igor Mitsyanko , Hao Wu , "Edgar E. Iglesias" , Peter Maydell , Rob Herring , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PATCH v3 8/9] hw/arm/vexpress: Check for CPU types in machine_run_board_init() Date: Mon, 29 Jan 2024 16:18:27 +0100 Message-ID: <20240129151828.59544-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706541588890100003 Leverage the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for the single valid CPU type. Remove the now unused MachineClass::default_cpu_type field. Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/vexpress.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index f1b45245d5..1a14c1933e 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -783,22 +783,30 @@ static void vexpress_class_init(ObjectClass *oc, void= *data) =20 static void vexpress_a9_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a9"), + NULL + }; MachineClass *mc =3D MACHINE_CLASS(oc); VexpressMachineClass *vmc =3D VEXPRESS_MACHINE_CLASS(oc); =20 mc->desc =3D "ARM Versatile Express for Cortex-A9"; - mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a9"); + mc->valid_cpu_types =3D valid_cpu_types; =20 vmc->daughterboard =3D &a9_daughterboard; } =20 static void vexpress_a15_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a15"), + NULL + }; MachineClass *mc =3D MACHINE_CLASS(oc); VexpressMachineClass *vmc =3D VEXPRESS_MACHINE_CLASS(oc); =20 mc->desc =3D "ARM Versatile Express for Cortex-A15"; - mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a15"); + mc->valid_cpu_types =3D valid_cpu_types; =20 vmc->daughterboard =3D &a15_daughterboard; =20 --=20 2.41.0 From nobody Tue Nov 26 15:16:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706541616; cv=none; d=zohomail.com; s=zohoarc; b=XkCCd3fTVAuOWZcV9RG9q8aCCvKYJ7/IYJwOgrtXNA2lMaqpNwwfMoeZyAidy+Xoj1FRFqVuuSYAHSiJU2mh380Tx4t8ub8/QM4x1FOHSpGom8Qj9kxWLPjNWAErX/2ZsAxe2tnSR0fFQt5nv8F2ohpo4KdmPZPAkPOLUigDVek= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706541616; 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Mon, 29 Jan 2024 07:19:26 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Tyrone Ting , Subbaraya Sundeep , Alistair Francis , Igor Mitsyanko , Hao Wu , "Edgar E. Iglesias" , Peter Maydell , Rob Herring , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PATCH v3 9/9] hw/arm/zynq: Check for CPU types in machine_run_board_init() Date: Mon, 29 Jan 2024 16:18:28 +0100 Message-ID: <20240129151828.59544-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706541617044100002 Leverage the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for the single valid CPU type. Remove the now unused MachineClass::default_cpu_type field. Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/xilinx_zynq.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 66d0de139f..c57bbccb70 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -355,13 +355,17 @@ static void zynq_init(MachineState *machine) =20 static void zynq_machine_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a9"), + NULL + }; MachineClass *mc =3D MACHINE_CLASS(oc); mc->desc =3D "Xilinx Zynq Platform Baseboard for Cortex-A9"; mc->init =3D zynq_init; mc->max_cpus =3D 1; mc->no_sdcard =3D 1; mc->ignore_memory_transaction_failures =3D true; - mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a9"); + mc->valid_cpu_types =3D valid_cpu_types; mc->default_ram_id =3D "zynq.ext_ram"; } =20 --=20 2.41.0