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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706417004; x=1707021804; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fDrlqZJJ0WFNjsqbAt49Vqu9oOvOnIDnuEZmci/Hrlo=; b=G3thYD7Hi0FxzXc24i5PY6XCFBTwwssQngC59XDGDBDBoEVmM9DhxFVOlwgPRZGhiP VQ35llQ3vprFPLI+3y6wMREzePkL5YlZRYrLTx8pWo5L4jvLSqVhuw0dRNz7hNqQYkDX 9BawaxutgHSVqLS2Q/OwxPGQfW+EX1lOvTp1tAmhzpsYfsVFvcYGv8gDoARPBu3a0SZL KtZWJE12610xN4HE9X7taDJWuQF4yUtmlv3cvHoq6hfuAtdEc2d86kQcuptbp93UV6tG yr+6qJ+wahGT/rDmLsVgW0jXVVf1YsAGyCJ9s2WuyUKEy3tDuTkF9RNq/bko7ncCmjum Gtkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706417004; x=1707021804; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fDrlqZJJ0WFNjsqbAt49Vqu9oOvOnIDnuEZmci/Hrlo=; b=Vjt7CGLPJNKETmhnAuHQROUQgqJ5xUWvDquKxD0P4x/z2c2g6U7+A0gpbT8h71+9qZ CtLbJxqp9BZUks/ci+FvfVqCh5c2D6E2t+/bjLAw2Url5yjtZQA+LiHtmtzPKVC5W4vm 0JWQvSXbmmXdE28lXoHwfBS6IW2Crh+yd+tSfgp/w4OrK+PUWCQQcbSvwmXnlk+va3e/ n2qo2QnymJkvGenwrp/Xoq/1AA4WfH+pHAbJSLhSnENzK3kPeKg/BfUC07F408btS8Gr y7/wMe5fw/VeXZ4ewph3r4ZQ3tD0V+M0GAA7/4OFLmgiYvi0RYlneJ5XRUC+djpRlQlK eR/Q== X-Gm-Message-State: AOJu0Ywm78qi1986TPTVMupVYzRJxKgdNyW1cGAHFF72VtwDkpnDKgPG uIH8JZu/mgiFrzzzq2yqqBpsHiURcUscFqXPg+BT5IqlH5FTQNkSFHqQ0mQRLgUHt6PcQcNzaFW J3oQXcg== X-Google-Smtp-Source: AGHT+IHLORWmHjOGBfVxW2ppm2CRKT4gXuHf6Zzm/QGW1hmYU8Ci1BeVSt5LgdYNFh56Rntddnp8RA== X-Received: by 2002:a17:903:41c8:b0:1d8:d3e8:c31c with SMTP id u8-20020a17090341c800b001d8d3e8c31cmr246672ple.105.1706417003986; Sat, 27 Jan 2024 20:43:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 26/33] include/qemu: Add TCGCPUOps typedef to typedefs.h Date: Sun, 28 Jan 2024 14:42:06 +1000 Message-Id: <20240128044213.316480-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417172931100001 Content-Type: text/plain; charset="utf-8" QEMU coding style recommends using structure typedefs. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 5 +---- include/qemu/typedefs.h | 1 + bsd-user/signal.c | 4 ++-- linux-user/signal.c | 4 ++-- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/arm/tcg/cpu32.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 4 ++-- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 26 files changed, 29 insertions(+), 31 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index db58f12233..2c284d6397 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -90,9 +90,6 @@ typedef enum MMUAccessType { =20 typedef struct CPUWatchpoint CPUWatchpoint; =20 -/* see tcg-cpu-ops.h */ -struct TCGCPUOps; - /* see accel-cpu.h */ struct AccelCPUClass; =20 @@ -177,7 +174,7 @@ struct CPUClass { const struct SysemuCPUOps *sysemu_ops; =20 /* when TCG is not available, this pointer is NULL */ - const struct TCGCPUOps *tcg_ops; + const TCGCPUOps *tcg_ops; =20 /* * if not NULL, this is called in order for the CPUClass to initialize diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 5abdbc3874..d7c703b4ae 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -131,6 +131,7 @@ typedef struct Range Range; typedef struct ReservedRegion ReservedRegion; typedef struct SHPCDevice SHPCDevice; typedef struct SSIBus SSIBus; +typedef struct TCGCPUOps TCGCPUOps; typedef struct TCGHelperInfo TCGHelperInfo; typedef struct TranslationBlock TranslationBlock; typedef struct VirtIODevice VirtIODevice; diff --git a/bsd-user/signal.c b/bsd-user/signal.c index ca31470772..f4352e4530 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -1022,7 +1022,7 @@ void process_pending_signals(CPUArchState *env) void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, MMUAccessType access_type, bool maperr, uintptr= _t ra) { - const struct TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; =20 if (tcg_ops->record_sigsegv) { tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); @@ -1038,7 +1038,7 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulon= g addr, void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, MMUAccessType access_type, uintptr_t ra) { - const struct TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; =20 if (tcg_ops->record_sigbus) { tcg_ops->record_sigbus(cpu, addr, access_type, ra); diff --git a/linux-user/signal.c b/linux-user/signal.c index c9527adfa3..d3e62ab030 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -671,7 +671,7 @@ void force_sigsegv(int oldsig) void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, MMUAccessType access_type, bool maperr, uintptr= _t ra) { - const struct TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; =20 if (tcg_ops->record_sigsegv) { tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); @@ -687,7 +687,7 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong = addr, void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, MMUAccessType access_type, uintptr_t ra) { - const struct TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; =20 if (tcg_ops->record_sigbus) { tcg_ops->record_sigbus(cpu, addr, access_type, ra); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index ce20a56270..80760be0f3 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -222,7 +222,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps alpha_tcg_ops =3D { +static const TCGCPUOps alpha_tcg_ops =3D { .initialize =3D alpha_translate_init, .restore_state_to_opc =3D alpha_restore_state_to_opc, =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0ee9a879f0..e050928598 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2456,7 +2456,7 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D { #endif =20 #ifdef CONFIG_TCG -static const struct TCGCPUOps arm_tcg_ops =3D { +static const TCGCPUOps arm_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, .debug_excp_handler =3D arm_debug_excp_handler, diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index d9e0e2a4dd..1125305115 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -1018,7 +1018,7 @@ static void pxa270c5_initfn(Object *obj) cpu->reset_sctlr =3D 0x00000078; } =20 -static const struct TCGCPUOps arm_v7m_tcg_ops =3D { +static const TCGCPUOps arm_v7m_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, .debug_excp_handler =3D arm_debug_excp_handler, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 76dbe56284..41ff121d20 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -233,7 +233,7 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps avr_tcg_ops =3D { +static const TCGCPUOps avr_tcg_ops =3D { .initialize =3D avr_cpu_tcg_init, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, .restore_state_to_opc =3D avr_restore_state_to_opc, diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 6512ef8ee2..93f26542d8 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -192,7 +192,7 @@ static const struct SysemuCPUOps cris_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps crisv10_tcg_ops =3D { +static const TCGCPUOps crisv10_tcg_ops =3D { .initialize =3D cris_initialize_crisv10_tcg, .restore_state_to_opc =3D cris_restore_state_to_opc, =20 @@ -203,7 +203,7 @@ static const struct TCGCPUOps crisv10_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 -static const struct TCGCPUOps crisv32_tcg_ops =3D { +static const TCGCPUOps crisv32_tcg_ops =3D { .initialize =3D cris_initialize_tcg, .restore_state_to_opc =3D cris_restore_state_to_opc, =20 diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index b2bbb21b59..49f05eae99 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -358,7 +358,7 @@ static void hexagon_cpu_init(Object *obj) =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps hexagon_tcg_ops =3D { +static const TCGCPUOps hexagon_tcg_ops =3D { .initialize =3D hexagon_translate_init, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, .restore_state_to_opc =3D hexagon_restore_state_to_opc, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 2cc8e43b33..2d98082306 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -225,7 +225,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps hppa_tcg_ops =3D { +static const TCGCPUOps hppa_tcg_ops =3D { .initialize =3D hppa_translate_init, .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, .restore_state_to_opc =3D hppa_restore_state_to_opc, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index e1405b7be9..8e148e9bc4 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -106,7 +106,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps x86_tcg_ops =3D { +static const TCGCPUOps x86_tcg_ops =3D { .initialize =3D tcg_x86_init, .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, .restore_state_to_opc =3D x86_restore_state_to_opc, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ea4281e177..d9ddab5b9a 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -758,7 +758,7 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, in= t flags) #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 -static struct TCGCPUOps loongarch_tcg_ops =3D { +static TCGCPUOps loongarch_tcg_ops =3D { .initialize =3D loongarch_translate_init, .synchronize_from_tb =3D loongarch_cpu_synchronize_from_tb, .restore_state_to_opc =3D loongarch_restore_state_to_opc, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index f9dc447897..288140c986 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -546,7 +546,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps m68k_tcg_ops =3D { +static const TCGCPUOps m68k_tcg_ops =3D { .initialize =3D m68k_tcg_init, .restore_state_to_opc =3D m68k_restore_state_to_opc, =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4c270e941f..171937564d 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -410,7 +410,7 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps mb_tcg_ops =3D { +static const TCGCPUOps mb_tcg_ops =3D { .initialize =3D mb_tcg_init, .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, .restore_state_to_opc =3D mb_restore_state_to_opc, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 4c3e1ec2d9..dfe82f93ef 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -563,7 +563,7 @@ static const struct SysemuCPUOps mips_sysemu_ops =3D { * NB: cannot be const, as some elements are changed for specific * mips hardware (see hw/mips/jazz.c). */ -static const struct TCGCPUOps mips_tcg_ops =3D { +static const TCGCPUOps mips_tcg_ops =3D { .initialize =3D mips_tcg_init, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, .restore_state_to_opc =3D mips_restore_state_to_opc, diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 3e42889ce6..bff35f835a 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -372,7 +372,7 @@ static const struct SysemuCPUOps nios2_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps nios2_tcg_ops =3D { +static const TCGCPUOps nios2_tcg_ops =3D { .initialize =3D nios2_tcg_init, .restore_state_to_opc =3D nios2_restore_state_to_opc, =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index fda0dc9470..bc54e7ccd0 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -235,7 +235,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps openrisc_tcg_ops =3D { +static const TCGCPUOps openrisc_tcg_ops =3D { .initialize =3D openrisc_translate_init, .synchronize_from_tb =3D openrisc_cpu_synchronize_from_tb, .restore_state_to_opc =3D openrisc_restore_state_to_opc, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 344196a8ce..23eb5522b6 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7332,7 +7332,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps ppc_tcg_ops =3D { +static const TCGCPUOps ppc_tcg_ops =3D { .initialize =3D ppc_translate_init, .restore_state_to_opc =3D ppc_restore_state_to_opc, =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 994ca1cdf9..b7da92783b 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -129,7 +129,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, env->bins =3D data[1]; } =20 -static const struct TCGCPUOps riscv_tcg_ops =3D { +static const TCGCPUOps riscv_tcg_ops =3D { .initialize =3D riscv_translate_init, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, .restore_state_to_opc =3D riscv_restore_state_to_opc, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index de1cc7a5e6..cfc97d06e7 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -192,7 +192,7 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps rx_tcg_ops =3D { +static const TCGCPUOps rx_tcg_ops =3D { .initialize =3D rx_translate_init, .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, .restore_state_to_opc =3D rx_restore_state_to_opc, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index db1590472e..b783e1e2e6 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -372,7 +372,7 @@ static void s390_cpu_reset_full(DeviceState *dev) #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps s390_tcg_ops =3D { +static const TCGCPUOps s390_tcg_ops =3D { .initialize =3D s390x_translate_init, .restore_state_to_opc =3D s390x_restore_state_to_opc, =20 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index eb7eb6f30a..89a42e0e22 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -265,7 +265,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps superh_tcg_ops =3D { +static const TCGCPUOps superh_tcg_ops =3D { .initialize =3D sh4_translate_init, .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, .restore_state_to_opc =3D superh_restore_state_to_opc, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 99d57cc209..8385c8a2b0 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -935,7 +935,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops =3D { #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps sparc_tcg_ops =3D { +static const TCGCPUOps sparc_tcg_ops =3D { .initialize =3D sparc_tcg_init, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, .restore_state_to_opc =3D sparc_restore_state_to_opc, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index dff88184c9..2f07fdbfab 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -190,7 +190,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops =3D= { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps tricore_tcg_ops =3D { +static const TCGCPUOps tricore_tcg_ops =3D { .initialize =3D tricore_tcg_init, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, .restore_state_to_opc =3D tricore_restore_state_to_opc, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index dfe0ff5c98..0da5409742 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -294,7 +294,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps xtensa_tcg_ops =3D { +static const TCGCPUOps xtensa_tcg_ops =3D { .initialize =3D xtensa_translate_init, .debug_excp_handler =3D xtensa_breakpoint_handler, .restore_state_to_opc =3D xtensa_restore_state_to_opc, --=20 2.34.1