From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417147; cv=none; d=zohomail.com; s=zohoarc; b=JiTmv9HCEzQ5Hx6saVLbzYjTmjtHJj8pam95EqMnwAT0baKYJHZ1VMkl5Yq83xMtRua47Ov2+TWfXo+GS/aP+kroJM9N0KUK7jhBlYcsTsNZjncr2kXvBn+/605VsdF6HOAqJnDl//VClZy6SJ9EWlBwhSgUg0kawpNDOVHWG/w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417147; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qYS/soxWe3h+ML5uFbbfcdAcoE+eOI+G62ajUSGtp3A=; b=BxCKSYxu+4w5aj5vI9rvShAUYu6HS8+OssMvIXU59afX9KVOtKd4lq3dHexbJhNBld+L13UewkdEtkXm7hwe5Ddo0oKys26tX2//NRDEl24Em8NtVs4awWCsqUbyHEZh+hVG6cMf0AK4tR6dzmEGiJDYBzDV+6inF4PzBrpcBV0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170641714755813.610217417057015; Sat, 27 Jan 2024 20:45:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTwzy-0004dm-J7; Sat, 27 Jan 2024 23:42:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTwzx-0004de-CD for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:25 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTwzv-0004FP-CV for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:25 -0500 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1d8a66a2976so16568165ad.2 for ; Sat, 27 Jan 2024 20:42:23 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416942; x=1707021742; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qYS/soxWe3h+ML5uFbbfcdAcoE+eOI+G62ajUSGtp3A=; b=NV03rp4b5mca3d5+wtx2dlG+sEm8M5fPIhm0xpVxRB2sT0bV1gHbxeS1Kg1HUMamv4 KmzLSZQ2TSwcN8cPt13X3hpUTAjLJgG5DKMQOlkg/9nIaV7ozNoLmW3PGPWdyU+3shKW VoHTbxYISyx6yukFYNynYfpcTpMGkm9Iule9rfdS0bk+X3Hu/TaFH4UqFwWkZESXcUBr YbxMfGffC3f6grFvu7qHxbFKXVhDNWuZG4zODVWfQ9fRGv3CGILQX651QOuQyMz5lXKP HPFhxD6yI7D5VFbECD64Ond0r9/G0J72KOtq8saRUVsMju7Nbh9Z40M27NDT+ts0mVEZ XQdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416942; x=1707021742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qYS/soxWe3h+ML5uFbbfcdAcoE+eOI+G62ajUSGtp3A=; b=HB/e4ZDDITxowWQGGaBPmk31/mUOUBJW93Dn5u3nQkug679cjUzAYWatzeIUh1O8iL Jxu/OIeAKCM2Ptc+QoXBxZqdi3eWanP+k23/3qHepHvhNT2LIsGD9VLtRneZz0miqYIi ryaPRl+Ds6LHAOoxJ1F06PvyBUKVAoScjnfWMyL+uOUYxJzT23DJoYbgiMk6ewVAVCJR el4LPtDrdKdHG14RRyEZexLnOccegx0BXDHy8tXDmU07Uct3A3+WBt+HqBD1Z+YDVRVE 02CYU9XGfAgmedlukWU5Gf10Y0KVy93F0lQsVhjynJa6tLWuyh102S03zfw1qNjhODzD pGmg== X-Gm-Message-State: AOJu0YzF3nPV5rEoQi7JuwpvPXfH2DZr6BXWBsKvyUr9BS+TxdfY8s+Z 6Oa28IZGQrB9zxJaRVLlfDRHY0PovXnWohVq+2+kF1o1sKN//BmVzwds1rZrLD8mvL3O5zPNxXo iUdA= X-Google-Smtp-Source: AGHT+IEtpG0xYW2IvKMcsCluwn6z8i/pAYdzzp3E1QPXpfLDngjMOcm0qyzKJzji3XignqEFUT3dDw== X-Received: by 2002:a17:902:e84b:b0:1d8:d71b:8801 with SMTP id t11-20020a170902e84b00b001d8d71b8801mr119288plg.54.1706416941824; Sat, 27 Jan 2024 20:42:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 01/33] cpu-exec: simplify jump cache management Date: Sun, 28 Jan 2024 14:41:41 +1000 Message-Id: <20240128044213.316480-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417148869100004 From: Paolo Bonzini Unless I'm missing something egregious, the jmp cache is only every populated with a valid entry by the same thread that reads the cache. Therefore, the contents of any valid entry are always consistent and there is no need for any acquire/release magic. Indeed ->tb has to be accessed with atomics, because concurrent invalidations would otherwise cause data races. But ->pc is only ever accessed by one thread, and accesses to ->tb and ->pc within tb_lookup can never race with another tb_lookup. While the TranslationBlock (especially the flags) could be modified by a concurrent invalidation, store-release and load-acquire operations on the cache entry would not add any additional ordering beyond what you get from performing the accesses within a single thread. Because of this, there is really nothing to win in splitting the CF_PCREL and !CF_PCREL paths. It is easier to just always use the ->pc field in the jump cache. I noticed this while working on splitting commit 8ed558ec0cb ("accel/tcg: Introduce TARGET_TB_PCREL", 2022-10-04) into multiple pieces, for the sake of finding a more fine-grained bisection result for https://gitlab.com/qemu-project/qemu/-/issues/2092. It does not (and does not intend to) fix that issue; therefore it may make sense to not commit it until the root cause of issue #2092 is found. Signed-off-by: Paolo Bonzini Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-Id: <20240122153409.351959-1-pbonzini@redhat.com> Signed-off-by: Richard Henderson --- accel/tcg/tb-jmp-cache.h | 8 +++-- accel/tcg/cpu-exec.c | 66 ++++++++++++++-------------------------- 2 files changed, 28 insertions(+), 46 deletions(-) diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h index bb424c8a05..4ab8553afc 100644 --- a/accel/tcg/tb-jmp-cache.h +++ b/accel/tcg/tb-jmp-cache.h @@ -13,9 +13,11 @@ #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) =20 /* - * Accessed in parallel; all accesses to 'tb' must be atomic. - * For CF_PCREL, accesses to 'pc' must be protected by a - * load_acquire/store_release to 'tb'. + * Invalidated in parallel; all accesses to 'tb' must be atomic. + * A valid entry is read/written by a single CPU, therefore there is + * no need for qatomic_rcu_read() and pc is always consistent with a + * non-NULL value of 'tb'. Strictly speaking pc is only needed for + * CF_PCREL, but it's used always for simplicity. */ struct CPUJumpCache { struct rcu_head rcu; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 67eda9865e..40c268bfa1 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -253,43 +253,29 @@ static inline TranslationBlock *tb_lookup(CPUState *c= pu, vaddr pc, hash =3D tb_jmp_cache_hash_func(pc); jc =3D cpu->tb_jmp_cache; =20 - if (cflags & CF_PCREL) { - /* Use acquire to ensure current load of pc from jc. */ - tb =3D qatomic_load_acquire(&jc->array[hash].tb); - - if (likely(tb && - jc->array[hash].pc =3D=3D pc && - tb->cs_base =3D=3D cs_base && - tb->flags =3D=3D flags && - tb_cflags(tb) =3D=3D cflags)) { - return tb; - } - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cflags); - if (tb =3D=3D NULL) { - return NULL; - } - jc->array[hash].pc =3D pc; - /* Ensure pc is written first. */ - qatomic_store_release(&jc->array[hash].tb, tb); - } else { - /* Use rcu_read to ensure current load of pc from *tb. */ - tb =3D qatomic_rcu_read(&jc->array[hash].tb); - - if (likely(tb && - tb->pc =3D=3D pc && - tb->cs_base =3D=3D cs_base && - tb->flags =3D=3D flags && - tb_cflags(tb) =3D=3D cflags)) { - return tb; - } - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cflags); - if (tb =3D=3D NULL) { - return NULL; - } - /* Use the pc value already stored in tb->pc. */ - qatomic_set(&jc->array[hash].tb, tb); + tb =3D qatomic_read(&jc->array[hash].tb); + if (likely(tb && + jc->array[hash].pc =3D=3D pc && + tb->cs_base =3D=3D cs_base && + tb->flags =3D=3D flags && + tb_cflags(tb) =3D=3D cflags)) { + goto hit; } =20 + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cflags); + if (tb =3D=3D NULL) { + return NULL; + } + + jc->array[hash].pc =3D pc; + qatomic_set(&jc->array[hash].tb, tb); + +hit: + /* + * As long as tb is not NULL, the contents are consistent. Therefore, + * the virtual PC has to match for non-CF_PCREL translations. + */ + assert((tb_cflags(tb) & CF_PCREL) || tb->pc =3D=3D pc); return tb; } =20 @@ -1012,14 +998,8 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) */ h =3D tb_jmp_cache_hash_func(pc); jc =3D cpu->tb_jmp_cache; - if (cflags & CF_PCREL) { - jc->array[h].pc =3D pc; - /* Ensure pc is written first. */ - qatomic_store_release(&jc->array[h].tb, tb); - } else { - /* Use the pc value already stored in tb->pc. */ - qatomic_set(&jc->array[h].tb, tb); - } + jc->array[h].pc =3D pc; + qatomic_set(&jc->array[h].tb, tb); } =20 #ifndef CONFIG_USER_ONLY --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706416998; cv=none; d=zohomail.com; s=zohoarc; b=ZFzpSA8pL9Qb1vPFBvIN2MN8IANVfdJUlCwnD2MD0AjmO40q/j1UGHw6GCltI8rlj8LXsC0wBRcv0kkemZ5TU20MubtFrz2njQvtZc3yBsZ5tTK7Z6dD+vxBHAUjq6LQ4nLpuj8CvI4zJRNvx9WFRcSZO1wr4TSmNRVFqBQmeP0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706416998; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=M8UjEMO1j2vm3/2aeEMHpkVHZcyY+4Tl4SZGy9Fx+X8=; b=afDBkb1Fu8bBoJtHEQPoQQt+8M4Qfk//69JwrHom8kxHNdpCTyaWlje6WvYAN+KEiupJGrLKbDBx8bViI4SXOBgakeus/hReLiI4we+uEuWv9pAgLlWneT1S/ALZiZlnSNF851NZ6TW75fT4QWVkK1W3uYO7TJ8WtNz2ZI+3Boc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706416998332992.2898354825131; Sat, 27 Jan 2024 20:43:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx01-0004fs-BH; Sat, 27 Jan 2024 23:42:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTwzz-0004e2-If for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:27 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTwzx-0004HV-UV for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:27 -0500 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-29080973530so1599299a91.1 for ; Sat, 27 Jan 2024 20:42:25 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416944; x=1707021744; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M8UjEMO1j2vm3/2aeEMHpkVHZcyY+4Tl4SZGy9Fx+X8=; b=xwpUCp6Z0/wMQUDar6h13ph8N6Cqlh3gAnSXJ9T+2EJt5wlB1QGShLOznRzbElZHHI yu/M+DvIERJbrPVJMXYKtXPgCPbbS+VLWsPQyYb4y+uwsSOdSURoUtcIewIgOc1spyVd /qLOFZoQdf3yLF+iK4pf09d+cyfMOz4JbikQ9RAzrrgNW20ozen8f1TleczAF7o6x1wq pLwRUvkRM5U6WnzAsOUQE20H5wukl0uV7INw0s8jc4ZaJuzhNb3oo5U+ld+wuFQAjQ89 ojsIEVB0l5DBChWWiQS5ZIk3cIIBx5X9/d3klhOB6e5J2YpR1Q7QBi3KCA43nBeCcpCc 2PEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416944; x=1707021744; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M8UjEMO1j2vm3/2aeEMHpkVHZcyY+4Tl4SZGy9Fx+X8=; b=MrPfpUhc9oiDOS4NEGRV6X5Ogoc1zGyP2bxPKXZI24erlNHsGsUI3TN7I2RuV3cpbC h5atIzE9Yy1+rr/7B+DTXpCJxTuuKBF0jPJj3/NMx9P9E5n1AQkmzqVUpi8+YkEJuFbE Nxq30mbacOZ8p6/hij6gvZE4/RbudmtnNNBqg7Iz9kzgxuFVQrMXAUW7J+5hE77rol7w jU6xB4jK9CNnoG7xxjN1HC3Nz0Ga6aw4roNfwkLRS6/Ck8caBFMIcP5F64s5OPlH69bg 7sVxNd2O4cqbE0Igavy4fqUm2DV8JrPnCYfkcXVEUIO3ml5g6osbSBdxPYH/RxGQJ6y/ e+zw== X-Gm-Message-State: AOJu0YwcwL6NBLel+1kiLRDmbIP8ZHMTRtnJS8Z/ujs6jnTX1Kd4Uzfa r/H1mVyC2kHw+wOojZxoE52xy+bxIOhmBBfQryHDzj70Yj0FGzFhMNS26sUtbS/OvnjlcM/LCqR 0GiEGOg== X-Google-Smtp-Source: AGHT+IHesmxOMg60A/XeOaybajAeK/+Za+rEP9yJMVYwQr6p/PQTpPP0TX/HDSoPZ5Vnn2TqmFmISg== X-Received: by 2002:a17:90a:9f0c:b0:290:cd3:a2d2 with SMTP id n12-20020a17090a9f0c00b002900cd3a2d2mr1592139pjp.3.1706416944267; Sat, 27 Jan 2024 20:42:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 02/33] include/exec: Move vaddr defines to separate file Date: Sun, 28 Jan 2024 14:41:42 +1000 Message-Id: <20240128044213.316480-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417000685100005 Content-Type: text/plain; charset="utf-8" From: Anton Johansson Needed to work around circular includes. vaddr is currently defined in cpu-common.h and needed by hw/core/cpu.h, but cpu-common.h also need cpu.h to know the size of the CPUState. [Maybe we can instead move parts of cpu-common.h w. hw/core/cpu.h to sort out the circular inclusion.] Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-7-anjo@rev.ng> Reviewed-by: Richard Henderson [rth: Add include of vaddr.h into cpu-common.h] Signed-off-by: Richard Henderson --- include/exec/cpu-common.h | 13 +------------ include/exec/vaddr.h | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 12 deletions(-) create mode 100644 include/exec/vaddr.h diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index fef3138d29..3109c6b67d 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -3,6 +3,7 @@ =20 /* CPU interfaces that are target independent. */ =20 +#include "exec/vaddr.h" #ifndef CONFIG_USER_ONLY #include "exec/hwaddr.h" #endif @@ -14,18 +15,6 @@ #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another= */ #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ =20 -/** - * vaddr: - * Type wide enough to contain any #target_ulong virtual address. - */ -typedef uint64_t vaddr; -#define VADDR_PRId PRId64 -#define VADDR_PRIu PRIu64 -#define VADDR_PRIo PRIo64 -#define VADDR_PRIx PRIx64 -#define VADDR_PRIX PRIX64 -#define VADDR_MAX UINT64_MAX - void cpu_exec_init_all(void); void cpu_exec_step_atomic(CPUState *cpu); =20 diff --git a/include/exec/vaddr.h b/include/exec/vaddr.h new file mode 100644 index 0000000000..b9844afc77 --- /dev/null +++ b/include/exec/vaddr.h @@ -0,0 +1,18 @@ +/* Define vaddr. */ + +#ifndef VADDR_H +#define VADDR_H + +/** + * vaddr: + * Type wide enough to contain any #target_ulong virtual address. + */ +typedef uint64_t vaddr; +#define VADDR_PRId PRId64 +#define VADDR_PRIu PRIu64 +#define VADDR_PRIo PRIo64 +#define VADDR_PRIx PRIx64 +#define VADDR_PRIX PRIX64 +#define VADDR_MAX UINT64_MAX + +#endif --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417147; cv=none; d=zohomail.com; s=zohoarc; b=RnWMj1hIz1nt+vagdx83vUUp469m+BmEwD2SGfeiQnLJW5XraMDW/kQiH6OBwcHVixNv8NINNKeNcp4yIILMAlVdxFEhc4oWUeKBmj2IVdSUYT+ZjZFWcvN85VDRVOKdgOi8x67eAr8TO070MTHuyPDhXzRWVQ/E/GcXcs7DGjc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417147; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ADBUc3fCETku7gSMiSslG1Ep+CbDq8k+uqgwv8Xr0vk=; b=AUitO8z0vmJfhDU9aMsU2O46COdgOqCetOhM81C8lrUbRkOWPDLvU6OSay//nLgT4ACS06ZrzfSCcqtlqwSrIw1+FG1MaAWvmdo5WXW1XTe+7Q6PwlNYnDSf0cE0J8yumkQM2fLd68AlH0P5agVDi8ju29i1rPqV7aBphBcaZRw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170641714783762.53220889362274; Sat, 27 Jan 2024 20:45:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx03-0004gS-6S; Sat, 27 Jan 2024 23:42:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx01-0004ft-Ah for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:29 -0500 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTwzz-0004He-Qr for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:29 -0500 Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-5cdbc4334edso782591a12.3 for ; Sat, 27 Jan 2024 20:42:27 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416946; x=1707021746; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ADBUc3fCETku7gSMiSslG1Ep+CbDq8k+uqgwv8Xr0vk=; b=GxFUAyKyJ2o/erIMEZwWZ75wlqDokA1HmbgjqiQ1d8Rs7AtwVK8V2R4UtBvGiIV0mD abe372aoUmeTGm6vh4dWrfWdJDvKgSyjJIUHnukSChm1XmnzAHgS9m0f8d2XuM7ULPpL dqyCNd9XQ5w6MxP4JEQmo5kT1PmTOkHn7dbL4LLgIxHqiKH+NNYhXcwetFp0+7pM6ehP 3jZh0a0F9UIz8MAxtr91YHRcoETB0YM9Xi04BWdUKLJ+FRIqGps0FVnzOOaBexJKn9Eb n+0gHAAajbH/p0865xQqJSuQmjN0q6xCTbV68GMda7VQnXa6EuXqoUXT8yiGsoVNJGJO rNmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416946; x=1707021746; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417148866100003 Content-Type: text/plain; charset="utf-8" From: Anton Johansson cpu-common.h is only needed for vaddr Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-8-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 238c02c05e..db58f12233 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -22,8 +22,8 @@ =20 #include "hw/qdev-core.h" #include "disas/dis-asm.h" -#include "exec/cpu-common.h" #include "exec/hwaddr.h" +#include "exec/vaddr.h" #include "exec/memattrs.h" #include "exec/tlb-common.h" #include "qapi/qapi-types-run-state.h" --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416949; x=1707021749; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9+/x34hZ0Savjf5fK/vjCGUP8dkpzXoOGlANXKjp7EA=; b=WKz9Ie4mFLhbswDPhE5HzRw9zXcT4RQtK0038S770RxLBSjsVhg3MOb2Bf/3rDZg+f wEl7lvW9fss8tqeELwDRSg4I7yzan6TW3NSa6LOb93jUr4rqRpeRphF3cwwsEz0r9oQA bUOqBBEmGdOVDJBJa7utWVOEuXc5QthRYFZTUw1bM+NnP4xzljr320Dt/+47y8DlyZIk Runu4xmjy+t/6YnGboc0VVVmklfN5kXHML166JvCTKyuvs6TMLnmVBfS36hC1nBhdzL5 gilANlcddAKCNSM7mefQy/SWEKrLOi7FJaR0NiGCqy8yEIVjuuVvAGv4B+J63RU9Pwig 6hSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416949; x=1707021749; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9+/x34hZ0Savjf5fK/vjCGUP8dkpzXoOGlANXKjp7EA=; b=b2HaDo4ic6pdIQDmE08H8ovAudvt2F6eA28y/EcTUvKuzrH8+uDGSrwoUHRAJYNj6c 6BX0MJ4Z6Ix/rJyhJkAPuRKpEUcDJYZT4dN7eQ+E6+UynF+u40xPnCxPq/vPCAVXXkcU hebQkEoKfOA0UCYjnJiaEn/fprftnxc8QlAWw74gybLRi+uOPH5NMIg/e1mcFHzd8By5 MQ/Oy9GT/bB2hZwqOaeYCFTyiR73cu+8f+A9pUGGOaR5qV6duv64EWpa0Y6tfMaEVqbD FUAEaiR7NZdyoq7MBE/LF3SCFxrq0hcH99P1Tgl4DUvR7QOxCzqfxOYlaFjMMpAr9DMX YxoQ== X-Gm-Message-State: AOJu0YwERRlovn5E0AqxHqb5iub1meqnoDaYqd2iJS39R6ekTr3IYJYy s0GTjadF78zgxYTMZBvh+BLj80V2K0MYzSKh/EdXP3jSg8TKgg7f6xcJWJkm9t00uoZRTcOozQO 8YYBcOQ== X-Google-Smtp-Source: AGHT+IEupSSUlk4yg27uHfUYkhPqcWfJ22C93QRHdTPv/xEjJTi3MZj198hh62fO+U7wp6BVh9mMLA== X-Received: by 2002:a05:6214:5092:b0:68c:4a74:f65 with SMTP id kk18-20020a056214509200b0068c4a740f65mr44845qvb.21.1706416948916; Sat, 27 Jan 2024 20:42:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 04/33] target: Use vaddr in gen_intermediate_code Date: Sun, 28 Jan 2024 14:41:44 +1000 Message-Id: <20240128044213.316480-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f32; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417094801100001 Content-Type: text/plain; charset="utf-8" From: Anton Johansson Makes gen_intermediate_code() signature target agnostic so the function can be called from accel/tcg/translate-all.c without target specifics. Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-9-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/exec/translator.h | 2 +- target/alpha/translate.c | 2 +- target/arm/tcg/translate.c | 2 +- target/avr/translate.c | 2 +- target/cris/translate.c | 2 +- target/hexagon/translate.c | 2 +- target/hppa/translate.c | 2 +- target/i386/tcg/translate.c | 2 +- target/loongarch/tcg/translate.c | 2 +- target/m68k/translate.c | 2 +- target/microblaze/translate.c | 2 +- target/mips/tcg/translate.c | 2 +- target/nios2/translate.c | 2 +- target/openrisc/translate.c | 2 +- target/ppc/translate.c | 2 +- target/riscv/translate.c | 2 +- target/rx/translate.c | 2 +- target/s390x/tcg/translate.c | 2 +- target/sh4/translate.c | 2 +- target/sparc/translate.c | 2 +- target/tricore/translate.c | 2 +- target/xtensa/translate.c | 2 +- 22 files changed, 22 insertions(+), 22 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index 6d3f59d095..b0412ea6b6 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -33,7 +33,7 @@ * the target-specific DisasContext, and then invoke translator_loop. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_i= nsns, - target_ulong pc, void *host_pc); + vaddr pc, void *host_pc); =20 /** * DisasJumpType: diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 32333081d8..134eb7225b 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2971,7 +2971,7 @@ static const TranslatorOps alpha_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_i= nsns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cpu, tb, max_insns, pc, host_pc, &alpha_tr_ops, &dc.ba= se); diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index b3660173d1..5fa8249723 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -9691,7 +9691,7 @@ static const TranslatorOps thumb_translator_ops =3D { =20 /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_i= nsns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc =3D { }; const TranslatorOps *ops =3D &arm_translator_ops; diff --git a/target/avr/translate.c b/target/avr/translate.c index cdffa04519..e5dd057799 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2805,7 +2805,7 @@ static const TranslatorOps avr_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc =3D { }; translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base); diff --git a/target/cris/translate.c b/target/cris/translate.c index b3974ba0bb..ee1402a9a3 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3172,7 +3172,7 @@ static const TranslatorOps cris_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cs, tb, max_insns, pc, host_pc, &cris_tr_ops, &dc.base= ); diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 95579ae243..a14211cf68 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -1154,7 +1154,7 @@ static const TranslatorOps hexagon_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; =20 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3ef39b1bd7..08d09d50d7 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4631,7 +4631,7 @@ static const TranslatorOps hppa_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.bas= e); diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index e193c74472..2808903661 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -7088,7 +7088,7 @@ static const TranslatorOps i386_tr_ops =3D { =20 /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_i= nsns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; =20 diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/transl= ate.c index 21f4db6fbd..235515c629 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -343,7 +343,7 @@ static const TranslatorOps loongarch_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; =20 diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 4a0b0b2703..5ec88c5f0d 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6088,7 +6088,7 @@ static const TranslatorOps m68k_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_i= nsns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cpu, tb, max_insns, pc, host_pc, &m68k_tr_ops, &dc.bas= e); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 49bfb4a0ea..2e628647d1 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1792,7 +1792,7 @@ static const TranslatorOps mb_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_i= nsns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base); diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 13e43fa3b6..e10232738c 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15554,7 +15554,7 @@ static const TranslatorOps mips_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; =20 diff --git a/target/nios2/translate.c b/target/nios2/translate.c index e806623594..3078372b36 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -1036,7 +1036,7 @@ static const TranslatorOps nios2_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cs, tb, max_insns, pc, host_pc, &nios2_tr_ops, &dc.bas= e); diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index ecff4412b7..d4cbc5eaea 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1658,7 +1658,7 @@ static const TranslatorOps openrisc_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 329da4d518..049f636927 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7518,7 +7518,7 @@ static const TranslatorOps ppc_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 071fbad7ef..ab18899122 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1287,7 +1287,7 @@ static const TranslatorOps riscv_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; =20 diff --git a/target/rx/translate.c b/target/rx/translate.c index c6ce717a95..2265bd14ac 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2266,7 +2266,7 @@ static const TranslatorOps rx_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; =20 diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 8df00b7df9..a5fd9cccaa 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6547,7 +6547,7 @@ static const TranslatorOps s390x_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; =20 diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 81f825f125..6a6d862b10 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2317,7 +2317,7 @@ static const TranslatorOps sh4_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9387299559..97184fa403 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5327,7 +5327,7 @@ static const TranslatorOps sparc_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc =3D {}; =20 diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 66553d1be0..f1156c39e7 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8472,7 +8472,7 @@ static const TranslatorOps tricore_tr_ops =3D { =20 =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; translator_loop(cs, tb, max_insns, pc, host_pc, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 87947236ca..e4772462b5 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1239,7 +1239,7 @@ static const TranslatorOps xtensa_translator_ops =3D { }; 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416951; x=1707021751; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8stgI+xO0LshRlV+dbOXjfDk9OWAAP8Iuj6nGWfVSvI=; b=ZMeBH8qsYJ009dEw2e/IrqW9Za95sgIFtwbsh7LKXgAsEnP3RPIuNIzAM9TU1Csp2m YsxAW8hxtbRTGr5VxiaXIPii/wb1eHa2Lb4f4zhbE5ahh5H7O9qXfHAnVSWU2n5xNYHE tp+xb4+m9GOUC5EKQsjlCgR7zucKcO/rg4lIOHAV/4YYaCVu81J9WRvByY6a7eeYv0qW ELRKRaW9CoCZnmxggguOx6HVGvEKmt7kj016ziKUW4UYYl42EDNql6fqrXp7Ve4Y17F8 KkeNj89h2Z6MdC/MiVQuMKGQp+IqlBSxKVj/z/oHbXEipl7JtiKtosRXh7K/oSfGs6TZ BTbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416951; x=1707021751; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8stgI+xO0LshRlV+dbOXjfDk9OWAAP8Iuj6nGWfVSvI=; b=FBXwDtAJAwx0UxQNY9W5n3IGR8MuSCHA5riR2b67DuZm4QHfxGrEQF+wU7L6pOcolt h0zEP24LSRGJKGKIr3II6K5lVJz2Qtv2Vj871iAyy6rljMtXXT64/g9KHTkGkxzUQ2Yp E3Fv/yjEtCkvlhttWtv3pyfFX8dw30vjPunlP4eiZQhMlR3CIqbNLpfsyhQEod7LNlz3 4ic5fWQPPM7N5Tzjxf91NhyIFbTGsIFNad2QimsKJ6JCkfrTXxXsMu4ckwWEuqv7vaC4 /38s00izH51pUD6vo7KKAZfytPKyv9TnnViiH2rxYaZmKKlqsT/uhjDhcu/IQ2TQucTT ASuA== X-Gm-Message-State: AOJu0YyY7SucVBHOwnD6nM7rEWmorJ+WP87fYzZHjUYRtQlyz/IHB3go DLtOPjY3S7znTeDLtUl//V+6mGrRU3sHJCkDsqDCz6aOvJ3BYUTSZKW7Y9102jcbV+FgAam2rGO mKSY+Og== X-Google-Smtp-Source: AGHT+IHoQHbXyGCIWkheEG2gDNNMGuSHWgbKewCc7D7o5WZRtSE7QjNYLJQkbTL2TBAU8cTbastYpg== X-Received: by 2002:a17:90a:6e4a:b0:290:58a7:1d65 with SMTP id s10-20020a17090a6e4a00b0029058a71d65mr2371173pjm.49.1706416951073; Sat, 27 Jan 2024 20:42:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 05/33] include/exec: Use vaddr in DisasContextBase for virtual addresses Date: Sun, 28 Jan 2024 14:41:45 +1000 Message-Id: <20240128044213.316480-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417024750100003 Content-Type: text/plain; charset="utf-8" From: Anton Johansson Updates target/ QEMU_LOG macros to use VADDR_PRIx for printing updated DisasContextBase fields. Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-10-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/exec/translator.h | 6 +++--- target/mips/tcg/translate.h | 3 ++- target/hexagon/translate.c | 3 ++- target/m68k/translate.c | 2 +- target/mips/tcg/translate.c | 12 ++++++------ 5 files changed, 14 insertions(+), 12 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index b0412ea6b6..51624feb10 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -79,8 +79,8 @@ typedef enum DisasJumpType { */ typedef struct DisasContextBase { TranslationBlock *tb; - target_ulong pc_first; - target_ulong pc_next; + vaddr pc_first; + vaddr pc_next; DisasJumpType is_jmp; int num_insns; int max_insns; @@ -235,7 +235,7 @@ void translator_fake_ldb(uint8_t insn8, abi_ptr pc); * Translators can use this to enforce the rule that only single-insn * translation blocks are allowed to cross page boundaries. */ -static inline bool is_same_page(const DisasContextBase *db, target_ulong a= ddr) +static inline bool is_same_page(const DisasContextBase *db, vaddr addr) { return ((addr ^ db->pc_first) & TARGET_PAGE_MASK) =3D=3D 0; } diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index cffcfeab8c..93a78b8121 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -202,7 +202,8 @@ extern TCGv bcond; do { = \ if (MIPS_DEBUG_DISAS) { = \ qemu_log_mask(CPU_LOG_TB_IN_ASM, = \ - TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\= n", \ + "%016" VADDR_PRIx = \ + ": %08x Invalid %s %03x %03x %03x\n", = \ ctx->base.pc_next, ctx->opcode, op, = \ ctx->opcode >> 26, ctx->opcode & 0x3F, = \ ((ctx->opcode >> 16) & 0x1F)); = \ diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index a14211cf68..f163eefe97 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -234,7 +234,8 @@ static int read_packet_words(CPUHexagonState *env, Disa= sContext *ctx, g_assert(ctx->base.num_insns =3D=3D 1); } =20 - HEX_DEBUG_LOG("decode_packet: pc =3D 0x%x\n", ctx->base.pc_next); + HEX_DEBUG_LOG("decode_packet: pc =3D 0x%" VADDR_PRIx "\n", + ctx->base.pc_next); HEX_DEBUG_LOG(" words =3D { "); for (int i =3D 0; i < nwords; i++) { HEX_DEBUG_LOG("0x%x, ", words[i]); diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 5ec88c5f0d..f886190f88 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1457,7 +1457,7 @@ DISAS_INSN(undef) * for the 680x0 series, as well as those that are implemented * but actually illegal for CPU32 or pre-68020. */ - qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n", + qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %" VADDR_PRIx "\= n", insn, s->base.pc_next); gen_exception(s, s->base.pc_next, EXCP_ILLEGAL); } diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index e10232738c..12094cc1e7 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -4585,8 +4585,8 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS - LOG_DISAS("Branch in delay / forbidden slot at PC 0x" - TARGET_FMT_lx "\n", ctx->base.pc_next); + LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" + VADDR_PRIx "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); goto out; @@ -9061,8 +9061,8 @@ static void gen_compute_branch1_r6(DisasContext *ctx,= uint32_t op, =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS - LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx - "\n", ctx->base.pc_next); + LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" + VADDR_PRIx "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); return; @@ -11274,8 +11274,8 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS - LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx - "\n", ctx->base.pc_next); + LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" + VADDR_PRIx "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); return; --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416954; x=1707021754; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Abpnrf3mk/IImEiBxCwuY+1bvCj+UYnsd1PobWXi05Q=; b=DvHQdL7RtDp5fiwNd6IpYwISdNEuhL42GcWdh498Rp/aryiZssq2rrbzALLYd4HjjP wAWOxZsPLX1E6EyKi5dECOfcPddFvPtHWvleD27hThyh00iYVFJzyS9usmT0lpNybE89 lH5/Fv+I1fbp5TzxyOERuufr+s6OdKtFSGnu4iFTeUrWK3Qdwk60jqnvfzNI7H59HYjB Be3j/9fWcJJnyETWs2ik+c1bjaeFwu7dWuMc6qyspdD2EUo4mVUv/vJdDkKFYtYWiJYd 1gteFDpL9sdBx3+VltnJPJqUaE+ul1E/TzegE4LccY9o/MbQBnkZ+kr/gKNpuqx2HsFL ipQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416954; x=1707021754; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417004540100001 Content-Type: text/plain; charset="utf-8" From: Anton Johansson Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-11-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 6061e33ac9..eb8f3f0595 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -121,8 +121,8 @@ static inline bool guest_range_valid_untagged(abi_ulong= start, abi_ulong len) h2g_nocheck(x); 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416956; x=1707021756; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VODEHWMxMF5aJBZz0S2TC6sc+IupRmg6TxWrBBUh29E=; b=IgdA0baFc7S4pfKZgA4ioGXevzDadvFAgqMQL1MpuYLT87R6/81IU3XVK2R18DQW2x T3xSIOGe0NfhBOCr9X8p8zMmMbcrF3NRnyzE0et56hJrUQuKP8dm4LpfIYj7zyJGCqj8 gJclooiXWt3+mhxih+V7+ZJhl12YloabYDA1pX9DqwJd57KAykPyB/RtNBQaybKpbG+H qG54v3enaAnyAIdeNkUPoRNVAwID9uqmg8oSn02Sw7/Tt01f4pT20ZC1/muvDIm+5Vb0 PiGkZO5XRCENSi8VI5cCWEZThaj5p7aNrqxG8EK8XS0M2z/ps8dbinmRWF73Ei8mwZQi u20A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416956; x=1707021756; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VODEHWMxMF5aJBZz0S2TC6sc+IupRmg6TxWrBBUh29E=; b=fGoFWakA5QWb+VD+4eSZutukvECEZyyCRZaN6wNqlz//MYvCQeb+KNY7MJIPgIwi5+ NFdYj4lVq7ccJZBkPNVljZpnWEQViShYRvA4qXKMTv4dU+SATlkWgtRfpMj4Caw4CAj3 0ZSvYyUIOHTnRMBE5HxB52jKuYsW6+N9dCcE8FfNkv9BWuhfHrQc+FZWm6rW2NMUiL9D 3A91JHInjLfEHS/h58XlOW0hElVkifOKpTwN6csgA6tbpSREX8HImw31KSJMsQ+bvEO9 vtbpqh0z/perCGdPsi3w3dF0/bm6W/Q8Q6LTdMv0h+ZXG/7twgztFcRvMv1Py7wlCwC2 4svQ== X-Gm-Message-State: AOJu0YxRtMUzRQ8gqleTiuNzoeHf9cvcAu37B/d6+UdIIcNPq8BtsbOk D0mdwSZ2Ymuv2eGfoNmirVbTiAbLwo80qC85zoKAGP2zQNCTFmPjAOitaIY3fde0UNB5L0QsuYu wGe81Ew== X-Google-Smtp-Source: AGHT+IHllzqTXRtRBjNCO11lpWy8ZOAPEBDoGiRhQrrZN3ZA6Wg7d27SgqX6ZKbx3awj2GZxyeLS7Q== X-Received: by 2002:ac8:4e93:0:b0:42a:820:b140 with SMTP id 19-20020ac84e93000000b0042a0820b140mr3733083qtp.120.1706416956249; Sat, 27 Jan 2024 20:42:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 07/33] target: Uninline cpu_mmu_index() Date: Sun, 28 Jan 2024 14:41:47 +1000 Message-Id: <20240128044213.316480-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82e; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417168941100001 Content-Type: text/plain; charset="utf-8" From: Anton Johansson Uninlines the target-defined cpu_mmu_index() function by moving its definition to target/*/cpu.c. This allows for compiling memory access functions in accel/tcg/cputlb.c without having to know target specifics. Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-13-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/exec/cpu-common.h | 10 ++++++++++ target/alpha/cpu.h | 9 --------- target/arm/cpu.h | 13 ------------- target/avr/cpu.h | 7 ------- target/cris/cpu.h | 4 ---- target/hexagon/cpu.h | 9 --------- target/hppa/cpu.h | 13 ------------- target/i386/cpu.h | 7 ------- target/loongarch/cpu.h | 12 ------------ target/m68k/cpu.h | 4 ---- target/microblaze/cpu.h | 15 --------------- target/mips/cpu.h | 5 ----- target/nios2/cpu.h | 6 ------ target/openrisc/cpu.h | 12 ------------ target/ppc/cpu.h | 8 -------- target/riscv/cpu.h | 3 --- target/rx/cpu.h | 5 ----- target/s390x/cpu.h | 31 ------------------------------- target/sh4/cpu.h | 10 ---------- target/sparc/cpu.h | 28 ---------------------------- target/tricore/cpu.h | 5 ----- target/xtensa/cpu.h | 5 ----- target/alpha/cpu.c | 8 ++++++++ target/arm/cpu.c | 5 +++++ target/avr/cpu.c | 5 +++++ target/cris/cpu.c | 4 ++++ target/hexagon/cpu.c | 9 +++++++++ target/hppa/cpu.c | 13 +++++++++++++ target/i386/cpu.c | 7 +++++++ target/loongarch/cpu.c | 12 ++++++++++++ target/m68k/cpu.c | 5 +++++ target/microblaze/cpu.c | 16 ++++++++++++++++ target/mips/cpu.c | 5 +++++ target/nios2/cpu.c | 6 ++++++ target/openrisc/cpu.c | 12 ++++++++++++ target/ppc/cpu.c | 9 +++++++++ target/riscv/cpu_helper.c | 2 +- target/rx/cpu.c | 5 +++++ target/s390x/cpu.c | 31 +++++++++++++++++++++++++++++++ target/sh4/cpu.c | 13 +++++++++++++ target/sparc/cpu.c | 28 ++++++++++++++++++++++++++++ target/tricore/cpu.c | 5 +++++ target/xtensa/cpu.c | 4 ++++ 43 files changed, 213 insertions(+), 212 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 3109c6b67d..4724135f30 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -34,6 +34,16 @@ void cpu_list_lock(void); void cpu_list_unlock(void); unsigned int cpu_list_generation_id_get(void); =20 +/** + * cpu_mmu_index: + * @env: The cpu environment + * @ifetch: True for code access, false for data access. + * + * Return the core mmu index for the current translation regime. + * This function is used by generic TCG code paths. + */ +int cpu_mmu_index(CPUArchState *env, bool ifetch); + void tcg_iommu_init_notifier_list(CPUState *cpu); void tcg_iommu_free_notifier_list(CPUState *cpu); =20 diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index ce806587ca..abf778735a 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -389,15 +389,6 @@ enum { =20 #define TB_FLAG_UNALIGN (1u << 1) =20 -static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) -{ - int ret =3D env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_= IDX; - if (env->flags & ENV_FLAG_PAL_MODE) { - ret =3D MMU_KERNEL_IDX; - } - return ret; -} - enum { IR_V0 =3D 0, IR_T0 =3D 1, diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ec276fcd57..b0edf2e540 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3268,19 +3268,6 @@ FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHIC= H) =20 -/** - * cpu_mmu_index: - * @env: The cpu environment - * @ifetch: True for code access, false for data access. - * - * Return the core mmu index for the current translation regime. - * This function is used by generic TCG code paths. - */ -static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) -{ - return EX_TBFLAG_ANY(env->hflags, MMUIDX); -} - /** * sve_vq * @env: the cpu context diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 7d5dd42575..d185d20dcb 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -184,13 +184,6 @@ static inline void set_avr_feature(CPUAVRState *env, i= nt feature) env->features |=3D (1U << feature); } =20 -#define cpu_mmu_index avr_cpu_mmu_index - -static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) -{ - return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; -} - void avr_cpu_tcg_init(void); =20 int cpu_avr_exec(CPUState *cpu); diff --git a/target/cris/cpu.h b/target/cris/cpu.h index d830dcac5b..3904e5448c 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -260,10 +260,6 @@ enum { =20 /* MMU modes definitions */ #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) -{ - return !!(env->pregs[PR_CCS] & U_FLAG); -} =20 /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 5c11ae3445..3eef58fe8f 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -146,15 +146,6 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonStat= e *env, vaddr *pc, *flags =3D hex_flags; } =20 -static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else -#error System mode not supported on Hexagon yet -#endif -} - typedef HexagonCPU ArchCPU; =20 void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6a153405d2..7a181e8f33 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -281,19 +281,6 @@ static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE; } =20 -static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else - if (env->psw & (ifetch ? PSW_C : PSW_D)) { - return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P); - } - /* mmu disabled */ - return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; -#endif -} - void hppa_translate_init(void); =20 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7f0786e8b9..6a5b180ccb 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2296,13 +2296,6 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define MMU_NESTED_IDX 3 #define MMU_PHYS_IDX 4 =20 -static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) -{ - return (env->hflags & HF_CPL_MASK) =3D=3D 3 ? MMU_USER_IDX : - (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) - ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; -} - static inline int cpu_mmu_index_kernel(CPUX86State *env) { return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 0fa5e0ca93..64eac07a16 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -408,18 +408,6 @@ struct LoongArchCPUClass { #define MMU_IDX_USER MMU_PLV_USER #define MMU_IDX_DA 4 =20 -static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_IDX_USER; -#else - if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { - return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); - } - return MMU_IDX_DA; -#endif -} - static inline bool is_la64(CPULoongArchState *env) { return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) =3D=3D CPUCFG1_ARCH_L= A64; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index d13427b0fe..aca4aa610b 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -577,10 +577,6 @@ enum { /* MMU modes definitions */ #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) -{ - return (env->sr & SR_S) =3D=3D 0 ? 1 : 0; -} =20 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b5374365f5..446af5dd4c 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -434,21 +434,6 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr ph= ysaddr, vaddr addr, MemTxResult response, uintptr_t retaddr); #endif =20 -static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) -{ - MicroBlazeCPU *cpu =3D env_archcpu(env); - - /* Are we in nommu mode?. */ - if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { - return MMU_NOMMU_IDX; - } - - if (env->msr & MSR_UM) { - return MMU_USER_IDX; - } - return MMU_KERNEL_IDX; -} - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_mb_cpu; #endif diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1163a71f3c..4c9dc09a66 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1253,11 +1253,6 @@ static inline int hflags_mmu_index(uint32_t hflags) } } =20 -static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) -{ - return hflags_mmu_index(env->hflags); -} - #include "exec/cpu-all.h" =20 /* Exceptions */ diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2d79b5b298..4164a3432e 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -270,12 +270,6 @@ void do_nios2_semihosting(CPUNios2State *env); #define MMU_SUPERVISOR_IDX 0 #define MMU_USER_IDX 1 =20 -static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) -{ - return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : - MMU_SUPERVISOR_IDX; -} - #ifndef CONFIG_USER_ONLY hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b454014ddd..b1b7db5cbd 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -361,18 +361,6 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCSta= te *env, vaddr *pc, | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); } =20 -static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) -{ - int ret =3D MMU_NOMMU_IDX; /* mmu is disabled */ - - if (env->sr & (ifetch ? SR_IME : SR_DME)) { - /* The mmu is enabled; test supervisor state. */ - ret =3D env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; - } - - return ret; -} - static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) { return (env->sr diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f8101ffa29..59587a8aba 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1624,14 +1624,6 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint= 32_t val); =20 /* MMU modes definitions */ #define MMU_USER_IDX 0 -static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else - return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) &= 7; -#endif -} =20 /* Compatibility modes */ #if defined(TARGET_PPC64) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5f3955c38d..bca27278ed 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -498,7 +498,6 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t reta= ddr); @@ -507,8 +506,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); =20 -#define cpu_mmu_index riscv_cpu_mmu_index - #ifndef CONFIG_USER_ONLY void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 65f9cd2d0a..c53593d7aa 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -158,11 +158,6 @@ static inline void cpu_get_tb_cpu_state(CPURXState *en= v, vaddr *pc, *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); } =20 -static inline int cpu_mmu_index(CPURXState *env, bool ifetch) -{ - return 0; -} - static inline uint32_t rx_cpu_pack_psw(CPURXState *env) { uint32_t psw =3D 0; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index fa3aac4f97..61c893b1b9 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -381,37 +381,6 @@ extern const VMStateDescription vmstate_s390_cpu; #define MMU_HOME_IDX 2 #define MMU_REAL_IDX 3 =20 -static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else - if (!(env->psw.mask & PSW_MASK_DAT)) { - return MMU_REAL_IDX; - } - - if (ifetch) { - if ((env->psw.mask & PSW_MASK_ASC) =3D=3D PSW_ASC_HOME) { - return MMU_HOME_IDX; - } - return MMU_PRIMARY_IDX; - } - - switch (env->psw.mask & PSW_MASK_ASC) { - case PSW_ASC_PRIMARY: - return MMU_PRIMARY_IDX; - case PSW_ASC_SECONDARY: - return MMU_SECONDARY_IDX; - case PSW_ASC_HOME: - return MMU_HOME_IDX; - case PSW_ASC_ACCREG: - /* Fallthrough: access register mode is not yet supported */ - default: - abort(); - } -#endif -} - #ifdef CONFIG_TCG =20 #include "tcg/tcg_s390x.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 0e6fa65bae..9211da6bde 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -273,16 +273,6 @@ void cpu_load_tlb(CPUSH4State * env); =20 /* MMU modes definitions */ #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch) -{ - /* The instruction in a RTE delay slot is fetched in privileged - mode, but executed in user mode. */ - if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { - return 0; - } else { - return (env->sr & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; - } -} =20 #include "exec/cpu-all.h" =20 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 12a11ecb26..51856152fa 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -708,34 +708,6 @@ static inline int cpu_supervisor_mode(CPUSPARCState *e= nv1) } #endif =20 -static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) -{ -#if defined(CONFIG_USER_ONLY) - return MMU_USER_IDX; -#elif !defined(TARGET_SPARC64) - if ((env->mmuregs[0] & MMU_E) =3D=3D 0) { /* MMU disabled */ - return MMU_PHYS_IDX; - } else { - return env->psrs; - } -#else - /* IMMU or DMMU disabled. */ - if (ifetch - ? (env->lsu & IMMU_E) =3D=3D 0 || (env->pstate & PS_RED) !=3D 0 - : (env->lsu & DMMU_E) =3D=3D 0) { - return MMU_PHYS_IDX; - } else if (cpu_hypervisor_mode(env)) { - return MMU_PHYS_IDX; - } else if (env->tl > 0) { - return MMU_NUCLEUS_IDX; - } else if (cpu_supervisor_mode(env)) { - return MMU_KERNEL_IDX; - } else { - return MMU_USER_IDX; - } -#endif -} - static inline int cpu_interrupts_enabled(CPUSPARCState *env1) { #if !defined (TARGET_SPARC64) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 2d4446cea5..220af69fc2 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -246,11 +246,6 @@ void fpu_set_state(CPUTriCoreState *env); =20 #define MMU_USER_IDX 2 =20 -static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) -{ - return 0; -} - #include "exec/cpu-all.h" =20 FIELD(TB_FLAGS, PRIV, 0, 2) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 4b033ee924..6b8d0636d2 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -713,11 +713,6 @@ static inline uint32_t xtensa_replicate_windowstart(CP= UXtensaState *env) /* MMU modes definitions */ #define MMU_USER_IDX 3 =20 -static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) -{ - return xtensa_get_cring(env); -} - #define XTENSA_TBFLAG_RING_MASK 0x3 #define XTENSA_TBFLAG_EXCM 0x4 #define XTENSA_TBFLAG_LITBASE 0x8 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b8ed29e343..ce18bedcca 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -25,6 +25,14 @@ #include "cpu.h" #include "exec/exec-all.h" =20 +int cpu_mmu_index(CPUAlphaState *env, bool ifetch) +{ + int ret =3D env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_= IDX; + if (env->flags & ENV_FLAG_PAL_MODE) { + ret =3D MMU_KERNEL_IDX; + } + return ret; +} =20 static void alpha_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 593695b424..0ee9a879f0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -49,6 +49,11 @@ #include "fpu/softfloat.h" #include "cpregs.h" =20 +int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + return EX_TBFLAG_ANY(env->hflags, MMUIDX); +} + static void arm_cpu_set_pc(CPUState *cs, vaddr value) { ARMCPU *cpu =3D ARM_CPU(cs); diff --git a/target/avr/cpu.c b/target/avr/cpu.c index f5cbdc4a8c..ffb2234ecf 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -27,6 +27,11 @@ #include "tcg/debug-assert.h" #include "hw/qdev-properties.h" =20 +int cpu_mmu_index(CPUAVRState *env, bool ifetch) +{ + return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; +} + static void avr_cpu_set_pc(CPUState *cs, vaddr value) { AVRCPU *cpu =3D AVR_CPU(cs); diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 9ba08e8b0c..1a8a544e31 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -27,6 +27,10 @@ #include "cpu.h" #include "mmu.h" =20 +int cpu_mmu_index(CPUCRISState *env, bool ifetch) +{ + return !!(env->pregs[PR_CCS] & U_FLAG); +} =20 static void cris_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index c0cd739e15..fd8dafad31 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -26,6 +26,15 @@ #include "tcg/tcg.h" #include "exec/gdbstub.h" =20 +int cpu_mmu_index(CPUHexagonState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else +#error System mode not supported on Hexagon yet +#endif +} + static void hexagon_v67_cpu_init(Object *obj) { } static void hexagon_v68_cpu_init(Object *obj) { } static void hexagon_v69_cpu_init(Object *obj) { } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 14e17fa9aa..04f0b927b6 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -28,6 +28,19 @@ #include "fpu/softfloat.h" #include "tcg/tcg.h" =20 +int cpu_mmu_index(CPUHPPAState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + if (env->psw & (ifetch ? PSW_C : PSW_D)) { + return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P); + } + /* mmu disabled */ + return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; +#endif +} + static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { HPPACPU *cpu =3D HPPA_CPU(cs); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 03822d9ba8..d0adfb381b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -46,6 +46,13 @@ #include "disas/capstone.h" #include "cpu-internal.h" =20 +int cpu_mmu_index(CPUX86State *env, bool ifetch) +{ + return (env->hflags & HF_CPL_MASK) =3D=3D 3 ? MMU_USER_IDX : + (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) + ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; +} + static void x86_cpu_realizefn(DeviceState *dev, Error **errp); =20 /* Helpers for building CPUID[2] descriptors: */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 064540397d..316a85bacd 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -31,6 +31,18 @@ #include "tcg/tcg.h" #endif =20 +int cpu_mmu_index(CPULoongArchState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_IDX_USER; +#else + if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { + return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); + } + return MMU_IDX_DA; +#endif +} + const char * const regnames[32] =3D { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 1421e77c2c..604cdd5faf 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -24,6 +24,11 @@ #include "migration/vmstate.h" #include "fpu/softfloat.h" =20 +int cpu_mmu_index(CPUM68KState *env, bool ifetch) +{ + return (env->sr & SR_S) =3D=3D 0 ? 1 : 0; +} + static void m68k_cpu_set_pc(CPUState *cs, vaddr value) { M68kCPU *cpu =3D M68K_CPU(cs); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bbb3335cad..f8891de41e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -32,6 +32,22 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" =20 +int cpu_mmu_index(CPUMBState *env, bool ifetch) +{ + MicroBlazeCPU *cpu =3D env_archcpu(env); + + /* Are we in nommu mode?. */ + if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { + return MMU_NOMMU_IDX; + } + + if (env->msr & MSR_UM) { + return MMU_USER_IDX; + } + return MMU_KERNEL_IDX; +} + + static const struct { const char *name; uint8_t version_id; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a0023edd43..34c0e40d32 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -35,6 +35,11 @@ #include "semihosting/semihost.h" #include "fpu_helper.h" =20 +int cpu_mmu_index(CPUMIPSState *env, bool ifetch) +{ + return hflags_mmu_index(env->hflags); +} + const char regnames[32][3] =3D { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index a27732bf2b..976b8c50ad 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -26,6 +26,12 @@ #include "gdbstub/helpers.h" #include "hw/qdev-properties.h" =20 +int cpu_mmu_index(CPUNios2State *env, bool ifetch) +{ + return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : + MMU_SUPERVISOR_IDX; +} + static void nios2_cpu_set_pc(CPUState *cs, vaddr value) { Nios2CPU *cpu =3D NIOS2_CPU(cs); diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 381ebe00d3..fedeba3a3f 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -25,6 +25,18 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" =20 +int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) +{ + int ret =3D MMU_NOMMU_IDX; /* mmu is disabled */ + + if (env->sr & (ifetch ? SR_IME : SR_DME)) { + /* The mmu is enabled; test supervisor state. */ + ret =3D env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; + } + + return ret; +} + static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index e3ad8e0c27..53f1d5c370 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -27,6 +27,15 @@ #include "helper_regs.h" #include "sysemu/tcg.h" =20 +int cpu_mmu_index(CPUPPCState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) &= 7; +#endif +} + target_ulong cpu_read_xer(const CPUPPCState *env) { if (is_isa300(env)) { diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c7cc7eb423..ea54081130 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -33,7 +33,7 @@ #include "debug.h" #include "tcg/oversized-guest.h" =20 -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) +int cpu_mmu_index(CPURISCVState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return 0; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index c5ffeffe32..b9f2bff9ce 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -26,6 +26,11 @@ #include "fpu/softfloat.h" #include "tcg/debug-assert.h" =20 +int cpu_mmu_index(CPURXState *env, bool ifetch) +{ + return 0; +} + static void rx_cpu_set_pc(CPUState *cs, vaddr value) { RXCPU *cpu =3D RX_CPU(cs); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 6acfa1c91b..bbb0b65bee 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -43,6 +43,37 @@ #define CR0_RESET 0xE0UL #define CR14_RESET 0xC2000000UL; =20 +int cpu_mmu_index(CPUS390XState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + if (!(env->psw.mask & PSW_MASK_DAT)) { + return MMU_REAL_IDX; + } + + if (ifetch) { + if ((env->psw.mask & PSW_MASK_ASC) =3D=3D PSW_ASC_HOME) { + return MMU_HOME_IDX; + } + return MMU_PRIMARY_IDX; + } + + switch (env->psw.mask & PSW_MASK_ASC) { + case PSW_ASC_PRIMARY: + return MMU_PRIMARY_IDX; + case PSW_ASC_SECONDARY: + return MMU_SECONDARY_IDX; + case PSW_ASC_HOME: + return MMU_HOME_IDX; + case PSW_ASC_ACCREG: + /* Fallthrough: access register mode is not yet supported */ + default: + abort(); + } +#endif +} + #ifndef CONFIG_USER_ONLY static bool is_early_exception_psw(uint64_t mask, uint64_t addr) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 806a0ef875..e99fba7778 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -28,6 +28,19 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" =20 +int cpu_mmu_index(CPUSH4State *env, bool ifetch) +{ + /* + * The instruction in a RTE delay slot is fetched in privileged + * mode, but executed in user mode. + */ + if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { + return 0; + } else { + return (env->sr & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; + } +} + static void superh_cpu_set_pc(CPUState *cs, vaddr value) { SuperHCPU *cpu =3D SUPERH_CPU(cs); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index befa7fc4eb..e2b1feac2f 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -29,6 +29,34 @@ =20 //#define DEBUG_FEATURES =20 +int cpu_mmu_index(CPUSPARCState *env, bool ifetch) +{ +#if defined(CONFIG_USER_ONLY) + return MMU_USER_IDX; +#elif !defined(TARGET_SPARC64) + if ((env->mmuregs[0] & MMU_E) =3D=3D 0) { /* MMU disabled */ + return MMU_PHYS_IDX; + } else { + return env->psrs; + } +#else + /* IMMU or DMMU disabled. */ + if (ifetch + ? (env->lsu & IMMU_E) =3D=3D 0 || (env->pstate & PS_RED) !=3D 0 + : (env->lsu & DMMU_E) =3D=3D 0) { + return MMU_PHYS_IDX; + } else if (cpu_hypervisor_mode(env)) { + return MMU_PHYS_IDX; + } else if (env->tl > 0) { + return MMU_NUCLEUS_IDX; + } else if (cpu_supervisor_mode(env)) { + return MMU_KERNEL_IDX; + } else { + return MMU_USER_IDX; + } +#endif +} + static void sparc_cpu_reset_hold(Object *obj) { CPUState *s =3D CPU(obj); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 8acacdf0c0..a2bb1038ff 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -24,6 +24,11 @@ #include "qemu/error-report.h" #include "tcg/debug-assert.h" =20 +int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) +{ + return 0; +} + static inline void set_feature(CPUTriCoreState *env, int feature) { env->features |=3D 1ULL << feature; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 99c0ca130f..7d69cef8cc 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -39,6 +39,10 @@ #include "exec/memory.h" #endif =20 +int cpu_mmu_index(CPUXtensaState *env, bool ifetch) +{ + return xtensa_get_cring(env); +} =20 static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) { --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706416998; cv=none; d=zohomail.com; s=zohoarc; b=F66oMszEMDGTZ0agtdpLZHiMxsas9lOcVA4DTI2Lu5lM6135d0HxGf1+7kY+l7NI2xvAdJmukFngKOWYBZxAEpQ9/nBIr/tM6lA9Tj89HJpxdTaaQyCcfPZ8oKVbGQrn8B/YtmO+XV/ke/cYYm1GljWqnD7Sbb/aWdWWgYF6Y5s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706416998; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5fv+pc/a9zag0QS85JnFIDYR2iyAM3R7hb/CB3POH4c=; b=fHyd20AQwmeaDwFWJQX7ro6dm4lrgRgGlP5bzc+qWg9l3Sw/YRkbpCjWv0l+6c0lmH4fLQp/eRFbtFDot83+LtTKqktec/Ek5+7zN1mNFATxwVBiYBJAwh6ha7JQwsMxJW6F0XIFT21PQBi5d6qf/m4TabuvdKLfxsbySiYKMlc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706416998313193.5520760408176; Sat, 27 Jan 2024 20:43:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx0H-0004jW-OB; Sat, 27 Jan 2024 23:42:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0G-0004j0-Da for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:44 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0C-0004Ii-Gi for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:44 -0500 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-290b1e19101so2168716a91.0 for ; Sat, 27 Jan 2024 20:42:40 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416959; x=1707021759; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5fv+pc/a9zag0QS85JnFIDYR2iyAM3R7hb/CB3POH4c=; b=WoUSTUWFUqyt3AppJFDzmnOGUy2EMgcn7BoNYIN7vIb0dAEhuGefSnZGSA44o32b9X l0wIjopagk64YnwVG40SbLsmoIuNeT71vLdpleUJtrqvnxOYAJ9wYBEVGYRO/blU1wWW A/2U+ltPpGJ7e+qXv5dQz1ysVhG/GEF2l5f0MYVviuEVTo2UTCYrUneV8WM2XMvWoOze FacGRVuEKZuRNS6dTGQEhgYlDOuJpf41NIrxsoqb0iVyVJdQPElS/4CZM9ZAcw2GV/Eb bBBSW+SK6fOdv+q0D67vi45E000k5vq+eEwI2yCFHhx92pFeyovPgwM/9S7JdQCfVqvJ UfuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416959; x=1707021759; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5fv+pc/a9zag0QS85JnFIDYR2iyAM3R7hb/CB3POH4c=; b=dRXVC6Zg/oJpSAhSeBjyDReMyo0hsOBZQ/I/NbeNrseCtycd3H3CDuRCem6x+XbSvN 0UVrD2duDN5eDvTLPHZSbvo8Th4F80g2Nv2TeNrYYuoVx75ifpPtRoheZloKJnHVUZCy 2Pap3zpajOPaoX+kIPbCz3jnlXfXEQtZ+s/R88Bso+EdRH/x7awTMEGELn4ogzZE/LYK jXLgWdaFvcsb/prebnOd1/1AKfnHf4zg+VXkSzqVEXfXFrFKgNrQ4V46xb2wlDpo2HB/ nDWmM8zKNhrmzj4212sW8i2UF4Ymdt4chKAXOxzOkBkYnp/sK0pNRXP4o28a0ETjg+B7 5nkA== X-Gm-Message-State: AOJu0YwUf7ScWzQM5xy7rrzYYTVqQ6+OrckUMRKpuFopRMOTtPoEFVD5 Gw0KQOeQE05kj1J27Uco1bGbZZut2jxs3uqUCx8VIFUXR+Fm59+hGs5wbabDQbbgieVbl2Bn14h RnVOETA== X-Google-Smtp-Source: AGHT+IESYEeW59RezkKc+iGAA9IDIOm2uZrJlYov7bJahUW4y4r7EHwAfYV5sxdYZK3V1cHQPiZCPA== X-Received: by 2002:a17:90a:5216:b0:28f:eede:244f with SMTP id v22-20020a17090a521600b0028feede244fmr2617710pjh.36.1706416958939; Sat, 27 Jan 2024 20:42:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 08/33] target: Uninline cpu_get_tb_cpu_state() Date: Sun, 28 Jan 2024 14:41:48 +1000 Message-Id: <20240128044213.316480-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417000708100006 Content-Type: text/plain; charset="utf-8" From: Anton Johansson Required to compile accel/tcg/translate-all.c once for softmmu targets. The function gets quite big for some targets so uninlining makes sense. Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-14-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/exec/cpu-common.h | 3 ++ target/alpha/cpu.h | 11 ------- target/arm/cpu.h | 3 -- target/avr/cpu.h | 18 ----------- target/cris/cpu.h | 10 ------ target/hexagon/cpu.h | 12 ------- target/hppa/cpu.h | 42 ------------------------ target/i386/cpu.h | 14 -------- target/loongarch/cpu.h | 12 ------- target/m68k/cpu.h | 16 --------- target/microblaze/cpu.h | 8 ----- target/mips/cpu.h | 9 ------ target/nios2/cpu.h | 12 ------- target/openrisc/cpu.h | 10 ------ target/ppc/cpu.h | 13 -------- target/riscv/cpu.h | 3 -- target/rx/cpu.h | 9 ------ target/s390x/cpu.h | 24 -------------- target/sh4/cpu.h | 15 --------- target/sparc/cpu.h | 33 ------------------- target/tricore/cpu.h | 12 ------- target/xtensa/cpu.h | 68 --------------------------------------- target/alpha/cpu.c | 11 +++++++ target/avr/cpu.c | 18 +++++++++++ target/cris/cpu.c | 10 ++++++ target/hexagon/cpu.c | 12 +++++++ target/hppa/cpu.c | 42 ++++++++++++++++++++++++ target/i386/cpu.c | 14 ++++++++ target/loongarch/cpu.c | 12 +++++++ target/m68k/cpu.c | 16 +++++++++ target/microblaze/cpu.c | 7 ++++ target/mips/cpu.c | 9 ++++++ target/nios2/cpu.c | 12 +++++++ target/openrisc/cpu.c | 10 ++++++ target/ppc/helper_regs.c | 17 +++++----- target/rx/cpu.c | 9 ++++++ target/s390x/cpu.c | 22 +++++++++++++ target/sh4/cpu.c | 15 +++++++++ target/sparc/cpu.c | 33 +++++++++++++++++++ target/tricore/cpu.c | 12 +++++++ target/xtensa/cpu.c | 68 +++++++++++++++++++++++++++++++++++++++ 41 files changed, 344 insertions(+), 362 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 4724135f30..1a8fad9222 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -44,6 +44,9 @@ unsigned int cpu_list_generation_id_get(void); */ int cpu_mmu_index(CPUArchState *env, bool ifetch); =20 +void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags); + void tcg_iommu_init_notifier_list(CPUState *cpu); void tcg_iommu_free_notifier_list(CPUState *cpu); =20 diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index abf778735a..2b0173577c 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -458,17 +458,6 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, MemTxResult response, uintptr_t retad= dr); #endif =20 -static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *pflags =3D env->flags & ENV_FLAG_TB_MASK; -#ifdef CONFIG_USER_ONLY - *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #ifdef CONFIG_USER_ONLY /* Copied from linux ieee_swcr_to_fpcr. */ static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b0edf2e540..a4ec37c8ed 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3313,9 +3313,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *en= v) } #endif =20 -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); - enum { QEMU_PSCI_CONDUIT_DISABLED =3D 0, QEMU_PSCI_CONDUIT_SMC =3D 1, diff --git a/target/avr/cpu.h b/target/avr/cpu.h index d185d20dcb..284041a87a 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -193,24 +193,6 @@ enum { TB_FLAGS_SKIP =3D 2, }; =20 -static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - uint32_t flags =3D 0; - - *pc =3D env->pc_w * 2; - *cs_base =3D 0; - - if (env->fullacc) { - flags |=3D TB_FLAGS_FULL_ACCESS; - } - if (env->skip) { - flags |=3D TB_FLAGS_SKIP; - } - - *pflags =3D flags; -} - static inline int cpu_interrupts_enabled(CPUAVRState *env) { return env->sregI !=3D 0; diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 3904e5448c..6df53f49c4 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -273,14 +273,4 @@ enum { =20 #include "exec/cpu-all.h" =20 -static inline void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D env->dslot | - (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG - | X_FLAG | PFIX_FLAG)); -} - #endif diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 3eef58fe8f..1d42c33827 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -134,18 +134,6 @@ struct ArchCPU { =20 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) =20 -static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t hex_flags =3D 0; - *pc =3D env->gpr[HEX_REG_PC]; - *cs_base =3D 0; - if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { - hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); - } - *flags =3D hex_flags; -} - typedef HexagonCPU ArchCPU; =20 void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7a181e8f33..b449ceea6b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -314,48 +314,6 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); #define TB_FLAG_PRIV_SHIFT 8 #define TB_FLAG_UNALIGN 0x400 =20 -static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - uint32_t flags =3D env->psw_n * PSW_N; - - /* TB lookup assumes that PC contains the complete virtual address. - If we leave space+offset separate, we'll get ITLB misses to an - incomplete virtual address. This also means that we must separate - out current cpu privilege from the low bits of IAOQ_F. */ -#ifdef CONFIG_USER_ONLY - *pc =3D env->iaoq_f & -4; - *cs_base =3D env->iaoq_b & -4; - flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#else - /* ??? E, T, H, L, B bits need to be here, when implemented. */ - flags |=3D env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); - flags |=3D (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - - *pc =3D hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : = 0), - env->iaoq_f & -4); - *cs_base =3D env->iasq_f; - - /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise = zero - low 32-bits of CS_BASE. This will succeed for all direct branches, - which is the primary case we care about -- using goto_tb within a p= age. - Failure is indicated by a zero difference. */ - if (env->iasq_f =3D=3D env->iasq_b) { - target_long diff =3D env->iaoq_b - env->iaoq_f; - if (diff =3D=3D (int32_t)diff) { - *cs_base |=3D (uint32_t)diff; - } - } - if ((env->sr[4] =3D=3D env->sr[5]) - & (env->sr[4] =3D=3D env->sr[6]) - & (env->sr[4] =3D=3D env->sr[7])) { - flags |=3D TB_FLAG_SR_SAME; - } -#endif - - *pflags =3D flags; -} - target_ulong cpu_hppa_get_psw(CPUHPPAState *env); void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); void cpu_hppa_loaded_fr0(CPUHPPAState *env); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6a5b180ccb..4352d0d163 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2315,20 +2315,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *= env) #include "hw/i386/apic.h" #endif =20 -static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *flags =3D env->hflags | - (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); - if (env->hflags & HF_CS64_MASK) { - *cs_base =3D 0; - *pc =3D env->eip; - } else { - *cs_base =3D env->segs[R_CS].base; - *pc =3D (uint32_t)(*cs_base + env->eip); - } -} - void do_cpu_init(X86CPU *cpu); =20 #define MCE_INJECT_BROADCAST 1 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 64eac07a16..dd375d115f 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -443,18 +443,6 @@ static inline void set_pc(CPULoongArchState *env, uint= 64_t value) #define HW_FLAGS_VA32 0x20 #define HW_FLAGS_EUEN_ASXE 0x40 =20 -static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_= ASXE; - *flags |=3D is_va32(env) * HW_FLAGS_VA32; -} - #include "exec/cpu-all.h" =20 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index aca4aa610b..54dcfe1194 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -601,22 +601,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr = physaddr, vaddr addr, #define TB_FLAGS_TRACE 16 #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) =20 -static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; - if (env->sr & SR_S) { - *flags |=3D TB_FLAGS_MSR_S; - *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; - *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; - } - if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { - *flags |=3D TB_FLAGS_TRACE; - } -} - void dump_mmu(CPUM68KState *env); =20 #endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 446af5dd4c..27ccfc92b4 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -415,14 +415,6 @@ void mb_tcg_init(void); /* Ensure there is no overlap between the two masks. */ QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); =20 -static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); - *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); -} - #if !defined(CONFIG_USER_ONLY) bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 4c9dc09a66..05e9c902d1 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1359,15 +1359,6 @@ void cpu_mips_clock_init(MIPSCPU *cpu); /* helper.c */ target_ulong exception_resume_pc(CPUMIPSState *env); =20 -static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->active_tc.PC; - *cs_base =3D 0; - *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | - MIPS_HFLAG_HWRENA_ULR); -} - /** * mips_cpu_create_with_clock: * @typename: a MIPS CPU type. diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 4164a3432e..d0616723fe 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -286,16 +286,4 @@ FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS =3D=3D 0. */ FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */ FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 =3D=3D 0. */ =20 -static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - unsigned crs =3D FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS); - - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->ctrl[CR_STATUS] & CR_STATUS_U) - | (crs ? 0 : R_TBFLAGS_CRS0_MASK) - | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK); -} - #endif /* NIOS2_CPU_H */ diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b1b7db5cbd..6997c7534e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -351,16 +351,6 @@ static inline void cpu_set_gpr(CPUOpenRISCState *env, = int i, uint32_t val) env->shadow_gpr[0][i] =3D val; } =20 -static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) - | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) - | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); -} - static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) { return (env->sr diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 59587a8aba..3bb10f0188 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2652,19 +2652,6 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xe= r); */ #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) =20 -#ifdef CONFIG_DEBUG_TCG -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); -#else -static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->nip; - *cs_base =3D 0; - *flags =3D env->hflags; -} -#endif - G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception); G_NORETURN void raise_exception_ra(CPUPPCState *env, uint32_t exception, uintptr_t raddr); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bca27278ed..625ffc7622 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -688,9 +688,6 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, ta= rget_ulong vtype) return cpu->cfg.vlen >> (sew + 3 - lmul); } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - void riscv_cpu_update_mask(CPURISCVState *env); bool riscv_cpu_is_32bit(RISCVCPU *cpu); =20 diff --git a/target/rx/cpu.h b/target/rx/cpu.h index c53593d7aa..dcda762212 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -149,15 +149,6 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, = int rte); #define RX_CPU_IRQ 0 #define RX_CPU_FIR 1 =20 -static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); - *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); -} - static inline uint32_t rx_cpu_pack_psw(CPURXState *env) { uint32_t psw =3D 0; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 61c893b1b9..dd5b145539 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -382,31 +382,7 @@ extern const VMStateDescription vmstate_s390_cpu; #define MMU_REAL_IDX 3 =20 #ifdef CONFIG_TCG - #include "tcg/tcg_s390x.h" - -static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - if (env->psw.addr & 1) { - /* - * Instructions must be at even addresses. - * This needs to be checked before address translation. - */ - env->int_pgm_ilen =3D 2; /* see s390_cpu_tlb_fill() */ - tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); - } - *pc =3D env->psw.addr; - *cs_base =3D env->ex_value; - *flags =3D (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; - if (env->cregs[0] & CR0_AFP) { - *flags |=3D FLAG_MASK_AFP; - } - if (env->cregs[0] & CR0_VECTOR) { - *flags |=3D FLAG_MASK_VECTOR; - } -} - #endif /* CONFIG_TCG */ =20 /* PER bits from control register 9 */ diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 9211da6bde..36aff035cf 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -370,19 +370,4 @@ static inline void cpu_write_sr(CPUSH4State *env, targ= et_ulong sr) env->sr =3D sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); } =20 -static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - /* For a gUSA region, notice the end of the region. */ - *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; - *flags =3D env->flags - | (env->fpscr & TB_FLAG_FPSCR_MASK) - | (env->sr & TB_FLAG_SR_MASK) - | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ -#ifdef CONFIG_USER_ONLY - *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #endif /* SH4_CPU_H */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 51856152fa..60c72f06f5 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -749,39 +749,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_HYPER (1 << 7) #define TB_FLAG_ASI_SHIFT 24 =20 -static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - uint32_t flags; - *pc =3D env->pc; - *cs_base =3D env->npc; - flags =3D cpu_mmu_index(env, false); -#ifndef CONFIG_USER_ONLY - if (cpu_supervisor_mode(env)) { - flags |=3D TB_FLAG_SUPER; - } -#endif -#ifdef TARGET_SPARC64 -#ifndef CONFIG_USER_ONLY - if (cpu_hypervisor_mode(env)) { - flags |=3D TB_FLAG_HYPER; - } -#endif - if (env->pstate & PS_AM) { - flags |=3D TB_FLAG_AM_ENABLED; - } - if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { - flags |=3D TB_FLAG_FPU_ENABLED; - } - flags |=3D env->asi << TB_FLAG_ASI_SHIFT; -#else - if (env->psref) { - flags |=3D TB_FLAG_FPU_ENABLED; - } -#endif - *pflags =3D flags; -} - static inline bool tb_fpu_enabled(int tb_flags) { #if defined(CONFIG_USER_ONLY) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 220af69fc2..9537fef2b9 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -253,18 +253,6 @@ FIELD(TB_FLAGS, PRIV, 0, 2) void cpu_state_reset(CPUTriCoreState *s); void tricore_tcg_init(void); =20 -static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t new_flags =3D 0; - *pc =3D env->PC; - *cs_base =3D 0; - - new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, - extract32(env->PSW, 10, 2)); - *flags =3D new_flags; -} - #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU =20 /* helpers.c */ diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 6b8d0636d2..2b6f2bdea7 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -734,74 +734,6 @@ static inline uint32_t xtensa_replicate_windowstart(CP= UXtensaState *env) =20 #include "exec/cpu-all.h" =20 -static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D 0; - *flags |=3D xtensa_get_ring(env); - if (env->sregs[PS] & PS_EXCM) { - *flags |=3D XTENSA_TBFLAG_EXCM; - } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { - target_ulong lend_dist =3D - env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); - - /* - * 0 in the csbase_lend field means that there may not be a loopba= ck - * for any instruction that starts inside this page. Any other val= ue - * means that an instruction that ends at this offset from the page - * start may loop back and will need loopback code to be generated. - * - * lend_dist is 0 when LEND points to the start of the page, but - * no instruction that starts inside this page may end at offset 0, - * so it's still correct. - * - * When an instruction ends at a page boundary it may only start in - * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE - * for the TB that contains this instruction. - */ - if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { - target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; - - *cs_base =3D lend_dist; - if (lbeg_off < 256) { - *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; - } - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && - (env->sregs[LITBASE] & 1)) { - *flags |=3D XTENSA_TBFLAG_LITBASE; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { - if (xtensa_get_cintlevel(env) < env->config->debug_level) { - *flags |=3D XTENSA_TBFLAG_DEBUG; - } - if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { - *flags |=3D XTENSA_TBFLAG_ICOUNT; - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { - *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && - (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { - uint32_t windowstart =3D xtensa_replicate_windowstart(env) >> - (env->sregs[WINDOW_BASE] + 1); - uint32_t w =3D ctz32(windowstart | 0x8); - - *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; - *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, - PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; - } else { - *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; - } - if (env->yield_needed) { - *flags |=3D XTENSA_TBFLAG_YIELD; - } -} - XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk); =20 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index ce18bedcca..ce20a56270 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -34,6 +34,17 @@ int cpu_mmu_index(CPUAlphaState *env, bool ifetch) return ret; } =20 +void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *pflags =3D env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void alpha_cpu_set_pc(CPUState *cs, vaddr value) { AlphaCPU *cpu =3D ALPHA_CPU(cs); diff --git a/target/avr/cpu.c b/target/avr/cpu.c index ffb2234ecf..76dbe56284 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -32,6 +32,24 @@ int cpu_mmu_index(CPUAVRState *env, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } =20 +void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags =3D 0; + + *pc =3D env->pc_w * 2; + *cs_base =3D 0; + + if (env->fullacc) { + flags |=3D TB_FLAGS_FULL_ACCESS; + } + if (env->skip) { + flags |=3D TB_FLAGS_SKIP; + } + + *pflags =3D flags; +} + static void avr_cpu_set_pc(CPUState *cs, vaddr value) { AVRCPU *cpu =3D AVR_CPU(cs); diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 1a8a544e31..6512ef8ee2 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -32,6 +32,16 @@ int cpu_mmu_index(CPUCRISState *env, bool ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } =20 +void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D env->dslot | + (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG + | X_FLAG | PFIX_FLAG)); +} + static void cris_cpu_set_pc(CPUState *cs, vaddr value) { CRISCPU *cpu =3D CRIS_CPU(cs); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index fd8dafad31..b2bbb21b59 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -35,6 +35,18 @@ int cpu_mmu_index(CPUHexagonState *env, bool ifetch) #endif } =20 +void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t hex_flags =3D 0; + *pc =3D env->gpr[HEX_REG_PC]; + *cs_base =3D 0; + if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); + } + *flags =3D hex_flags; +} + static void hexagon_v67_cpu_init(Object *obj) { } static void hexagon_v68_cpu_init(Object *obj) { } static void hexagon_v69_cpu_init(Object *obj) { } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 04f0b927b6..2cc8e43b33 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -41,6 +41,48 @@ int cpu_mmu_index(CPUHPPAState *env, bool ifetch) #endif } =20 +void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags =3D env->psw_n * PSW_N; + + /* TB lookup assumes that PC contains the complete virtual address. + If we leave space+offset separate, we'll get ITLB misses to an + incomplete virtual address. This also means that we must separate + out current cpu privilege from the low bits of IAOQ_F. */ +#ifdef CONFIG_USER_ONLY + *pc =3D env->iaoq_f & -4; + *cs_base =3D env->iaoq_b & -4; + flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#else + /* ??? E, T, H, L, B bits need to be here, when implemented. */ + flags |=3D env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); + flags |=3D (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; + + *pc =3D hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : = 0), + env->iaoq_f & -4); + *cs_base =3D env->iasq_f; + + /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise = zero + low 32-bits of CS_BASE. This will succeed for all direct branches, + which is the primary case we care about -- using goto_tb within a p= age. + Failure is indicated by a zero difference. */ + if (env->iasq_f =3D=3D env->iasq_b) { + target_long diff =3D env->iaoq_b - env->iaoq_f; + if (diff =3D=3D (int32_t)diff) { + *cs_base |=3D (uint32_t)diff; + } + } + if ((env->sr[4] =3D=3D env->sr[5]) + & (env->sr[4] =3D=3D env->sr[6]) + & (env->sr[4] =3D=3D env->sr[7])) { + flags |=3D TB_FLAG_SR_SAME; + } +#endif + + *pflags =3D flags; +} + static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { HPPACPU *cpu =3D HPPA_CPU(cs); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d0adfb381b..da32929558 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -53,6 +53,20 @@ int cpu_mmu_index(CPUX86State *env, bool ifetch) ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; } =20 +void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *flags =3D env->hflags | + (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); + if (env->hflags & HF_CS64_MASK) { + *cs_base =3D 0; + *pc =3D env->eip; + } else { + *cs_base =3D env->segs[R_CS].base; + *pc =3D (uint32_t)(*cs_base + env->eip); + } +} + static void x86_cpu_realizefn(DeviceState *dev, Error **errp); =20 /* Helpers for building CPUID[2] descriptors: */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 316a85bacd..ea4281e177 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -43,6 +43,18 @@ int cpu_mmu_index(CPULoongArchState *env, bool ifetch) #endif } =20 +void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_= ASXE; + *flags |=3D is_va32(env) * HW_FLAGS_VA32; +} + const char * const regnames[32] =3D { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 604cdd5faf..f9dc447897 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -29,6 +29,22 @@ int cpu_mmu_index(CPUM68KState *env, bool ifetch) return (env->sr & SR_S) =3D=3D 0 ? 1 : 0; } =20 +void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; + if (env->sr & SR_S) { + *flags |=3D TB_FLAGS_MSR_S; + *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; + *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; + } + if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { + *flags |=3D TB_FLAGS_TRACE; + } +} + static void m68k_cpu_set_pc(CPUState *cs, vaddr value) { M68kCPU *cpu =3D M68K_CPU(cs); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f8891de41e..4c270e941f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -47,6 +47,13 @@ int cpu_mmu_index(CPUMBState *env, bool ifetch) return MMU_KERNEL_IDX; } =20 +void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); + *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); +} =20 static const struct { const char *name; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 34c0e40d32..4c3e1ec2d9 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -40,6 +40,15 @@ int cpu_mmu_index(CPUMIPSState *env, bool ifetch) return hflags_mmu_index(env->hflags); } =20 +void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->active_tc.PC; + *cs_base =3D 0; + *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | + MIPS_HFLAG_HWRENA_ULR); +} + const char regnames[32][3] =3D { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 976b8c50ad..3e42889ce6 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -32,6 +32,18 @@ int cpu_mmu_index(CPUNios2State *env, bool ifetch) MMU_SUPERVISOR_IDX; } =20 +void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + unsigned crs =3D FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS); + + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D (env->ctrl[CR_STATUS] & CR_STATUS_U) + | (crs ? 0 : R_TBFLAGS_CRS0_MASK) + | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK); +} + static void nios2_cpu_set_pc(CPUState *cs, vaddr value) { Nios2CPU *cpu =3D NIOS2_CPU(cs); diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index fedeba3a3f..fda0dc9470 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -37,6 +37,16 @@ int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) return ret; } =20 +void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); +} + static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index e0b2dcd02e..a506f9823c 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -217,26 +217,27 @@ void hreg_update_pmu_hflags(CPUPPCState *env) env->hflags |=3D hreg_compute_pmu_hflags_value(env); } =20 -#ifdef CONFIG_DEBUG_TCG void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { +#ifdef CONFIG_DEBUG_TCG + uint32_t hflags_rebuilt =3D hreg_compute_hflags_value(env); uint32_t hflags_current =3D env->hflags; - uint32_t hflags_rebuilt; =20 - *pc =3D env->nip; - *cs_base =3D 0; - *flags =3D hflags_current; - - hflags_rebuilt =3D hreg_compute_hflags_value(env); if (unlikely(hflags_current !=3D hflags_rebuilt)) { cpu_abort(env_cpu(env), "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", hflags_current, hflags_rebuilt); } -} + *flags =3D hflags_current; +#else + *flags =3D env->hflags; #endif =20 + *pc =3D env->nip; + *cs_base =3D 0; +} + void cpu_interrupt_exittb(CPUState *cs) { /* diff --git a/target/rx/cpu.c b/target/rx/cpu.c index b9f2bff9ce..de1cc7a5e6 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -31,6 +31,15 @@ int cpu_mmu_index(CPURXState *env, bool ifetch) return 0; } =20 +void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); + *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); +} + static void rx_cpu_set_pc(CPUState *cs, vaddr value) { RXCPU *cpu =3D RX_CPU(cs); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index bbb0b65bee..db1590472e 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -74,6 +74,28 @@ int cpu_mmu_index(CPUS390XState *env, bool ifetch) #endif } =20 +void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + if (env->psw.addr & 1) { + /* + * Instructions must be at even addresses. + * This needs to be checked before address translation. + */ + env->int_pgm_ilen =3D 2; /* see s390_cpu_tlb_fill() */ + tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); + } + *pc =3D env->psw.addr; + *cs_base =3D env->ex_value; + *flags =3D (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; + if (env->cregs[0] & CR0_AFP) { + *flags |=3D FLAG_MASK_AFP; + } + if (env->cregs[0] & CR0_VECTOR) { + *flags |=3D FLAG_MASK_VECTOR; + } +} + #ifndef CONFIG_USER_ONLY static bool is_early_exception_psw(uint64_t mask, uint64_t addr) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index e99fba7778..eb7eb6f30a 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -41,6 +41,21 @@ int cpu_mmu_index(CPUSH4State *env, bool ifetch) } } =20 +void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + /* For a gUSA region, notice the end of the region. */ + *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; + *flags =3D env->flags + | (env->fpscr & TB_FLAG_FPSCR_MASK) + | (env->sr & TB_FLAG_SR_MASK) + | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ +#ifdef CONFIG_USER_ONLY + *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void superh_cpu_set_pc(CPUState *cs, vaddr value) { SuperHCPU *cpu =3D SUPERH_CPU(cs); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index e2b1feac2f..99d57cc209 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -57,6 +57,39 @@ int cpu_mmu_index(CPUSPARCState *env, bool ifetch) #endif } =20 +void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags; + *pc =3D env->pc; + *cs_base =3D env->npc; + flags =3D cpu_mmu_index(env, false); +#ifndef CONFIG_USER_ONLY + if (cpu_supervisor_mode(env)) { + flags |=3D TB_FLAG_SUPER; + } +#endif +#ifdef TARGET_SPARC64 +#ifndef CONFIG_USER_ONLY + if (cpu_hypervisor_mode(env)) { + flags |=3D TB_FLAG_HYPER; + } +#endif + if (env->pstate & PS_AM) { + flags |=3D TB_FLAG_AM_ENABLED; + } + if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { + flags |=3D TB_FLAG_FPU_ENABLED; + } + flags |=3D env->asi << TB_FLAG_ASI_SHIFT; +#else + if (env->psref) { + flags |=3D TB_FLAG_FPU_ENABLED; + } +#endif + *pflags =3D flags; +} + static void sparc_cpu_reset_hold(Object *obj) { CPUState *s =3D CPU(obj); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index a2bb1038ff..dff88184c9 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -29,6 +29,18 @@ int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) return 0; } =20 +void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t new_flags =3D 0; + *pc =3D env->PC; + *cs_base =3D 0; + + new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, + extract32(env->PSW, 10, 2)); + *flags =3D new_flags; +} + static inline void set_feature(CPUTriCoreState *env, int feature) { env->features |=3D 1ULL << feature; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 7d69cef8cc..dfe0ff5c98 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -44,6 +44,74 @@ int cpu_mmu_index(CPUXtensaState *env, bool ifetch) return xtensa_get_cring(env); } =20 +void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D 0; + *flags |=3D xtensa_get_ring(env); + if (env->sregs[PS] & PS_EXCM) { + *flags |=3D XTENSA_TBFLAG_EXCM; + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { + target_ulong lend_dist =3D + env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); + + /* + * 0 in the csbase_lend field means that there may not be a loopba= ck + * for any instruction that starts inside this page. Any other val= ue + * means that an instruction that ends at this offset from the page + * start may loop back and will need loopback code to be generated. + * + * lend_dist is 0 when LEND points to the start of the page, but + * no instruction that starts inside this page may end at offset 0, + * so it's still correct. + * + * When an instruction ends at a page boundary it may only start in + * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE + * for the TB that contains this instruction. + */ + if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { + target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; + + *cs_base =3D lend_dist; + if (lbeg_off < 256) { + *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; + } + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && + (env->sregs[LITBASE] & 1)) { + *flags |=3D XTENSA_TBFLAG_LITBASE; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { + if (xtensa_get_cintlevel(env) < env->config->debug_level) { + *flags |=3D XTENSA_TBFLAG_DEBUG; + } + if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { + *flags |=3D XTENSA_TBFLAG_ICOUNT; + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { + *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && + (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { + uint32_t windowstart =3D xtensa_replicate_windowstart(env) >> + (env->sregs[WINDOW_BASE] + 1); + uint32_t w =3D ctz32(windowstart | 0x8); + + *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; + *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, + PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; + } else { + *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; + } + if (env->yield_needed) { + *flags |=3D XTENSA_TBFLAG_YIELD; + } +} + static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) { XtensaCPU *cpu =3D XTENSA_CPU(cs); --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417213; cv=none; d=zohomail.com; s=zohoarc; b=Eo/KhPWZXP6OvtDLEe6ZTir9A/ARhVEGz+gai3h34E5uKaEuij++XNi7DgL47b4CW0J8kw8F3MCobD2rtAeJTqTGSBWThtnx7rODZq/ZD4WwX1LFMI+LVtHDuaNEM67UYialTM7tjkpy4hCc3rLt/6gsND0v4QjZGMWw4NtloXA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417213; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=b//53eqNBjSFpOfVle7vTtty4ZHIEf38Wv0KnQlUNkk=; b=Y1txfxuKz7LiE0A2pVJjHOJEu71dUXkd3F6aKyDXlph1J4hwwH8YQeviP/XHcwydjQ9boipd1QzC4W2mGiqXZWKczwkNxuBEfigdBJr5BnqH22kUgCrK6gnCwO/vh70f+VVDgLFmT3DyJZIg5uCF6Xyti8vJXHVBNKzby9EobNw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417213191660.8899147520121; Sat, 27 Jan 2024 20:46:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx0H-0004jE-5z; Sat, 27 Jan 2024 23:42:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0G-0004it-4p for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:44 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0E-0004Is-JU for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:43 -0500 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-2906dffd8ddso1350739a91.3 for ; Sat, 27 Jan 2024 20:42:42 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416961; x=1707021761; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b//53eqNBjSFpOfVle7vTtty4ZHIEf38Wv0KnQlUNkk=; b=MmtVTpvtDxcbcobH5GUe3J/pBqYp66zXh69JcCoVzSq4aJKLnWxrNkwgaH0MYObcJl 9rv8H9/v8+k6gGO6yjH+Gm7Dg/DA7ppJGyS2O1Fst0wY4H2NrVrXRAcedrTztO+dG/gm v+mX2YbAYgPRC9GMn0qJmezmJuswZx8Ao93VLormZWHF3js67tcmrcxxg6LWUa2jzKWY Ag55kz/0sABoq+Glap81JqWeqyVqX/yNP6V5Cr+0yPMocPWcQcvdpp7EAhcNQvJ4aMUI T/ylokk59oz6TxJbiFd8jlJR2Ux5KOfxubXWJUwduDZyVDwvq0KxeY/lJ+P/gAfddw19 rDnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416961; x=1707021761; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b//53eqNBjSFpOfVle7vTtty4ZHIEf38Wv0KnQlUNkk=; b=RP5uSACYuzjuUWGjQYeTwyhQxnVufiI0Tk/aJdzg+eDOPxvyz+sihwaGnAmwXyUsu0 TOd6mQJcKFoPY3Ocx2USqRwk5kI8XNlgxqfvozcq3dijn5rklZ46A5p3sCpwNlE69DGx kPMxA1fo7AwrpqSPymGon8Hv6hbY0ugs5DKZsKQQUjC+5xaLL1+yv2PVBMNXSkYRa7t4 JVfvrvMgU6s44HOxcFFRvUbc9FCoZXAnBQmwJR8O+yFVZgnT3FWNkMxLjGOuOyancu9y GTSexaeOxoACRzeCHlOnD3SaEngCUbJ/VCvFEeXtGKcDNcdlKRGA7N3HCy/7jqRHPYf0 nHgA== X-Gm-Message-State: AOJu0YxMHjnpZ2MQYiePWmUH9sNCu/Qk1S+St35RHT24QeHB2YEjUTq3 5II8cjuJG0Bb/05VLFVlsGRfZlRvl2qL7L41DDl0DeQgq7hAEIgNBdWZtq/hVmh3GQaGT17lsRk oGUedDA== X-Google-Smtp-Source: AGHT+IEDzNoVLsrSlyIQolz0PJtuRawBP2dV4OJISgIxJ8gJKLPsVQP10W7Y/PMYiRkjcjxVA18vbg== X-Received: by 2002:a17:90b:1207:b0:28e:7a18:4e4a with SMTP id gl7-20020a17090b120700b0028e7a184e4amr1514464pjb.81.1706416961361; Sat, 27 Jan 2024 20:42:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 09/33] include/exec: Move PAGE_* macros to common header Date: Sun, 28 Jan 2024 14:41:49 +1000 Message-Id: <20240128044213.316480-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417215019100003 Content-Type: text/plain; charset="utf-8" From: Anton Johansson These don't vary across targets and are used in soon-to-be common code (cputlb.c). Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-15-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 24 ------------------------ include/exec/cpu-common.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 24 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 5340907cfd..edee87d3f4 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -171,34 +171,10 @@ extern const TargetPageBits target_page; =20 #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) =20 -/* same as PROT_xxx */ -#define PAGE_READ 0x0001 -#define PAGE_WRITE 0x0002 -#define PAGE_EXEC 0x0004 -#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) -#define PAGE_VALID 0x0008 -/* - * Original state of the write flag (used when tracking self-modifying cod= e) - */ -#define PAGE_WRITE_ORG 0x0010 -/* - * Invalidate the TLB entry immediately, helpful for s390x - * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs= () - */ -#define PAGE_WRITE_INV 0x0020 -/* For use with page_set_flags: page is being replaced; target_data cleare= d. */ -#define PAGE_RESET 0x0040 -/* For linux-user, indicates that the page is MAP_ANON. */ -#define PAGE_ANON 0x0080 - #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ #define PAGE_RESERVED 0x0100 #endif -/* Target-specific bits that will be used via page_get_flags(). */ -#define PAGE_TARGET_1 0x0200 -#define PAGE_TARGET_2 0x0400 - /* * For linux-user, indicates that the page is mapped with the same semanti= cs * in both guest and host. diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 1a8fad9222..ba10351576 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -219,4 +219,34 @@ G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, ui= ntptr_t pc); G_NORETURN void cpu_loop_exit(CPUState *cpu); G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); =20 +/* same as PROT_xxx */ +#define PAGE_READ 0x0001 +#define PAGE_WRITE 0x0002 +#define PAGE_EXEC 0x0004 +#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) +#define PAGE_VALID 0x0008 +/* + * Original state of the write flag (used when tracking self-modifying cod= e) + */ +#define PAGE_WRITE_ORG 0x0010 +/* + * Invalidate the TLB entry immediately, helpful for s390x + * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs= () + */ +#define PAGE_WRITE_INV 0x0020 +/* For use with page_set_flags: page is being replaced; target_data cleare= d. */ +#define PAGE_RESET 0x0040 +/* For linux-user, indicates that the page is MAP_ANON. */ +#define PAGE_ANON 0x0080 + +/* Target-specific bits that will be used via page_get_flags(). */ +#define PAGE_TARGET_1 0x0200 +#define PAGE_TARGET_2 0x0400 + +/* + * For linux-user, indicates that the page is mapped with the same semanti= cs + * in both guest and host. + */ +#define PAGE_PASSTHROUGH 0x0800 + #endif /* CPU_COMMON_H */ --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417100; cv=none; d=zohomail.com; s=zohoarc; b=Wy33knUqu8Hc9Md5XleOCLu7Lm8Vs7wHGbbEyiHUL6IXwEk30oDjXVVb0PTrb9EWxtOHuu5UesmpEhneRqPWBtCCoOfqRogGrMCxvFiBk/AnsZNiZqgpJSVYnrNPttl3E0L3UkKDhyyTjjztJEfkWGD53Hf7IAqe2toqfv54jDM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417100; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=XtUAEvtZlEFe6xSkMZOBhFgppz0gGYIST8afKDqnszc=; b=j9FcfbY0TNA6UREc7Cclsl17Skg64X4AwK2W22tnrFZc4a9YwJyOHkp84SpRSvbmSZRcNgdwDCob5JS1OSmapvC0TByz2J5zeLP9Mm4c9oeNLCt2qr71Xk0pKXoYzxUT0OKu27RkYah/3Xc9mGCD5AVQWeeIN2npt3pDjr8SjhU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417100766705.855982719591; Sat, 27 Jan 2024 20:45:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx0K-0004jy-Ah; Sat, 27 Jan 2024 23:42:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0I-0004jm-IX for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:46 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0H-0004J4-0J for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:46 -0500 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1d746ce7d13so15818885ad.0 for ; Sat, 27 Jan 2024 20:42:44 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416964; x=1707021764; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XtUAEvtZlEFe6xSkMZOBhFgppz0gGYIST8afKDqnszc=; b=crpLBow+lgRWgjMyPIqbGTsIDiIk4vLB7QRA61wclq/DT6BiTJzyK4n3lp4buvhOQ8 oEJYsmqVrvAE1xe64tNAk03SlWvy/HwJmBnMnwxqcrwd+fAPXDjQzbMK0yS90lRomnEp Zgmz7J6gwwfRy2IppW71SYGXaQgRbzzOoGrJ0v5BawcnUyflt8ChyK4PTqJ3c1JZV750 wNrGV44tt0LCklw0YGXDaVSwlKv69hgVOUuEvd1wa2SJ/JJLKUg5tGz4kVSOftqdGE80 X1zPm3j+n0w3WjqMWayzlRD9QZOZMNpq0vQXLG7Uiy0qq+EBXsZQa9yHTaF1GtViwnQZ 6XGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416964; x=1707021764; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XtUAEvtZlEFe6xSkMZOBhFgppz0gGYIST8afKDqnszc=; b=G4tyRWFSLea60CPUwiL4Dql7Hpfv7maTYnb3P0dN1XJ0VMAtT6IPvDG0DTnbdMNxfQ rFfOMgDLUAhj2Ss8QIVhhdj6NDNVKCO3WQ8L4vr1kHIMMJHLSdBVnhCrbuBF6mYYO7mE zXtFMFU3EDwU/d6yLM93nicNdTPudoPoFy7+r8zbsHl/VEPyJFmrJrPzWjgwnpLSrGMD 0AZZLMLvYUgE+lADb5ieEQ13293jGqqB3nW0JdvfFBjkWDOx45G6AHgf1NI/zjfLEmov 76pdoZyoVVrxsi8FaCtC4SBhAm/X9bTXKPWw4TS/XR+m0E/E9kzcjYcA+uFe+LLiQXyb W80g== X-Gm-Message-State: AOJu0Yx+ItyTi4WQLrkBwUtdWe5HN5WhVn8QZYBeLJbTMytzs8ROYF01 nWKxcSmc8SbS+S/vnj6BUaHhZ+pm5BZzs95JO4cGE89faWZSP7yCEjcn0hFQEEjAGkjwCiShu2S 2f/UkRQ== X-Google-Smtp-Source: AGHT+IEqoXUMbDRfq9zvPJMnm+rGsQYvSdXTOb7OoHIYYKSxF0pbRiw3MmBjRnVMzTbZX+FFHfKx8A== X-Received: by 2002:a17:902:c412:b0:1d8:d6c1:fcb9 with SMTP id k18-20020a170902c41200b001d8d6c1fcb9mr139840plk.100.1706416963770; Sat, 27 Jan 2024 20:42:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 10/33] include/exec: Move cpu_*()/cpu_env() to common header Date: Sun, 28 Jan 2024 14:41:50 +1000 Message-Id: <20240128044213.316480-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417102760100007 Content-Type: text/plain; charset="utf-8" From: Anton Johansson Functions are target independent. Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-17-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-all.h | 25 ------------------------- include/exec/cpu-common.h | 26 ++++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 25 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index edee87d3f4..8501a33dbf 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -384,33 +384,8 @@ static inline bool tlb_hit(uint64_t tlb_addr, vaddr ad= dr) =20 #endif /* !CONFIG_USER_ONLY */ =20 -/* accel/tcg/cpu-exec.c */ -int cpu_exec(CPUState *cpu); - /* Validate correct placement of CPUArchState. */ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) !=3D 0); QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) !=3D sizeof(CPUState)); =20 -/** - * env_archcpu(env) - * @env: The architecture environment - * - * Return the ArchCPU associated with the environment. - */ -static inline ArchCPU *env_archcpu(CPUArchState *env) -{ - return (void *)env - sizeof(CPUState); -} - -/** - * env_cpu(env) - * @env: The architecture environment - * - * Return the CPUState associated with the environment. - */ -static inline CPUState *env_cpu(CPUArchState *env) -{ - return (void *)env - sizeof(CPUState); -} - #endif /* CPU_ALL_H */ diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index ba10351576..7e1a4afad8 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -7,6 +7,7 @@ #ifndef CONFIG_USER_ONLY #include "exec/hwaddr.h" #endif +#include "hw/core/cpu.h" =20 #define EXCP_INTERRUPT 0x10000 /* async interruption */ #define EXCP_HLT 0x10001 /* hlt instruction reached */ @@ -249,4 +250,29 @@ G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, u= intptr_t pc); */ #define PAGE_PASSTHROUGH 0x0800 =20 +/* accel/tcg/cpu-exec.c */ +int cpu_exec(CPUState *cpu); + +/** + * env_archcpu(env) + * @env: The architecture environment + * + * Return the ArchCPU associated with the environment. + */ +static inline ArchCPU *env_archcpu(CPUArchState *env) +{ + return (void *)env - sizeof(CPUState); +} + +/** + * env_cpu(env) + * @env: The architecture environment + * + * Return the CPUState associated with the environment. + */ +static inline CPUState *env_cpu(CPUArchState *env) +{ + return (void *)env - sizeof(CPUState); +} + #endif /* CPU_COMMON_H */ --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417191; cv=none; d=zohomail.com; s=zohoarc; b=YpcHs3fIVfq7z+H1PrjQ+GioQ4K89Yc7vYMouR5nrhKlNeVNAtThluWRpH7T4tj/85R/vEjzMOs3P9HCzi9RYy/wkbrJtnUrvvQFBFTZ7/iY8ev4BJEn2kwzKCE3oLKS7HDw0pjf8TXzwC+pgSt5jCKye3a6W9idHqb8J48+RZw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417191; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0IsJCYKuWrursPA6kPyaSh6Iig/if/7dsXp1H2oDJMs=; b=d+QZl3MGDiWSMW6Axf/ZE2/APibTDqAzaFg38gNyOxhQhud61JtMyTKPEJhYQk2YcKwd55FsVw9QIHBwLq5UsGKcEL5wmz0eMGrsbjANfJ4Zlcf7Tuv6fHtKdMSjUE/cv4hra//Yw5z2LSDNMoKb1S1IrRGgC4axtz8zVUycO/k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417191198248.47663846508465; Sat, 27 Jan 2024 20:46:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx0M-0004kS-4m; Sat, 27 Jan 2024 23:42:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0K-0004kI-Pg for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:48 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0J-0004JL-9j for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:48 -0500 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-290483f8c7bso1322954a91.3 for ; Sat, 27 Jan 2024 20:42:46 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416966; x=1707021766; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0IsJCYKuWrursPA6kPyaSh6Iig/if/7dsXp1H2oDJMs=; b=BaOPrRv980yaVACOJTE4DnWzuGl/0lVF+rWL52lIIC7JNOGVEee0Ckvz8Kl7p5tjxh Itd9ZlY6pC3z0bdp63LBFXwa7jIpHQYBjuAoFpiDBq5W28cB099b4Zo/H8AiJdyuzV/x Ilq0T/BDp2Eq7w0DvxhfhZe2WFrgNBlXgXG8fos3ZEQJwSjuusqQUG4GqIa5ajjBVKfs u2oyhz7iJ8wZw4wSyRBC2hZCvzWzYNNZIsc4VENuaqkqhdDBIZSxtW9hjYHxIPRigt2D /MjpzO5m2bgEBzhtgwgfPlcUJ8TQlg2LJq+8j3bgaSrm9aOfAvJnP/etTPx9keNBcnyK 46wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416966; x=1707021766; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0IsJCYKuWrursPA6kPyaSh6Iig/if/7dsXp1H2oDJMs=; b=qX17bqvGgCKkkKlIbA0TkwsMHItEifTGm64THynG/Lul+ELT+1AL6Ymcj76CcLczhA kwwDfw9GrJjMOO7oEF0nIeOec6lo0myeLyNlXSqzZemZVJryibDX++OQ95XfbBiDoJEQ 0fo5vf31hNxXXAtkJ4InllqLb7vJ7QGxGbb48glPr1IRP3vf61yMJm7Auky54U+0dauc lWjs+3qJOLKVhpg+MTillGcOqqyG21N3tWDhYDAU7nCSYAQWRPN+PbsdN5qTkna4l/WP zx8Z5QhOM5vc6PyRJePOlcPvEVk7jLXnZJd0PV2ar9bj2cmHJvP2j+fr/PRloQcuWyd2 0kAQ== X-Gm-Message-State: AOJu0YzH2gntopdIEUkwUKMohly5kzSC4Alf77DF8v8i+ub29+iQUFuG 1Z3bSC9XMtC+QSXxeNo5JQgDpk/4jifQ9aasJY5cCN6uKA4pHWmMJFPVN1IN5V+n3hUpJO11TuW 6KIEsrg== X-Google-Smtp-Source: AGHT+IGDsF25tuBpf3hP1SjogbVqRI7bd1LE/jHwl5HLdeowmtarHEL465tLSaCdsLT6mrc7Wfwr+w== X-Received: by 2002:a17:90a:5d07:b0:293:e0bf:39ae with SMTP id s7-20020a17090a5d0700b00293e0bf39aemr1659675pji.59.1706416965937; Sat, 27 Jan 2024 20:42:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 11/33] include/hw/core: Move do_interrupt in TCGCPUOps Date: Sun, 28 Jan 2024 14:41:51 +1000 Message-Id: <20240128044213.316480-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417192946100003 Content-Type: text/plain; charset="utf-8" From: Anton Johansson The ifdef out of which it is moved is not quite right: do_interrupt is only needed for system mode. Move it to the top of a different ifdef block, which preserves its position within the structure for that case. Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-18-anjo@rev.ng> [rth: Split from a larger patch and simplified.] Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 479713a36e..d6fe55d471 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -58,11 +58,6 @@ struct TCGCPUOps { * cpu execution loop (hack for x86 user mode). */ void (*fake_user_interrupt)(CPUState *cpu); -#else - /** - * @do_interrupt: Callback for interrupt handling. - */ - void (*do_interrupt)(CPUState *cpu); #endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ #ifdef CONFIG_USER_ONLY /** @@ -114,6 +109,8 @@ struct TCGCPUOps { void (*record_sigbus)(CPUState *cpu, vaddr addr, MMUAccessType access_type, uintptr_t ra); #else + /** @do_interrupt: Callback for interrupt handling. */ + void (*do_interrupt)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); /** --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417153; cv=none; d=zohomail.com; s=zohoarc; b=hQiWteaE0faFKGNtR+2GwwAoV4bwJTKjYqpeUjToYOFYKTxVpIbUsXdvpbRc3qT4CkymTS7LgzXhudyahVRdNORZgxqYoEx8u7xkVY1YeYsh9btrYdJ0OlkvHn+bysYAmyOrC9J7/eC01EAQuwyCUzVK6Ai0ho22jI7KlvG2Y0w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417153; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=o1cRBtAgGqadhUih0VNs9If35/tfCXiaB3lrOMREblM=; b=gfuYIuw9aSk4d1H/w4aXcgS9kC8nf1Ivizz/zAAG4/EMGmKv7/+Nq5rJeF5M+lEC9DO/lvLCFOmoMo6nbaoiKACHKDr8ub25DVgAAOtrBZr8ZCSdxTrI8S5uP5sBEvdbcxnT+JcPibvdFdZNt3/kckdEA8sKgxpAWw3b2myoL74= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417153513719.0241507434387; Sat, 27 Jan 2024 20:45:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx0O-0004lc-Rw; Sat, 27 Jan 2024 23:42:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0M-0004kj-SR for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:50 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0L-0004Ja-CF for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:50 -0500 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-290b9f83037so1064998a91.1 for ; Sat, 27 Jan 2024 20:42:48 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416968; x=1707021768; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o1cRBtAgGqadhUih0VNs9If35/tfCXiaB3lrOMREblM=; b=kYnh0zd0TQiYg0Z6U6BJ80akl4v3ALjHiZGHQlJaeMIVSh3dU6mnQCFmRWQqazty0H hvBpeLYTF+aAt778g2KqPSNsYTKW3fIsVVfchUBan7BYxJljeGwPY1recRK2jkarsETM q59qVySUNJpny+HiCnWsC1RMEl5YzRM+rsXHJJsOIx3YxI3AVdKBc9jd2q/G+SIVRWa+ q0IpG2pUkGYH48nAxfUaW/O+X1dEscrRg22t56GkctjRc8eotRl/wbu7jX+gYBtB9fGr VbH2rHmXeHV4zjnLniv+bhZ1SAwZUnTz6gqOt63Esv4i7OnUGt9romA511l+Aq8CM0Sj 3VcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416968; x=1707021768; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o1cRBtAgGqadhUih0VNs9If35/tfCXiaB3lrOMREblM=; b=rQ+K0s89PD5SWbD1Htrla7VjJOOvmR5CjRijPGvAIkD19YxIz9nWAkkzaIgxo1Wh0G 9FjfXLYPrGm8u3MQaZD6uNoNccHpuQEofiV3ZJpTyG6AIenMEKbwvkEDN6jvoW5FumKG rJX62uPN21Ao0fvocS40Oo7dq9yX3Sg1rXjDS861lgj+J1ZERtadFkdDWoqHXgkKRqVh NMkfjOcobdXr8xtjhICIt5Drw1lXn6aQc8MqVX7wItTEEaB3Ys6xwjpmMcfUV0LRGRfa a1HoHXUwEL93fdhN9ixHfv+R5HlWJHhjY6DXOqlYYQ75badGMT/nk6KWnyDFBFiBRJ+Y 4FYQ== X-Gm-Message-State: AOJu0YxfsFf65wSUYBGhd5cE/Y3GkZbTc8M0Gj5ACZgG4lmfM2HDr8t3 Bteb3Tj0CObfzWW4u34KpkVGTXJRtMmtO+/+Oc+7Qmtr5vSi8ZRfRfhC/IouIyXOW7w0p7NmPRo kel05tg== X-Google-Smtp-Source: AGHT+IEijjP8ZPixMaWeIou+bNJAqOExYJCOmhVTN94HZ3VJpWf5ca85o/beBWx4yai3j2f3fsKxWw== X-Received: by 2002:a17:90b:1e05:b0:28d:afe2:1013 with SMTP id pg5-20020a17090b1e0500b0028dafe21013mr2662049pjb.34.1706416968059; Sat, 27 Jan 2024 20:42:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 12/33] include/hw/core: Remove i386 conditional on fake_user_interrupt Date: Sun, 28 Jan 2024 14:41:52 +1000 Message-Id: <20240128044213.316480-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417154872100003 Content-Type: text/plain; charset="utf-8" From: Anton Johansson Always include fake_user_interrupt in user-only build, despite only being used for i386. This will enable cpu-exec.c to be compiled only once. Signed-off-by: Anton Johansson Message-ID: <20240119144024.14289-18-anjo@rev.ng> [rth: Split out of a larger patch; remove TARGET_I386 conditional.] Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index d6fe55d471..3ed279836f 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -50,7 +50,7 @@ struct TCGCPUOps { void (*debug_excp_handler)(CPUState *cpu); =20 #ifdef NEED_CPU_H -#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386) +#ifdef CONFIG_USER_ONLY /** * @fake_user_interrupt: Callback for 'fake exception' handling. * @@ -58,8 +58,7 @@ struct TCGCPUOps { * cpu execution loop (hack for x86 user mode). */ void (*fake_user_interrupt)(CPUState *cpu); -#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ -#ifdef CONFIG_USER_ONLY + /** * record_sigsegv: * @cpu: cpu context --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417135; cv=none; d=zohomail.com; s=zohoarc; b=USbFCNKKF2Nim6o5toE8f3p/pX0d2Bm48OVNIbVhYlOPINCOwxi3QmGmaWCi4x5eTaIvTAgY+zTQEzZvPvYPrz0qohQcpgoUL0oAwQRHkv5o/L5iNthk+VVzuw92XNk7v/Fu0ikQn5yozFmmo4olpjB1t4KJJnmgI6Mo9BTlqfg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417135; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=50eKL1UP4eaaSsdfVAm5gMAL4OibGGuLebFEQUtStnM=; b=bJ0xY3A1J5cS6QIuiyclm2PI/Cly32ciBMQRKaL6EOv/NygrD7Xyrk64nW1uDqIP4mcajdjrkvR5jMqBmhMquU4FXTWZb9I2ob+duCPE3uBWCkXa788naYkg9Qen7CdDC2eat6FYQhsVaogEIs5k2aaB4g9yMXOBz75ncn474WY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417135766869.1589365216604; Sat, 27 Jan 2024 20:45:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx0Q-0004my-Dt; Sat, 27 Jan 2024 23:42:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0P-0004mj-0K for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:53 -0500 Received: from mail-qt1-x82b.google.com ([2607:f8b0:4864:20::82b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0N-0004Jq-9G for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:52 -0500 Received: by mail-qt1-x82b.google.com with SMTP id d75a77b69052e-42993124fa1so17148271cf.3 for ; Sat, 27 Jan 2024 20:42:50 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416970; x=1707021770; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=50eKL1UP4eaaSsdfVAm5gMAL4OibGGuLebFEQUtStnM=; b=hg3VOZS1o4Ryc53UNyUCUH1VAsTJ4Z62+DZrcgT1zGGYNv2JD42GCSH1SrC1e0gFAG /g4D3IaEtfYeD4AjtUUbBIGQqv1ij1QgOYYVrb/rY4I8FP9TaKqQnoiSyc50waKu/7CF 0E8ikzFlp/COpowCOjEEVLtfoHKPtZuto64mfz7xzEHDgihPg6cIb8ZWmovv+aR5rijY r7kWGuheyUUSOkb4rkruzf9lG+xxRpg92DWJPP0ZmQqu30nIUwq1GSarjYcTifIwMQiB tIrMrLhU0ngurf4lyLWeKgeLX6CaDDE4VoOUOY9WYR5kflYskKwnBWkjKd2ebZ3znYOb WYKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416970; x=1707021770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=50eKL1UP4eaaSsdfVAm5gMAL4OibGGuLebFEQUtStnM=; b=q2l9mTyFlM4bL0Ae+tZiJJS3oZZ356Tr/eLU+56RWpvzY//8BR7UBl39kW3I9XUKxS F7M39m8GV9FkJRcQbxhyUdWdfE9JHDwLEiY4wCG8Hin9H6yYibC+ZinBfRndGUyzcPQo pVMxW4A7JGyCYS31WJheo+pZOd73JG1ToSH3QWbNF/A3QFXSX4mhpMtEztsp3VD+kiAv oxcW/yjifcQBQ1kJo+GQit7vfsaeJCOLrQpYnChmog+oYW/DELWsCC4+MyiQuby2EZBZ wKzM+kYITMvg9Ur4orKjBGLawB3INtsJhwchxsViS6dTdlSYTJ9hQJSsZeyHcK25SEZW dU0g== X-Gm-Message-State: AOJu0YwlgrAtDQPxuI4ux+WU0Bm3lmHhYxa5zbTA8ILKARGm6lik+iUk Tl9Cp9KdnoeMlI7PU3VNmwv7hp8qUyRX+RXE9fHKujBsRpXt9DP8hjq61t49tonumIXr3jfFnpF vrhd2Jw== X-Google-Smtp-Source: AGHT+IGyW1LUPib3EQWfTd+FngMbcPzvs0CSNrLwSkTzui9Re7Tjv+TTgB++thF7EkeqHNu98tuBGw== X-Received: by 2002:ac8:5795:0:b0:42a:85b1:9be2 with SMTP id v21-20020ac85795000000b0042a85b19be2mr3867274qta.83.1706416970383; Sat, 27 Jan 2024 20:42:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich Subject: [PATCH 13/33] linux-user: Allow gdbstub to ignore page protection Date: Sun, 28 Jan 2024 14:41:53 +1000 Message-Id: <20240128044213.316480-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82b; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417136858100001 Content-Type: text/plain; charset="utf-8" From: Ilya Leoshkevich gdbserver ignores page protection by virtue of using /proc/$pid/mem. Teach qemu gdbstub to do this too. This will not work if /proc is not mounted; accept this limitation. One alternative is to temporarily grant the missing PROT_* bit, but this is inherently racy. Another alternative is self-debugging with ptrace(POKE), which will break if QEMU itself is being debugged - a much more severe limitation. Signed-off-by: Ilya Leoshkevich Reviewed-by: Richard Henderson Message-Id: <20240109230808.583012-2-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- cpu-target.c | 76 +++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 61 insertions(+), 15 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index f6e07c3deb..c4e2169ab1 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -382,6 +382,9 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, vaddr l, page; void * p; uint8_t *buf =3D ptr; + ssize_t written; + int ret =3D -1; + int fd =3D -1; =20 while (len > 0) { page =3D addr & TARGET_PAGE_MASK; @@ -389,30 +392,73 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, if (l > len) l =3D len; flags =3D page_get_flags(page); - if (!(flags & PAGE_VALID)) - return -1; + if (!(flags & PAGE_VALID)) { + goto out_close; + } if (is_write) { - if (!(flags & PAGE_WRITE)) - return -1; + if (flags & PAGE_WRITE) { + /* XXX: this code should not depend on lock_user */ + p =3D lock_user(VERIFY_WRITE, addr, l, 0); + if (!p) { + goto out_close; + } + memcpy(p, buf, l); + unlock_user(p, addr, l); + } else { + /* Bypass the host page protection using ptrace. */ + if (fd =3D=3D -1) { + fd =3D open("/proc/self/mem", O_WRONLY); + if (fd =3D=3D -1) { + goto out; + } + } + /* + * If there is a TranslationBlock and we weren't bypassing= the + * host page protection, the memcpy() above would SEGV, + * ultimately leading to page_unprotect(). So invalidate t= he + * translations manually. Both invalidation and pwrite() m= ust + * be under mmap_lock() in order to prevent the creation of + * another TranslationBlock in between. + */ + mmap_lock(); + tb_invalidate_phys_range(addr, addr + l - 1); + written =3D pwrite(fd, buf, l, (off_t)g2h_untagged(addr)); + mmap_unlock(); + if (written !=3D l) { + goto out_close; + } + } + } else if (flags & PAGE_READ) { /* XXX: this code should not depend on lock_user */ - if (!(p =3D lock_user(VERIFY_WRITE, addr, l, 0))) - return -1; - memcpy(p, buf, l); - unlock_user(p, addr, l); - } else { - if (!(flags & PAGE_READ)) - return -1; - /* XXX: this code should not depend on lock_user */ - if (!(p =3D lock_user(VERIFY_READ, addr, l, 1))) - return -1; + p =3D lock_user(VERIFY_READ, addr, l, 1); + if (!p) { + goto out_close; + } memcpy(buf, p, l); unlock_user(p, addr, 0); + } else { + /* Bypass the host page protection using ptrace. */ + if (fd =3D=3D -1) { + fd =3D open("/proc/self/mem", O_RDONLY); + if (fd =3D=3D -1) { + goto out; + } + } + if (pread(fd, buf, l, (off_t)g2h_untagged(addr)) !=3D l) { + goto out_close; + } } len -=3D l; buf +=3D l; addr +=3D l; } - return 0; + ret =3D 0; +out_close: + if (fd !=3D -1) { + close(fd); + } +out: + return ret; } #endif =20 --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417083; cv=none; d=zohomail.com; s=zohoarc; b=IJgrS62BYXGLvS18kfRLBQezGhifKCleZp9g0kPf/3pJhEFh8EdFEiAYKOnByXzaf9WjGNzfQrpvC7jDUdEkRhTcx6aUgblmPPXHSUezXY90srtsEVBdv1ggw5Hi4xacYcmNzDJhFhbsu9c/oL1f8yJrhC31j45ZN7h7aATSl50= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417083; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=n3i8WIPnfJe6OJ/KMGjZPX6qT+eI0MPf6OW8gP6VkEI=; b=hk6HJq5cS8hZwI4g42ubJC2pJNSRYTTZd4bYUzwEgZHH/4qH8V2S8k8V56xNIbCCwdhGvlLQmoNBW4ihNO/vLo245CrNAha+jpPGXVZb8FDiFKCPyxdekyPRdx9eH6PDbg52LJcOsvWgRnZJYHoA0QQI8kT0YcIdj9hivbO22ZU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417083831811.7296281176122; Sat, 27 Jan 2024 20:44:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx0U-0004nP-0z; Sat, 27 Jan 2024 23:42:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0S-0004nG-SR for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:56 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0Q-0004LT-4x for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:56 -0500 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-2954b34ddd0so313455a91.0 for ; Sat, 27 Jan 2024 20:42:53 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416973; x=1707021773; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n3i8WIPnfJe6OJ/KMGjZPX6qT+eI0MPf6OW8gP6VkEI=; b=Eac12R1P1SS7QNLIlhoXAB2DrTLsmI3mNNHKhz2fC2aXwvJZsLSYgL7vYOnx+pCFC5 opH6J4/nh6VL2J+/2hayD4cbYd+cg2IpyZvF2AkBC+mqeBtA62h8/yzb5P8pFUHY7fsN DLPw26vRRL/XMRgoPAXLtf6fTkSPXZMQxtUrR8Mjq4gGO2Ipj6WYvqhjeh59T8ORogjw KkzHjPdemJZ0hb8jmRhNrT8tT9WKWTondfPXUN7hs0ALAESP1A7cKTotbrxFSgEwYFMC Be56iirMIe2OPO/hwxrtZTGh408yQ3U7X8W0c8xk06fOqB12fNRL6XmXr9Xcv+xyWITz 7Jgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416973; x=1707021773; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n3i8WIPnfJe6OJ/KMGjZPX6qT+eI0MPf6OW8gP6VkEI=; b=l+2hnQawIk6CFp2vA8mud6BSyg511B/UZJY2U6pt0exXoXfMbdNlU1aIV6ZcDhb6Te ycQSpU0fkSTqTFooZjp2zogdUwLziICSliQN4/fffNIh8TOMZnnvT/Nb2B3cXa/fDrp7 K/AcFlGg9pGnkIgkXJDW1SoeNBH1UwQ0eypfR3ixNsT7W6slK6onbbOGlwtEyMMlOAGp Lde9+zD6BHVNzUMJk9rT/6odj+uSheZle6mHhD8WVK7WzdDm/MhUg2xO/cTfQ+oWAKMr A4Rc0upBgGpm5kwhZqv0nnC+78tKXTuICE5d1EYEJvgBGb2mt7opJ++Ab6bRkIn6t9i6 B5tg== X-Gm-Message-State: AOJu0YyIwMCgV9DX7lJgm30BqnRlHg/HYUxqCPJtnKpoKDac7vPJpP6R ZOWsAIDl6uWBO/YAA4AfreVqsgyp7fagerJhyOXYm0b500yd80hUm8wwlsu6M7gYMNLZkV3/8pJ 52vBZAw== X-Google-Smtp-Source: AGHT+IE1opL2eZ7d3MUOOou62+xihPi04M9omeaSYm9yLz4uRBTQENcKUkjFviVMb1LuF/VsQnXz6A== X-Received: by 2002:a17:90b:1d8a:b0:28f:f6fa:55a7 with SMTP id pf10-20020a17090b1d8a00b0028ff6fa55a7mr1661308pjb.2.1706416972788; Sat, 27 Jan 2024 20:42:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich Subject: [PATCH 14/33] tests/tcg: Factor out gdbstub test functions Date: Sun, 28 Jan 2024 14:41:54 +1000 Message-Id: <20240128044213.316480-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417084766100009 Content-Type: text/plain; charset="utf-8" From: Ilya Leoshkevich Both the report() function as well as the initial gdbstub test sequence are copy-pasted into ~10 files with slight modifications. This indicates that they are indeed generic, so factor them out. While at it, add a few newlines to make the formatting closer to PEP-8. Signed-off-by: Ilya Leoshkevich Message-Id: <20240109230808.583012-3-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/guest-debug/run-test.py | 7 ++- tests/guest-debug/test_gdbstub.py | 56 +++++++++++++++++++ tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 34 +---------- tests/tcg/aarch64/gdbstub/test-sve.py | 33 +---------- tests/tcg/multiarch/gdbstub/interrupt.py | 47 ++-------------- tests/tcg/multiarch/gdbstub/memory.py | 39 +------------ tests/tcg/multiarch/gdbstub/registers.py | 41 ++------------ tests/tcg/multiarch/gdbstub/sha1.py | 38 ++----------- .../multiarch/gdbstub/test-proc-mappings.py | 39 +------------ .../multiarch/gdbstub/test-qxfer-auxv-read.py | 37 +----------- .../gdbstub/test-thread-breakpoint.py | 37 +----------- tests/tcg/s390x/gdbstub/test-signals-s390x.py | 42 +------------- tests/tcg/s390x/gdbstub/test-svc.py | 39 +------------ 13 files changed, 94 insertions(+), 395 deletions(-) create mode 100644 tests/guest-debug/test_gdbstub.py diff --git a/tests/guest-debug/run-test.py b/tests/guest-debug/run-test.py index b13b27d4b1..368ff8a890 100755 --- a/tests/guest-debug/run-test.py +++ b/tests/guest-debug/run-test.py @@ -97,7 +97,12 @@ def log(output, msg): sleep(1) log(output, "GDB CMD: %s" % (gdb_cmd)) =20 - result =3D subprocess.call(gdb_cmd, shell=3DTrue, stdout=3Doutput, std= err=3Dstderr) + gdb_env =3D dict(os.environ) + gdb_pythonpath =3D gdb_env.get("PYTHONPATH", "").split(os.pathsep) + gdb_pythonpath.append(os.path.dirname(os.path.realpath(__file__))) + gdb_env["PYTHONPATH"] =3D os.pathsep.join(gdb_pythonpath) + result =3D subprocess.call(gdb_cmd, shell=3DTrue, stdout=3Doutput, std= err=3Dstderr, + env=3Dgdb_env) =20 # A result of greater than 128 indicates a fatal signal (likely a # crash due to gdb internal failure). That's a problem for GDB and diff --git a/tests/guest-debug/test_gdbstub.py b/tests/guest-debug/test_gdb= stub.py new file mode 100644 index 0000000000..1bc4ed131f --- /dev/null +++ b/tests/guest-debug/test_gdbstub.py @@ -0,0 +1,56 @@ +"""Helper functions for gdbstub testing + +""" +from __future__ import print_function +import gdb +import sys + +fail_count =3D 0 + + +def report(cond, msg): + """Report success/fail of a test""" + if cond: + print("PASS: {}".format(msg)) + else: + print("FAIL: {}".format(msg)) + global fail_count + fail_count +=3D 1 + + +def main(test, expected_arch=3DNone): + """Run a test function + + This runs as the script it sourced (via -x, via run-test.py).""" + try: + inferior =3D gdb.selected_inferior() + arch =3D inferior.architecture() + print("ATTACHED: {}".format(arch)) + if expected_arch is not None: + report(arch.name() =3D=3D expected_arch, + "connected to {}".format(expected_arch)) + except (gdb.error, AttributeError): + print("SKIP: not connected") + exit(0) + + if gdb.parse_and_eval("$pc") =3D=3D 0: + print("SKIP: PC not set") + exit(0) + + try: + test() + except: + print("GDB Exception: {}".format(sys.exc_info()[0])) + global fail_count + fail_count +=3D 1 + import code + code.InteractiveConsole(locals=3Dglobals()).interact() + raise + + try: + gdb.execute("kill") + except gdb.error: + pass + + print("All tests complete: %d failures".format(fail_count)) + exit(fail_count) diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch6= 4/gdbstub/test-sve-ioctl.py index ee8d467e59..a78a3a2514 100644 --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py @@ -8,19 +8,10 @@ # =20 import gdb -import sys +from test_gdbstub import main, report =20 initial_vlen =3D 0 -failcount =3D 0 =20 -def report(cond, msg): - "Report success/fail of test" - if cond: - print ("PASS: %s" % (msg)) - else: - print ("FAIL: %s" % (msg)) - global failcount - failcount +=3D 1 =20 class TestBreakpoint(gdb.Breakpoint): def __init__(self, sym_name=3D"__sve_ld_done"): @@ -64,26 +55,5 @@ def run_test(): =20 gdb.execute("c") =20 -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior =3D gdb.selected_inferior() - arch =3D inferior.architecture() - report(arch.name() =3D=3D "aarch64", "connected to aarch64") -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=3Dsys.stderr) - exit(0) =20 -try: - # Run the actual tests - run_test() -except: - print ("GDB Exception: %s" % (sys.exc_info()[0])) - failcount +=3D 1 - import code - code.InteractiveConsole(locals=3Dglobals()).interact() - raise - -print("All tests complete: %d failures" % failcount) -exit(failcount) +main(run_test, expected_arch=3D"aarch64") diff --git a/tests/tcg/aarch64/gdbstub/test-sve.py b/tests/tcg/aarch64/gdbs= tub/test-sve.py index afd8ece98d..84cdcd4a32 100644 --- a/tests/tcg/aarch64/gdbstub/test-sve.py +++ b/tests/tcg/aarch64/gdbstub/test-sve.py @@ -6,20 +6,10 @@ # =20 import gdb -import sys +from test_gdbstub import main, report =20 MAGIC =3D 0xDEADBEEF =20 -failcount =3D 0 - -def report(cond, msg): - "Report success/fail of test" - if cond: - print ("PASS: %s" % (msg)) - else: - print ("FAIL: %s" % (msg)) - global failcount - failcount +=3D 1 =20 def run_test(): "Run through the tests one by one" @@ -54,24 +44,5 @@ def run_test(): report(str(v.type) =3D=3D "uint64_t", "size of %s" % (reg)) report(int(v) =3D=3D MAGIC, "%s is 0x%x" % (reg, MAGIC)) =20 -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior =3D gdb.selected_inferior() - arch =3D inferior.architecture() - report(arch.name() =3D=3D "aarch64", "connected to aarch64") -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=3Dsys.stderr) - exit(0) =20 -try: - # Run the actual tests - run_test() -except: - print ("GDB Exception: %s" % (sys.exc_info()[0])) - failcount +=3D 1 - -print("All tests complete: %d failures" % failcount) - -exit(failcount) +main(run_test, expected_arch=3D"aarch64") diff --git a/tests/tcg/multiarch/gdbstub/interrupt.py b/tests/tcg/multiarch= /gdbstub/interrupt.py index c016e7afbb..90a45b5140 100644 --- a/tests/tcg/multiarch/gdbstub/interrupt.py +++ b/tests/tcg/multiarch/gdbstub/interrupt.py @@ -8,19 +8,7 @@ # =20 import gdb -import sys - -failcount =3D 0 - - -def report(cond, msg): - "Report success/fail of test" - if cond: - print("PASS: %s" % (msg)) - else: - print("FAIL: %s" % (msg)) - global failcount - failcount +=3D 1 +from test_gdbstub import main, report =20 =20 def check_interrupt(thread): @@ -59,6 +47,9 @@ def run_test(): Test if interrupting the code always lands us on the same thread when running with scheduler-lock enabled. """ + if len(gdb.selected_inferior().threads()) =3D=3D 1: + print("SKIP: set to run on a single thread") + exit(0) =20 gdb.execute("set scheduler-locking on") for thread in gdb.selected_inferior().threads(): @@ -66,32 +57,4 @@ def run_test(): "thread %d resumes correctly on interrupt" % thread.num) =20 =20 -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior =3D gdb.selected_inferior() - arch =3D inferior.architecture() - print("ATTACHED: %s" % arch.name()) -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=3Dsys.stderr) - exit(0) - -if gdb.parse_and_eval('$pc') =3D=3D 0: - print("SKIP: PC not set") - exit(0) -if len(gdb.selected_inferior().threads()) =3D=3D 1: - print("SKIP: set to run on a single thread") - exit(0) - -try: - # Run the actual tests - run_test() -except (gdb.error): - print("GDB Exception: %s" % (sys.exc_info()[0])) - failcount +=3D 1 - pass - -# Finally kill the inferior and exit gdb with a count of failures -gdb.execute("kill") -exit(failcount) +main(run_test) diff --git a/tests/tcg/multiarch/gdbstub/memory.py b/tests/tcg/multiarch/gd= bstub/memory.py index fb1d06b7bb..532b92e7fb 100644 --- a/tests/tcg/multiarch/gdbstub/memory.py +++ b/tests/tcg/multiarch/gdbstub/memory.py @@ -9,18 +9,7 @@ =20 import gdb import sys - -failcount =3D 0 - - -def report(cond, msg): - "Report success/fail of test" - if cond: - print("PASS: %s" % (msg)) - else: - print("FAIL: %s" % (msg)) - global failcount - failcount +=3D 1 +from test_gdbstub import main, report =20 =20 def check_step(): @@ -99,29 +88,5 @@ def run_test(): =20 report(cbp.hit_count =3D=3D 0, "didn't reach backstop") =20 -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior =3D gdb.selected_inferior() - arch =3D inferior.architecture() - print("ATTACHED: %s" % arch.name()) -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=3Dsys.stderr) - exit(0) =20 -if gdb.parse_and_eval('$pc') =3D=3D 0: - print("SKIP: PC not set") - exit(0) - -try: - # Run the actual tests - run_test() -except (gdb.error): - print("GDB Exception: %s" % (sys.exc_info()[0])) - failcount +=3D 1 - pass - -# Finally kill the inferior and exit gdb with a count of failures -gdb.execute("kill") -exit(failcount) +main(run_test) diff --git a/tests/tcg/multiarch/gdbstub/registers.py b/tests/tcg/multiarch= /gdbstub/registers.py index 688c061107..b3d13cb077 100644 --- a/tests/tcg/multiarch/gdbstub/registers.py +++ b/tests/tcg/multiarch/gdbstub/registers.py @@ -7,20 +7,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later =20 import gdb -import sys import xml.etree.ElementTree as ET +from test_gdbstub import main, report + =20 initial_vlen =3D 0 -failcount =3D 0 - -def report(cond, msg): - "Report success/fail of test." - if cond: - print("PASS: %s" % (msg)) - else: - print("FAIL: %s" % (msg)) - global failcount - failcount +=3D 1 =20 =20 def fetch_xml_regmap(): @@ -75,6 +66,7 @@ def fetch_xml_regmap(): =20 return reg_map =20 + def get_register_by_regnum(reg_map, regnum): """ Helper to find a register from the map via its XML regnum @@ -84,6 +76,7 @@ def get_register_by_regnum(reg_map, regnum): return entry return None =20 + def crosscheck_remote_xml(reg_map): """ Cross-check the list of remote-registers with the XML info. @@ -144,6 +137,7 @@ def crosscheck_remote_xml(reg_map): elif "seen" not in x_reg: print(f"{x_reg} wasn't seen in remote-registers") =20 + def initial_register_read(reg_map): """ Do an initial read of all registers that we know gdb cares about @@ -214,27 +208,4 @@ def run_test(): complete_and_diff(reg_map) =20 =20 -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior =3D gdb.selected_inferior() - arch =3D inferior.architecture() - print("ATTACHED: %s" % arch.name()) -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=3Dsys.stderr) - exit(0) - -if gdb.parse_and_eval('$pc') =3D=3D 0: - print("SKIP: PC not set") - exit(0) - -try: - run_test() -except (gdb.error): - print ("GDB Exception: %s" % (sys.exc_info()[0])) - failcount +=3D 1 - pass - -print("All tests complete: %d failures" % failcount) -exit(failcount) +main(run_test) diff --git a/tests/tcg/multiarch/gdbstub/sha1.py b/tests/tcg/multiarch/gdbs= tub/sha1.py index 416728415f..1ce711a402 100644 --- a/tests/tcg/multiarch/gdbstub/sha1.py +++ b/tests/tcg/multiarch/gdbstub/sha1.py @@ -7,19 +7,11 @@ # =20 import gdb -import sys +from test_gdbstub import main, report + =20 initial_vlen =3D 0 -failcount =3D 0 =20 -def report(cond, msg): - "Report success/fail of test" - if cond: - print("PASS: %s" % (msg)) - else: - print("FAIL: %s" % (msg)) - global failcount - failcount +=3D 1 =20 def check_break(sym_name): "Setup breakpoint, continue and check we stopped." @@ -35,6 +27,7 @@ def check_break(sym_name): =20 bp.delete() =20 + def run_test(): "Run through the tests one by one" =20 @@ -57,28 +50,5 @@ def run_test(): # finally check we don't barf inspecting registers gdb.execute("info registers") =20 -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior =3D gdb.selected_inferior() - arch =3D inferior.architecture() - print("ATTACHED: %s" % arch.name()) -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=3Dsys.stderr) - exit(0) =20 -if gdb.parse_and_eval('$pc') =3D=3D 0: - print("SKIP: PC not set") - exit(0) - -try: - # Run the actual tests - run_test() -except (gdb.error): - print ("GDB Exception: %s" % (sys.exc_info()[0])) - failcount +=3D 1 - pass - -print("All tests complete: %d failures" % failcount) -exit(failcount) +main(run_test) diff --git a/tests/tcg/multiarch/gdbstub/test-proc-mappings.py b/tests/tcg/= multiarch/gdbstub/test-proc-mappings.py index 04ec61d219..564613fabf 100644 --- a/tests/tcg/multiarch/gdbstub/test-proc-mappings.py +++ b/tests/tcg/multiarch/gdbstub/test-proc-mappings.py @@ -3,20 +3,7 @@ This runs as a sourced script (via -x, via run-test.py).""" from __future__ import print_function import gdb -import sys - - -n_failures =3D 0 - - -def report(cond, msg): - """Report success/fail of a test""" - if cond: - print("PASS: {}".format(msg)) - else: - print("FAIL: {}".format(msg)) - global n_failures - n_failures +=3D 1 +from test_gdbstub import main, report =20 =20 def run_test(): @@ -37,26 +24,4 @@ def run_test(): # report("/sha1" in mappings, "Found the test binary name in the mappi= ngs") =20 =20 -def main(): - """Prepare the environment and run through the tests""" - try: - inferior =3D gdb.selected_inferior() - print("ATTACHED: {}".format(inferior.architecture().name())) - except (gdb.error, AttributeError): - print("SKIPPING (not connected)") - exit(0) - - if gdb.parse_and_eval('$pc') =3D=3D 0: - print("SKIP: PC not set") - exit(0) - - try: - # Run the actual tests - run_test() - except gdb.error: - report(False, "GDB Exception: {}".format(sys.exc_info()[0])) - print("All tests complete: %d failures" % n_failures) - exit(n_failures) - - -main() +main(run_test) diff --git a/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py b/tests/tc= g/multiarch/gdbstub/test-qxfer-auxv-read.py index 926fa962b7..00c26ab4a9 100644 --- a/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py +++ b/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py @@ -6,18 +6,8 @@ # =20 import gdb -import sys +from test_gdbstub import main, report =20 -failcount =3D 0 - -def report(cond, msg): - "Report success/fail of test" - if cond: - print ("PASS: %s" % (msg)) - else: - print ("FAIL: %s" % (msg)) - global failcount - failcount +=3D 1 =20 def run_test(): "Run through the tests one by one" @@ -26,28 +16,5 @@ def run_test(): report(isinstance(auxv, str), "Fetched auxv from inferior") report(auxv.find("sha1"), "Found test binary name in auxv") =20 -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior =3D gdb.selected_inferior() - arch =3D inferior.architecture() - print("ATTACHED: %s" % arch.name()) -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=3Dsys.stderr) - exit(0) =20 -if gdb.parse_and_eval('$pc') =3D=3D 0: - print("SKIP: PC not set") - exit(0) - -try: - # Run the actual tests - run_test() -except (gdb.error): - print ("GDB Exception: %s" % (sys.exc_info()[0])) - failcount +=3D 1 - pass - -print("All tests complete: %d failures" % failcount) -exit(failcount) +main(run_test) diff --git a/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py b/tests/= tcg/multiarch/gdbstub/test-thread-breakpoint.py index e57d2a8db8..4d6b6b9fbe 100644 --- a/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py +++ b/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py @@ -6,18 +6,8 @@ # =20 import gdb -import sys +from test_gdbstub import main, report =20 -failcount =3D 0 - -def report(cond, msg): - "Report success/fail of test" - if cond: - print ("PASS: %s" % (msg)) - else: - print ("FAIL: %s" % (msg)) - global failcount - failcount +=3D 1 =20 def run_test(): "Run through the tests one by one" @@ -29,28 +19,5 @@ def run_test(): frame =3D gdb.selected_frame() report(str(frame.function()) =3D=3D "thread1_func", "break @ %s"%frame) =20 -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior =3D gdb.selected_inferior() - arch =3D inferior.architecture() - print("ATTACHED: %s" % arch.name()) -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=3Dsys.stderr) - exit(0) =20 -if gdb.parse_and_eval('$pc') =3D=3D 0: - print("SKIP: PC not set") - exit(0) - -try: - # Run the actual tests - run_test() -except (gdb.error): - print ("GDB Exception: %s" % (sys.exc_info()[0])) - failcount +=3D 1 - pass - -print("All tests complete: %d failures" % failcount) -exit(failcount) +main(run_test) diff --git a/tests/tcg/s390x/gdbstub/test-signals-s390x.py b/tests/tcg/s390= x/gdbstub/test-signals-s390x.py index ca2bbc0b03..b6b7b39fc4 100644 --- a/tests/tcg/s390x/gdbstub/test-signals-s390x.py +++ b/tests/tcg/s390x/gdbstub/test-signals-s390x.py @@ -7,19 +7,7 @@ # =20 import gdb -import sys - -failcount =3D 0 - - -def report(cond, msg): - """Report success/fail of test""" - if cond: - print("PASS: %s" % (msg)) - else: - print("FAIL: %s" % (msg)) - global failcount - failcount +=3D 1 +from test_gdbstub import main, report =20 =20 def run_test(): @@ -42,31 +30,7 @@ def run_test(): gdb.Breakpoint("_exit") gdb.execute("c") status =3D int(gdb.parse_and_eval("$r2")) - report(status =3D=3D 0, "status =3D=3D 0"); + report(status =3D=3D 0, "status =3D=3D 0") =20 =20 -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior =3D gdb.selected_inferior() - arch =3D inferior.architecture() - print("ATTACHED: %s" % arch.name()) -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=3Dsys.stderr) - exit(0) - -if gdb.parse_and_eval("$pc") =3D=3D 0: - print("SKIP: PC not set") - exit(0) - -try: - # Run the actual tests - run_test() -except (gdb.error): - print("GDB Exception: %s" % (sys.exc_info()[0])) - failcount +=3D 1 - pass - -print("All tests complete: %d failures" % failcount) -exit(failcount) +main(run_test) diff --git a/tests/tcg/s390x/gdbstub/test-svc.py b/tests/tcg/s390x/gdbstub/= test-svc.py index 804705fede..17210b4e02 100644 --- a/tests/tcg/s390x/gdbstub/test-svc.py +++ b/tests/tcg/s390x/gdbstub/test-svc.py @@ -3,20 +3,7 @@ This runs as a sourced script (via -x, via run-test.py).""" from __future__ import print_function import gdb -import sys - - -n_failures =3D 0 - - -def report(cond, msg): - """Report success/fail of a test""" - if cond: - print("PASS: {}".format(msg)) - else: - print("FAIL: {}".format(msg)) - global n_failures - n_failures +=3D 1 +from test_gdbstub import main, report =20 =20 def run_test(): @@ -35,26 +22,4 @@ def run_test(): gdb.execute("si") =20 =20 -def main(): - """Prepare the environment and run through the tests""" - try: - inferior =3D gdb.selected_inferior() - print("ATTACHED: {}".format(inferior.architecture().name())) - except (gdb.error, AttributeError): - print("SKIPPING (not connected)") - exit(0) - - if gdb.parse_and_eval('$pc') =3D=3D 0: - print("SKIP: PC not set") - exit(0) - - try: - # Run the actual tests - run_test() - except gdb.error: - report(False, "GDB Exception: {}".format(sys.exc_info()[0])) - print("All tests complete: %d failures" % n_failures) - exit(n_failures) - - -main() +main(run_test) --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417194; cv=none; d=zohomail.com; s=zohoarc; b=lN9n9QR4gsmY6smYhMfa6KNUldUScAS7LeM3OnqOtBh7MLxEYVXQxPk4o8R0SQW7c+NE5nzYxl5IWpT4OimD46xYr/v4xZNF3NmrSJ56sSN6GkPf//qE0QS+g3j8glx4sJNpaB27kNZTlF6Q+aYXPR4A1AbivKeR2G6bsdYb5Yo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417194; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=s84QwsvJ4FUEfSYgoD2xLjKpOUhTXQHsXWR0Okjxs+g=; b=kIubbUl0uVDJq2yjTjglLnuRG36780SPiOBFentphpttY9dQRvQzo+fGwTADCZsp4QfVydeLqEpIsGnnqP7TmL7d5d7zLiVCYQ1NM467iC+hcc3kxuhnveG7C+CqIm0zNt/+fMS6A96JTlv0F5XJfrtHYyph2v0nt/Us6o/+dD0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417194637781.3709781792392; Sat, 27 Jan 2024 20:46:34 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx0V-0004o9-U4; Sat, 27 Jan 2024 23:42:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0U-0004nQ-31 for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:58 -0500 Received: from mail-ot1-x333.google.com ([2607:f8b0:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0S-0004La-FY for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:42:57 -0500 Received: by mail-ot1-x333.google.com with SMTP id 46e09a7af769-6e11cda9f6fso320121a34.2 for ; Sat, 27 Jan 2024 20:42:56 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416975; x=1707021775; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s84QwsvJ4FUEfSYgoD2xLjKpOUhTXQHsXWR0Okjxs+g=; b=esJ/DG5QHYlz2RF+C3L4+gDhtW4weBNIESMy+VH73gs4fqs3DIiqGV8v1a0MnXenqM r01sw0vlhje4nemCojnzakN3R/wtOVIsM5CQVAVRWIP5vHS/vrkHKQjjkARmx19rTtzH vSElKnvVTzJcUAg/vtps7NDm3K92HDF7ps3S1h8VDYxTNfr3wYbRRUgDLdMuTRJSSAvk s1lHa1EMS5dkZsGDJAUlpSEaHXkVe+XLp1rh2rn4k1GON1AbcJ4fN9YH+qCGixCXfWBL LeA7op+40LLJ0cKfp4EeQFzQXxnNGKS2LM6LfAwMsSOod6hJwr/yR6kTIBPc04wutNOO 2ZFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416975; x=1707021775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s84QwsvJ4FUEfSYgoD2xLjKpOUhTXQHsXWR0Okjxs+g=; b=oUhPt28u/rNlgUHrnmec/MhZZuHYnbr7+QYOuusVrVN0BOxLwTxCxOQbKGZE+6j07L 3uLdI0FSJw97t2vRW4/O29jyilmG9ccsQmP0+Oc/1cxUtaEJrgD+3Kzvmiexh/pjMGBV RuBrWHWCJS618n5gMF1L9bM5iFC5FeiluSs6hHffzlbjpaIuQeB3d3KRyf+nqvB2TICd tyyo+YL9ahkq/WHq1TyxGEQghsbol7bpvrgRM0l3F1cZJkOnVJis2XkdVS4MaMFfRGS6 Bel2sYAJhcTVEUPDRDMjO2L9t2756IHSKdHborIXJ718x/VIC77hXTrdBQ5bs1DR7+8Q cUUg== X-Gm-Message-State: AOJu0YzhjSxeY93QGH+zvwO+0Z1zB3HxqkAdHIV0WuROVeTKAHqBg8AC PeqCeGXiSqUCbznDEA55NqXyBuV4sFdRiDWRaFRD8JqqW1/NT9wIyLxzfUyIzBIKvDCzFSxBk0T MCfSuBA== X-Google-Smtp-Source: AGHT+IFjOJsDxai7Yqjd+IMqWSxpXCgee7cKN31LdGejTnFIbhjTt+jtXs/xsTE4PIV0sYEgB8/RWw== X-Received: by 2002:a05:6358:2826:b0:175:7a57:81ed with SMTP id k38-20020a056358282600b001757a5781edmr3127610rwb.23.1706416975133; Sat, 27 Jan 2024 20:42:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich Subject: [PATCH 15/33] tests/tcg: Add the PROT_NONE gdbstub test Date: Sun, 28 Jan 2024 14:41:55 +1000 Message-Id: <20240128044213.316480-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417195057100001 Content-Type: text/plain; charset="utf-8" From: Ilya Leoshkevich Make sure that qemu gdbstub, like gdbserver, allows reading from and writing to PROT_NONE pages. Signed-off-by: Ilya Leoshkevich Message-Id: <20240109230808.583012-4-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/multiarch/prot-none.c | 40 ++++++++++++++++++++++++ tests/tcg/multiarch/Makefile.target | 9 +++++- tests/tcg/multiarch/gdbstub/prot-none.py | 22 +++++++++++++ 3 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/multiarch/prot-none.c create mode 100644 tests/tcg/multiarch/gdbstub/prot-none.py diff --git a/tests/tcg/multiarch/prot-none.c b/tests/tcg/multiarch/prot-non= e.c new file mode 100644 index 0000000000..dc56aadb3c --- /dev/null +++ b/tests/tcg/multiarch/prot-none.c @@ -0,0 +1,40 @@ +/* + * Test that GDB can access PROT_NONE pages. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include +#include +#include +#include +#include + +void break_here(void *q) +{ +} + +int main(void) +{ + long pagesize =3D sysconf(_SC_PAGESIZE); + void *p, *q; + int err; + + p =3D mmap(NULL, pagesize * 2, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + assert(p !=3D MAP_FAILED); + q =3D p + pagesize - 1; + strcpy(q, "42"); + + err =3D mprotect(p, pagesize * 2, PROT_NONE); + assert(err =3D=3D 0); + + break_here(q); + + err =3D mprotect(p, pagesize * 2, PROT_READ); + assert(err =3D=3D 0); + if (getenv("PROT_NONE_PY")) { + assert(strcmp(q, "24") =3D=3D 0); + } + + return EXIT_SUCCESS; +} diff --git a/tests/tcg/multiarch/Makefile.target b/tests/tcg/multiarch/Make= file.target index d31ba8d6ae..315a2e1358 100644 --- a/tests/tcg/multiarch/Makefile.target +++ b/tests/tcg/multiarch/Makefile.target @@ -101,13 +101,20 @@ run-gdbstub-registers: sha512 --bin $< --test $(MULTIARCH_SRC)/gdbstub/registers.py, \ checking register enumeration) =20 +run-gdbstub-prot-none: prot-none + $(call run-test, $@, env PROT_NONE_PY=3D1 $(GDB_SCRIPT) \ + --gdb $(GDB) \ + --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \ + --bin $< --test $(MULTIARCH_SRC)/gdbstub/prot-none.py, \ + accessing PROT_NONE memory) + else run-gdbstub-%: $(call skip-test, "gdbstub test $*", "need working gdb with $(patsubst -%= ,,$(TARGET_NAME)) support") endif EXTRA_RUNS +=3D run-gdbstub-sha1 run-gdbstub-qxfer-auxv-read \ run-gdbstub-proc-mappings run-gdbstub-thread-breakpoint \ - run-gdbstub-registers + run-gdbstub-registers run-gdbstub-prot-none =20 # ARM Compatible Semi Hosting Tests # diff --git a/tests/tcg/multiarch/gdbstub/prot-none.py b/tests/tcg/multiarch= /gdbstub/prot-none.py new file mode 100644 index 0000000000..f1f1dd82cb --- /dev/null +++ b/tests/tcg/multiarch/gdbstub/prot-none.py @@ -0,0 +1,22 @@ +"""Test that GDB can access PROT_NONE pages. + +This runs as a sourced script (via -x, via run-test.py). + +SPDX-License-Identifier: GPL-2.0-or-later +""" +from test_gdbstub import main, report + + +def run_test(): + """Run through the tests one by one""" + gdb.Breakpoint("break_here") + gdb.execute("continue") + val =3D gdb.parse_and_eval("*(char[2] *)q").string() + report(val =3D=3D "42", "{} =3D=3D 42".format(val)) + gdb.execute("set *(char[3] *)q =3D \"24\"") + gdb.execute("continue") + exitcode =3D int(gdb.parse_and_eval("$_exitcode")) + report(exitcode =3D=3D 0, "{} =3D=3D 0".format(exitcode)) + + +main(run_test) --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416977; x=1707021777; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p58dq3BNm1M9yORIAE2cQcXeCTaVjSrZcGgMOspnf2M=; b=FFQcIL8r9e1BzlduKnXMpK2Odl/2g3YabMHMfV/DpnnSRAW1ZYRpzhfq7Mw5AveHwH v4O8952/hjrwNgSFlvkzuiLP+Gsrm4Z2fAtJ9+BGvwyCkNWZPx6reep+kOd2DIME/865 SZzfXszBPrz54YeYGlitwcZyOOCb+KCLyJr/EYp33THU0PpA3rrbFc8IPKtqUlK1mB64 2DSEVhzDH/ERcogPQZcu2RVVhlwptj7l934hE9g1L8Rke6vXXF7RXivE3pVGJtMrq8gm vY/D2/5ImmvPrKRVy8qnH44PIh31c9vy+83/d3Gni9MlSmPpPot+IVcL0DYT4kU5kXKv l0kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416977; x=1707021777; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p58dq3BNm1M9yORIAE2cQcXeCTaVjSrZcGgMOspnf2M=; b=MWPLEWzIS05OMcunCN4hSdZp94iJCJDJn8OF0wlFnbyWLcuWEHI1B9GqF1MBzKm9pD +diRTJzhcuHgTrF3H9+5K20dEgSynFzBuwr2QQZEE+PMXJMgiRyOQ+NbtfrEXHBeLt1/ aIA9tbkA2bVNhT56z1ViY/2h7STLszbatX+Z2LYF39w2A0JrMXHhJYw4eTVJ1y5rQqWW AHHJpKj4zgaFRhqbVEbDcjn7vaQy4oxWAMjzahAFDosn/+YTfqDw73R+PhBEMYvBagaf ca4HzSM6KWJH/4MCL0WHpW5vkyKXczY4NFDBNDYIP9LhEZkysZ6eTC/9922j0vkFRFlZ jdVQ== X-Gm-Message-State: AOJu0Yxnl+PnIUMKOh4ZhBMehxpXqtEdMWll1Uwz+npWkh7IbaWa9mj1 sy5q6jWrVOzuvMJxUDHc6/K+meSItARBBVG7p5Bp1WW2HVmSRG5XDP2MPjDzaFYD0UGTtRG3rlK 3qS7hew== X-Google-Smtp-Source: AGHT+IGf3VxO1VhOTznnn69pllVLFyMmg4ojYaF58hz4yLlUxbJX7zc1k3sy4UU7CYZW2yWFLmow4Q== X-Received: by 2002:a17:90a:4bc6:b0:290:11a4:ec4b with SMTP id u6-20020a17090a4bc600b0029011a4ec4bmr1603372pjl.61.1706416977455; Sat, 27 Jan 2024 20:42:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 16/33] accel/tcg/cpu-exec: Use RCU_READ_LOCK_GUARD Date: Sun, 28 Jan 2024 14:41:56 +1000 Message-Id: <20240128044213.316480-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417148890100005 From: Philippe Mathieu-Daud=C3=A9 Replace the manual rcu_read_(un)lock calls in cpu_exec(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20240124074201.8239-2-philmd@linaro.org> [rth: Use RCU_READ_LOCK_GUARD not WITH_RCU_READ_LOCK_GUARD] Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/cpu-exec.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 40c268bfa1..950dad63cb 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1050,7 +1050,7 @@ int cpu_exec(CPUState *cpu) return EXCP_HALTED; } =20 - rcu_read_lock(); + RCU_READ_LOCK_GUARD(); cpu_exec_enter(cpu); =20 /* @@ -1064,8 +1064,6 @@ int cpu_exec(CPUState *cpu) ret =3D cpu_exec_setjmp(cpu, &sc); =20 cpu_exec_exit(cpu); - rcu_read_unlock(); - return ret; } =20 --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417249; cv=none; d=zohomail.com; s=zohoarc; b=VuCIU0xAMT7A3HEQtdlIaROOZ/KueaoBWfHDm+bCtTCSpIk6V3XbQECboe/TDCVUvzfVoni9ZipUSgDfdQV03jSocqmXbc9RiMO2ZwmMu54XpZdmXJrlQF2YkZPFhvzv45dmMxbp5WTnJaUQk4pgNwcReMWyprqopDyVWVUhy80= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417249; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5Gt1CNQckx8yO7WR3bedyoAfBxjm8E850nOtIhoFZIA=; b=GSralLdS/n9ALbMA94OPbCBtn4ARRLgkSRB98OYUpPkxGdfi6ECXc1BOVz0jFRKULJAxQ1rkF4GMOZieytO2rrksC1W18WMT+elnHxFLUyEyqr4vY8x5sC/uEit5wcbimRcCPmIJ7dTQ42R7WaV0vlNOO4UA0FFJIQzQgmyKjdw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417249427631.1681082277311; Sat, 27 Jan 2024 20:47:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx0a-0004on-31; Sat, 27 Jan 2024 23:43:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0Y-0004oZ-Vg for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:02 -0500 Received: from mail-oo1-xc2f.google.com ([2607:f8b0:4864:20::c2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0X-0004MI-BG for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:02 -0500 Received: by mail-oo1-xc2f.google.com with SMTP id 006d021491bc7-59502aa878aso892602eaf.1 for ; Sat, 27 Jan 2024 20:43:00 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416980; x=1707021780; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5Gt1CNQckx8yO7WR3bedyoAfBxjm8E850nOtIhoFZIA=; b=WJdnCzucKZBV4towWVl24R5F++q0UC7aooRKRVdEr1NrI1SIwOPwOwnsSTa/8bsqgw idc5cJdzLWbUjiLmxd9QG4KIMNpVtFFFSXu+Wvvz1KnxbjZq/yGSNIudUGr9MwVFl3C4 v9x7huVVhm1wo/Pvo/3IQ4AVydOgxH8boYalJXeXAWg9vF5oRBolMslBNW/1YxEhgWto 2RSdg2Fhysh7ixasKRJ4yyhqE0EyKIXKrm+qtprToll1urUAIyhVlMQ6ypVxshbity8u 82mNg0ze2JUAJ4dcPkqGLeK23L2ZrcpJMB1CJBLepEYUghlZ9Mz7qTZZ5RdeoMRavWIw n48g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416980; x=1707021780; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5Gt1CNQckx8yO7WR3bedyoAfBxjm8E850nOtIhoFZIA=; b=nkWsa+9IKszQZLk6mo4uYAcVAaS7g0rQMs8d2mJvcb7BHVD99fpoWzsidAEJE30PCw I3NlwkxqqtBBAGPTrPPB6luDUry/x4haGMp0TYsgcJp95lnZeeNH5ROXxUVaI6TBeu/t 7NzHyTlUEoyQYphiDNUomtGXoXDDfDFpmDns/v8iLz+rn7falL+R5jTNr3Giqv/6n97U 4bbNDTKmxNEHZ4JepQQnaXXPRzmZQnU2QvDwktzjc9TZHWcc6tB/qT4aoZRXHluHy8X6 J6ckEXBjUNP93XSMDQmHUjSUqDpdIw014N0gumdyI1NsrBBEhIc0v5UG6mu+zB4+e+Nm l8kQ== X-Gm-Message-State: AOJu0YxEP28HXgZt9AZIWeNnujV1PrCTMYjYxOPGDoMarNPVyhcDmDph 68nDD+n5t1Ne6gfUDbyS8VdOO8g915XB8OYlEghnFWDTy/okxmhYE13c3+gmEVe2s8p2sRxiStD tig5Dvw== X-Google-Smtp-Source: AGHT+IHKOjdAhCfbPIdMghraXMGmP3LDCEbjqUjU9s7DX1xYeJcB3q1unkvroBBod6ZpguoBSarosA== X-Received: by 2002:a05:6358:cc1b:b0:176:b6fe:db88 with SMTP id gx27-20020a056358cc1b00b00176b6fedb88mr2148763rwb.64.1706416979988; Sat, 27 Jan 2024 20:42:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 17/33] target: Make qemu_target_page_mask() available for *-user Date: Sun, 28 Jan 2024 14:41:57 +1000 Message-Id: <20240128044213.316480-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417251092100003 From: Ilya Leoshkevich Currently qemu_target_page_mask() is usable only from the softmmu code. Make it possible to use it from the *-user code as well. Signed-off-by: Ilya Leoshkevich Message-ID: <20231208003754.3688038-2-iii@linux.ibm.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20240124075609.14756-2-philmd@linaro.org> Reviewed-by: Richard Henderson [rth: Split out change to accel/tcg/perf.c] Signed-off-by: Richard Henderson --- system/physmem.c | 5 ----- target/target-common.c | 10 ++++++++++ target/meson.build | 2 ++ 3 files changed, 12 insertions(+), 5 deletions(-) create mode 100644 target/target-common.c diff --git a/system/physmem.c b/system/physmem.c index cc68a79763..5e66d9ae36 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -3431,11 +3431,6 @@ size_t qemu_target_page_size(void) return TARGET_PAGE_SIZE; } =20 -int qemu_target_page_mask(void) -{ - return TARGET_PAGE_MASK; -} - int qemu_target_page_bits(void) { return TARGET_PAGE_BITS; diff --git a/target/target-common.c b/target/target-common.c new file mode 100644 index 0000000000..903b10cfe4 --- /dev/null +++ b/target/target-common.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include "qemu/osdep.h" + +#include "cpu.h" +#include "exec/target_page.h" + +int qemu_target_page_mask(void) +{ + return TARGET_PAGE_MASK; +} diff --git a/target/meson.build b/target/meson.build index a53a60486f..dee2ac47e0 100644 --- a/target/meson.build +++ b/target/meson.build @@ -19,3 +19,5 @@ subdir('sh4') subdir('sparc') subdir('tricore') subdir('xtensa') + +specific_ss.add(files('target-common.c')) --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417138; cv=none; d=zohomail.com; s=zohoarc; b=Dfi8z+eHl3bgUkdwxv8YhVg0fBUn9vlYnLjzC+zMQxSnggDWx/g0fKMvnRCowhWvzDw8Foc1PcZSa+H/0k6Uj8AeDkd6etONqQj4OJ37O/8fk1zGVIWbgkYkkLD+tJvstkOC7Z8GJ+THxKZhenkIrqYR3EWVBB5exqBbWfC+wCY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417138; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qYcGKO9y7L+9nQKGBMKS98rrLGXyxY/fBFTDvtgcJC4=; b=XC24aQD4EbLkHKvAXmfp9VF67zQJPnesOP0ahHY5z0t+QpMuAEwFuj0ix/HdYWfYOEay4/BFev+LI+WMnEDRi86HYckhHtsGXCM2U01yvyZcL/z6ZxxPpJKBhDmG6PVXaC/5cQUrEdF/c4if8xFkbbWAA1MW7TQp4ZbkYmC6nq8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417138420957.425562182363; Sat, 27 Jan 2024 20:45:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx0d-0004pF-Kv; Sat, 27 Jan 2024 23:43:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0b-0004p4-LT for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:05 -0500 Received: from mail-oo1-xc2b.google.com ([2607:f8b0:4864:20::c2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0a-0004MY-7L for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:05 -0500 Received: by mail-oo1-xc2b.google.com with SMTP id 006d021491bc7-5957ede4deaso1180363eaf.1 for ; Sat, 27 Jan 2024 20:43:03 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416983; x=1707021783; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qYcGKO9y7L+9nQKGBMKS98rrLGXyxY/fBFTDvtgcJC4=; b=cQu9qzDOk8qh/9nVgpD1JtJCoLFPpNEsrMgzXLSYxeX5TOPiDTRrOfK0vRo4bL41EL wqwpXgE/XdW6WM3TFOKJ2PM59zfdk3Uad71u5iCEXoONm2GvS2uOAgLF2sRoPPwi9rOT dSgayf0qJL1ynOQ52AF5FXXN8CZLwBW4wXN4CV7K4RyJZ4otJiKo3Yo259TVeriODl77 TWvBymbgjOPCEJ+V0Xp2pi/1fssAWIp2UszDsWFPug+FHEzEJpof761XDMWyTJqMKx7k I7bzSaHjBxvMSNlksch5Vjt8BidWCbJKbo2nwjiUde5dRkULlwLbAqbf6DJ+eVktCuDg NtUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416983; x=1707021783; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qYcGKO9y7L+9nQKGBMKS98rrLGXyxY/fBFTDvtgcJC4=; b=TczMa5ljoD5o56+yn9xco0GLCjtMNU9lUtyxET0doQzW8FMtZSg/ZDDFpKomZ2L9z4 mat2/tvqjDl+m9e51tCewRyKo6KA2hz3+Cu5lCCNb0WFTuqizqRGGts8oAA/9CLQ3qPN 9mt3p7TruEILFa4fUz5CBnMDFOhXOVOdFfYIMNx+7dIDe37bI+Phebp872mIjBoCD2ga BVo7fy1/pKmKoIAGwMF/RKYtKLg1BDxbrsKlvkvbbp3hXII2mHzCyPKjHbfF/c8L+0XT DkQSilivcrfDrsVGd31NdL7YgkL+/6FglfxkgrsRDNEQW2lGAM9U17/xkivwFW8W8veU Qpvw== X-Gm-Message-State: AOJu0YxtXOXhD238YOketFbsPyQSBg/isl+JlfoMHxPFpmrVQO5ZTC90 ruuuWM7kBh0VIUeX6CAV9WUqXuiJ6OxhjpsLFiVc5qIqEzes9PAvJZ0MPIhoyXT0RBUET6c1Zky cXUq7iA== X-Google-Smtp-Source: AGHT+IHFNaj2yS6YbaRTmr3lHAiin40bBj0nluT6OXuPekcIN7tDCtyDDnYEiBUEBjEjo/a7OrDlhA== X-Received: by 2002:a05:6359:2b0:b0:176:b25e:a36e with SMTP id ek48-20020a05635902b000b00176b25ea36emr2528020rwb.52.1706416983010; Sat, 27 Jan 2024 20:43:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 18/33] accel/tcg: Make use of qemu_target_page_mask() in perf.c Date: Sun, 28 Jan 2024 14:41:58 +1000 Message-Id: <20240128044213.316480-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2b; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417138884100005 From: Ilya Leoshkevich Stop using TARGET_PAGE_MASK in order to make perf.c more target-agnostic. Signed-off-by: Ilya Leoshkevich Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20231212003837.64090-2-iii@linux.ibm.com> Reviewed-by: Richard Henderson Message-Id: <20240125054631.78867-2-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/perf.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/accel/tcg/perf.c b/accel/tcg/perf.c index cd1aa99a7e..ba75c1bbe4 100644 --- a/accel/tcg/perf.c +++ b/accel/tcg/perf.c @@ -10,6 +10,7 @@ =20 #include "qemu/osdep.h" #include "elf.h" +#include "exec/target_page.h" #include "exec/exec-all.h" #include "qemu/timer.h" #include "tcg/tcg.h" @@ -335,7 +336,7 @@ void perf_report_code(uint64_t guest_pc, TranslationBlo= ck *tb, /* FIXME: This replicates the restore_state_to_opc() logic. */ q[insn].address =3D gen_insn_data[insn * start_words + 0]; if (tb_cflags(tb) & CF_PCREL) { - q[insn].address |=3D (guest_pc & TARGET_PAGE_MASK); + q[insn].address |=3D (guest_pc & qemu_target_page_mask()); } else { #if defined(TARGET_I386) q[insn].address -=3D tb->cs_base; --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417081; cv=none; d=zohomail.com; s=zohoarc; b=Kr9v+n75bqnUl72JxRq9Tzdxwn5bfWeKGHOYZ+Fw00CIMhoz9E5fpN+eVvPehwBQ1aNOJQ8xrM4VmMxMgKBF6icmfNfADCewmHVrr6UGpVfOkNJ5/xlqMXezhhM3LnCH03eirn3uLnn9onGvOS39XwJlFLHfmuisuLTVvq67hm4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417081; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4bfmq9Mg4HxfU53OW0oPle9hQIH8zXg09YsWAHRVD1c=; b=WbR+3kQkujYLFMzSfM/YjstLhZ0snboL4c4D7+ycpnYSlVGsfUGUreBSVKq/2HmRwU6AV6c+/57OhgonDqz1tUgL1Uuv/+JbQ6lodJ+MES4FXm/ksY0wvYvGY8USYesVS2twBV+yd5IERJ/Ys8jW7L9hWdiGxtwfLKsls5sSDN4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417081862139.17946398783636; Sat, 27 Jan 2024 20:44:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx0h-0004q3-7x; Sat, 27 Jan 2024 23:43:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0f-0004pa-62 for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:09 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0d-0004Mj-I7 for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:08 -0500 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-2954b34ddd0so313513a91.0 for ; Sat, 27 Jan 2024 20:43:07 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416986; x=1707021786; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4bfmq9Mg4HxfU53OW0oPle9hQIH8zXg09YsWAHRVD1c=; b=oMOjDl1Ybii2UF44Dm/KozkbX7FzH7gGHCmdhoMEX+qVtm0heOxFuhKKJaI7+9WfnC lS72teZ0eoHA3J9gQF5/eI7stMwXmmO8fa5cUAuYgIqM7YSyXA3oGqM6qcL4FUvanL61 NIgA9b95GszQW2He8pGtxkrYrY6kIHlri8W7+SmSBqzi+p8ys0zK6qa/eLXLKH5Ku7bi xI8BI2H0FjYjOqijbi0NppGfkNmFGnlw7+JWt8sI5u5IBp9KwW+Eq7HohP04+lZCLiZ5 e+ISyNyY+UGV+55fBu5JozAg2ka8GEsromGvzYPSlQ+5PdQVQL05reUub5BdoMuLTXvo dfDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416986; x=1707021786; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4bfmq9Mg4HxfU53OW0oPle9hQIH8zXg09YsWAHRVD1c=; b=ohVB4dBx5oaGGSXeehQRr2UJG+jQOlQR4pYw9ax2V/rZiKprMZiFqztv6njvhwfaZr S1wKbLKX/jU8XmRjKmlSBhNy9hWeP/Ty3qHOsHUQfha0ijSGN6BCTWPG/tedXB2C1zV0 38OQog4xxn90Ln+zSl9PpbYao9SW/GytZaj2gNpNXVhafqloDZ3/GwrmkgLo2dBGnFGT o5QUb1gDxaxsAhZTJT8u0/miuoj9NKXS7CHUY2FrE9v4DYPeXQ9wqhdF3RMB3wbheq/G gopRWq6BbKa56gIppjpxN6FUV/ewXk4E6bmbea7EXw4m8wrkYl1HEGbXNVhp/yN4t2S9 rpxA== X-Gm-Message-State: AOJu0Yxx2jQBmp1PNxhDsYruxKUT0CaiYkTxEoGiqBjA/GowAz26k96n IuyLg50mJTcs/Elviin261UNckMqS2/cC30Qjqdhn1zBIJHOipi97AnPpldZ+89runCSslmkxxx SYWKSvA== X-Google-Smtp-Source: AGHT+IHSxmkYaNVW+tpEbBadq3HejzPPH+5J3zGBjk1wnyNuIc2YhbpnYA07N2z1bjKPMr+aTtLaAg== X-Received: by 2002:a17:902:b48d:b0:1d7:323e:f362 with SMTP id y13-20020a170902b48d00b001d7323ef362mr2525328plr.120.1706416986320; Sat, 27 Jan 2024 20:43:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 19/33] tcg: Make tb_cflags() usable from target-agnostic code Date: Sun, 28 Jan 2024 14:41:59 +1000 Message-Id: <20240128044213.316480-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417082731100005 From: Ilya Leoshkevich Currently tb_cflags() is defined in exec-all.h, which is not usable from target-agnostic code. Move it to translation-block.h, which is. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Ilya Leoshkevich Reviewed-by: Richard Henderson Message-ID: <20231212003837.64090-3-iii@linux.ibm.com> Message-Id: <20240125054631.78867-3-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 6 ------ include/exec/translation-block.h | 6 ++++++ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index df3d93a2e2..ce36bb10d4 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -459,12 +459,6 @@ int probe_access_full_mmu(CPUArchState *env, vaddr add= r, int size, =20 #endif =20 -/* Hide the qatomic_read to make code a little easier on the eyes */ -static inline uint32_t tb_cflags(const TranslationBlock *tb) -{ - return qatomic_read(&tb->cflags); -} - static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb) { #ifdef CONFIG_USER_ONLY diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index e2b26e16da..48211c890a 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -145,4 +145,10 @@ struct TranslationBlock { /* The alignment given to TranslationBlock during allocation. */ #define CODE_GEN_ALIGN 16 =20 +/* Hide the qatomic_read to make code a little easier on the eyes */ +static inline uint32_t tb_cflags(const TranslationBlock *tb) +{ + return qatomic_read(&tb->cflags); +} + #endif /* EXEC_TRANSLATION_BLOCK_H */ --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417198; cv=none; d=zohomail.com; s=zohoarc; b=SCC8dpMbymL7Al1Bhpo6mMOd9G/zCQEwblQJFyCQ1Ddkg4zpwuWAcUSf6vABDDY5ZIDIF29f8MuiHK+XoO+EEibpUdG1fQsVMXLO0zBxvb1D/4SD1bEY099agaCWK2KVqHb0D29j2MRlAN7KkoivqW++bSK8tm0K9JE4L7eKfIs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417198; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TByYFDCUWCaxnnHjASz8MJMk4paFqdDSnL+kqN7t/Zk=; b=joqB9OFNpMVqvFX3Pf9CMKsNOJTxGW48mdV9otNqAlXSo3eavWFVgDW07XLk21feQxofGGkhsZSI6dskaedynnx5FVM/Jbna4nbN0HoEIJEmfUB9dSWI421UhhocjcIiNmWCjfySGpTiZ7+Cg13Po5h4YG3VxYA2MRjnyWRr72g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170641719866265.81011900136616; Sat, 27 Jan 2024 20:46:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx0i-0004qW-4x; Sat, 27 Jan 2024 23:43:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0h-0004q4-Bu for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:11 -0500 Received: from mail-oo1-xc35.google.com ([2607:f8b0:4864:20::c35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0f-0004Ms-TM for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:11 -0500 Received: by mail-oo1-xc35.google.com with SMTP id 006d021491bc7-59a146e8c85so791257eaf.0 for ; Sat, 27 Jan 2024 20:43:09 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416989; x=1707021789; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TByYFDCUWCaxnnHjASz8MJMk4paFqdDSnL+kqN7t/Zk=; b=eXVbQFpA+LwlZFCaBQFGeO7sBbwOFpHC+n0fqfHlnsGsrCQorVgeKYt3/KczxMixdM wrGi1d7xPh+MwKQoMQ5pMDYBOFBxUf/fHe/PAInQdvqZbJJveiEITSnUPZ3mfoDbQyMG QCsjiT5ljWld1z3cHeLY7fQTlxMUlsFqlJ01CzyBYlP3YDsOcRdkf632C1oJjeS5j41m G2zo3xWKbK5bmPbcMmvEgHp8THlNXwMiAQX/+e9mZivYEZxn5/7bjvL0FMVtvXgmqYkO pDZTaWEueUb+0ANvDCulyAlqORr65MSCizDjhb5CC7z44OW4276hLB//cC4PibsgNKEb eYCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416989; x=1707021789; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TByYFDCUWCaxnnHjASz8MJMk4paFqdDSnL+kqN7t/Zk=; b=UsSrDRgdVtNrp6lWlo+EOKnp8scB87+c2gHEgDQvkKLtn7oHST8quLMTHDaFlnMLCT MAErvj5zGoLJaVM/CmN+QK8AQ8+fKwYeTR+sMYPjo+JrLRk+NaQzfpcnYhcoR4MwzzSa SAdtyNUewBcEGJ4SKjM74JIlZBU8tpeuYAIfFTvi7ksTLYqrWjs9Z9Q4VHcixZI/AXSg 40N+Fld5kpTOMnJuDsfdcZGzuf+T4DcM69nWOXl9VDyd2eXaTA2kITowPcGWAkatsurC NoWpQSY0M2zI0CgQwj01snN0b/cMlO/L0hBcLBe1BEO5ZFGC/dz0eEVD9nBTdzpa86ac m2kA== X-Gm-Message-State: AOJu0YwFHCfr1LkDdYN6A3OzvA0g+ix0uNW9Ydq3zL6OznsnSvRus8qX yzFHDU7aspjK0EGMawzMDM33dzdETwCIxN9sOdevW070nkUY85YfiE4GmW6TwNTfzsW2h1OmVDY /2j3MGQ== X-Google-Smtp-Source: AGHT+IEGpw6L5swsr+ZUjpZfyryp3qm5R51U2sJW0Yl9+Ko5BkDSoHjb+W9SM5aSwGMBgov3iRSJUQ== X-Received: by 2002:a05:6358:7e9a:b0:175:cc50:56dc with SMTP id o26-20020a0563587e9a00b00175cc5056dcmr3369287rwn.58.1706416988777; Sat, 27 Jan 2024 20:43:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 20/33] accel/tcg: Remove #ifdef TARGET_I386 from perf.c Date: Sun, 28 Jan 2024 14:42:00 +1000 Message-Id: <20240128044213.316480-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c35; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417199005100001 From: Ilya Leoshkevich Preparation for moving perf.c to tcg/. This affects only profiling guest code, which has code in a non-0 based segment, e.g., 16-bit code, which is not particularly important. Suggested-by: Richard Henderson Signed-off-by: Ilya Leoshkevich Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-ID: <20231212003837.64090-4-iii@linux.ibm.com> Message-Id: <20240125054631.78867-4-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/perf.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/accel/tcg/perf.c b/accel/tcg/perf.c index ba75c1bbe4..68a46b1b52 100644 --- a/accel/tcg/perf.c +++ b/accel/tcg/perf.c @@ -337,10 +337,6 @@ void perf_report_code(uint64_t guest_pc, TranslationBl= ock *tb, q[insn].address =3D gen_insn_data[insn * start_words + 0]; if (tb_cflags(tb) & CF_PCREL) { q[insn].address |=3D (guest_pc & qemu_target_page_mask()); - } else { -#if defined(TARGET_I386) - q[insn].address -=3D tb->cs_base; -#endif } q[insn].flags =3D DEBUGINFO_SYMBOL | (jitdump ? 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416991; x=1707021791; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MmzrBNQK2eDwb+/K0EzCDtsTU1SD4iiHNXZIgeBMj8o=; b=vRjIfXPxMyRLJTNekl6NbOsj9QO9j8qwiupc70GQDG+iuEWrC/UPeqTlMjqvD9g4Fa 36RIFoODWN/mYaLKygNxSOh07EuYJ0D/7jJ6qNuqmSEbKcJgocKLGtbjX7zzPw8epU9M QUooiGMt7AT/yYbpTVVjYz6axtcEv09kRbtEGeSHOeAXVMdhwfhswQKwXjpjddI2SpgP Xk5YDPKj3J26M71lGMsXHNR3PXTsTH2FRBqkoyvXX8Ya/In0t518e20uC0Ek4ZNnKuVT n7gO4a0J3A/XfrSZ9Sqyux6yAYF4ZSXDBy1WXXuAqIbuixAd2mBvp0wNyxid5J4Nsuxl IvGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416991; x=1707021791; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MmzrBNQK2eDwb+/K0EzCDtsTU1SD4iiHNXZIgeBMj8o=; b=l+VWmQSW3c23ZSdR0pjbP651aYSHNK0RRUaADLXVTwz6TfRaufmsEcg56lsVPXzXRv TLT3tmw9KfSzvb0jvh6wRvAwzrc7rWpeoUs1zLobuCSEajCX+qwp57y62cdH0X/5mOdO hssW/M9alYJECL1lQ4dr/4VyE08bpNpBknn/NHcxOFtSKlFUrgiqfohY41ftxv9IYLak J4Mrb0sp5GDdG5OPTTNYDKN3ccfI0pUHOgXb+nmxtzJ8okoZNIwVlw1jWfOkJJzMdg9z DtQfmbkzlr/LVSV2QA4ujSjcKm/bx0JvVJE/3B0V3O0VnOGFNXPgoq+za6FJo/pAIX2P K83A== X-Gm-Message-State: AOJu0Yz1GOzzzHpWPxek+4Suuyt4O9CjjiEzH48hgVQD+iJ9anoVCDJa bS5rM2g8OFKK1jmcUX1zDIMPZdeTezjJ5SZXrZAsPXQXuTVpRBspppP0mwQ2Rm3Z5Ed12g6r9z6 3tTWUTg== X-Google-Smtp-Source: AGHT+IEIwfPUza5qgF0gE06/OTfMMSTGPHQwndJayvLAPrpArArD0DCVNMgMHD01RYIe+YdmmHI/jA== X-Received: by 2002:a05:6358:16c7:b0:176:8447:63be with SMTP id r7-20020a05635816c700b00176844763bemr3324212rwl.55.1706416991424; Sat, 27 Jan 2024 20:43:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 21/33] accel/tcg: Move perf and debuginfo support to tcg/ Date: Sun, 28 Jan 2024 14:42:01 +1000 Message-Id: <20240128044213.316480-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c30; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417052721100003 From: Ilya Leoshkevich tcg/ should not depend on accel/tcg/, but perf and debuginfo support provided by the latter are being used by tcg/tcg.c. Since that's the only user, move both to tcg/. Suggested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Ilya Leoshkevich Reviewed-by: Richard Henderson Message-ID: <20231212003837.64090-5-iii@linux.ibm.com> Message-Id: <20240125054631.78867-5-philmd@linaro.org> Signed-off-by: Richard Henderson --- {accel =3D> include}/tcg/debuginfo.h | 4 ++-- {accel =3D> include}/tcg/perf.h | 4 ++-- accel/tcg/translate-all.c | 2 +- hw/core/loader.c | 2 +- linux-user/elfload.c | 2 +- linux-user/exit.c | 2 +- linux-user/main.c | 2 +- system/vl.c | 2 +- {accel/tcg =3D> tcg}/debuginfo.c | 3 +-- {accel/tcg =3D> tcg}/perf.c | 7 +++---- tcg/tcg.c | 2 +- accel/tcg/meson.build | 4 ---- tcg/meson.build | 5 +++++ 13 files changed, 20 insertions(+), 21 deletions(-) rename {accel =3D> include}/tcg/debuginfo.h (96%) rename {accel =3D> include}/tcg/perf.h (95%) rename {accel/tcg =3D> tcg}/debuginfo.c (98%) rename {accel/tcg =3D> tcg}/perf.c (99%) diff --git a/accel/tcg/debuginfo.h b/include/tcg/debuginfo.h similarity index 96% rename from accel/tcg/debuginfo.h rename to include/tcg/debuginfo.h index f064e1c144..858535b5da 100644 --- a/accel/tcg/debuginfo.h +++ b/include/tcg/debuginfo.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ =20 -#ifndef ACCEL_TCG_DEBUGINFO_H -#define ACCEL_TCG_DEBUGINFO_H +#ifndef TCG_DEBUGINFO_H +#define TCG_DEBUGINFO_H =20 #include "qemu/bitops.h" =20 diff --git a/accel/tcg/perf.h b/include/tcg/perf.h similarity index 95% rename from accel/tcg/perf.h rename to include/tcg/perf.h index f92dd52c69..c96b5920a3 100644 --- a/accel/tcg/perf.h +++ b/include/tcg/perf.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ =20 -#ifndef ACCEL_TCG_PERF_H -#define ACCEL_TCG_PERF_H +#ifndef TCG_PERF_H +#define TCG_PERF_H =20 #if defined(CONFIG_TCG) && defined(CONFIG_LINUX) /* Start writing perf-.map. */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 1737bb3da5..1c695efe02 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -63,7 +63,7 @@ #include "tb-context.h" #include "internal-common.h" #include "internal-target.h" -#include "perf.h" +#include "tcg/perf.h" #include "tcg/insn-start-words.h" =20 TBContext tb_ctx; diff --git a/hw/core/loader.c b/hw/core/loader.c index e7a9b3775b..b8e52f3fb0 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -62,7 +62,7 @@ #include "hw/boards.h" #include "qemu/cutils.h" #include "sysemu/runstate.h" -#include "accel/tcg/debuginfo.h" +#include "tcg/debuginfo.h" =20 #include =20 diff --git a/linux-user/elfload.c b/linux-user/elfload.c index daf7ef8435..b8eef893d0 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -22,7 +22,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "target_signal.h" -#include "accel/tcg/debuginfo.h" +#include "tcg/debuginfo.h" =20 #ifdef TARGET_ARM #include "target/arm/cpu-features.h" diff --git a/linux-user/exit.c b/linux-user/exit.c index 50266314e0..1ff8fe4f07 100644 --- a/linux-user/exit.c +++ b/linux-user/exit.c @@ -17,7 +17,7 @@ * along with this program; if not, see . */ #include "qemu/osdep.h" -#include "accel/tcg/perf.h" +#include "tcg/perf.h" #include "gdbstub/syscalls.h" #include "qemu.h" #include "user-internals.h" diff --git a/linux-user/main.c b/linux-user/main.c index c9470eeccf..74b2fbb393 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -54,7 +54,7 @@ #include "signal-common.h" #include "loader.h" #include "user-mmap.h" -#include "accel/tcg/perf.h" +#include "tcg/perf.h" =20 #ifdef CONFIG_SEMIHOSTING #include "semihosting/semihost.h" diff --git a/system/vl.c b/system/vl.c index 788d88ea03..60fd1e56b6 100644 --- a/system/vl.c +++ b/system/vl.c @@ -96,7 +96,7 @@ #endif #include "sysemu/qtest.h" #ifdef CONFIG_TCG -#include "accel/tcg/perf.h" +#include "tcg/perf.h" #endif =20 #include "disas/disas.h" diff --git a/accel/tcg/debuginfo.c b/tcg/debuginfo.c similarity index 98% rename from accel/tcg/debuginfo.c rename to tcg/debuginfo.c index 71c66d04d1..3753f7ef67 100644 --- a/accel/tcg/debuginfo.c +++ b/tcg/debuginfo.c @@ -6,11 +6,10 @@ =20 #include "qemu/osdep.h" #include "qemu/lockable.h" +#include "tcg/debuginfo.h" =20 #include =20 -#include "debuginfo.h" - static QemuMutex lock; static Dwfl *dwfl; static const Dwfl_Callbacks dwfl_callbacks =3D { diff --git a/accel/tcg/perf.c b/tcg/perf.c similarity index 99% rename from accel/tcg/perf.c rename to tcg/perf.c index 68a46b1b52..412a987d95 100644 --- a/accel/tcg/perf.c +++ b/tcg/perf.c @@ -11,13 +11,12 @@ #include "qemu/osdep.h" #include "elf.h" #include "exec/target_page.h" -#include "exec/exec-all.h" +#include "exec/translation-block.h" #include "qemu/timer.h" +#include "tcg/debuginfo.h" +#include "tcg/perf.h" #include "tcg/tcg.h" =20 -#include "debuginfo.h" -#include "perf.h" - static FILE *safe_fopen_w(const char *path) { int saved_errno; diff --git a/tcg/tcg.c b/tcg/tcg.c index e2c38f6d11..eeff4c1d51 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -55,7 +55,7 @@ #include "tcg/tcg-ldst.h" #include "tcg/tcg-temp-internal.h" #include "tcg-internal.h" -#include "accel/tcg/perf.h" +#include "tcg/perf.h" #ifdef CONFIG_USER_ONLY #include "exec/user/guest-base.h" #endif diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index c15ac9ac8f..46f7d53eeb 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -16,10 +16,6 @@ tcg_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files('= user-exec-stub.c')) if get_option('plugins') tcg_ss.add(files('plugin-gen.c')) endif -tcg_ss.add(when: libdw, if_true: files('debuginfo.c')) -if host_os =3D=3D 'linux' - tcg_ss.add(files('perf.c')) -endif specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) =20 specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( diff --git a/tcg/meson.build b/tcg/meson.build index 5afdec1e1a..8251589fd4 100644 --- a/tcg/meson.build +++ b/tcg/meson.build @@ -22,6 +22,11 @@ if get_option('tcg_interpreter') tcg_ss.add(files('tci.c')) endif =20 +tcg_ss.add(when: libdw, if_true: files('debuginfo.c')) +if host_os =3D=3D 'linux' + tcg_ss.add(files('perf.c')) +endif + tcg_ss =3D tcg_ss.apply({}) =20 libtcg_user =3D static_library('tcg_user', --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416994; x=1707021794; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XRwZFjq4cQsQYmD6HoikyRyAnRDJPSlCSVsphAQE8HU=; b=JfHO/C6CexIZQrUYSOn3R/sQ43j985rFR7lFYvbNRffAS8XJhohfNwPid2Oo2/v77I rGjVkVG6eloxX2x4FIhd4eJOndd5Y6zhqS3VWKbzb7UdoBmNt2nFKWMrFt66uTgMb4/A 2waXY07cYvcqcqlznhL/gYYkFvZ7+pzNO6jKtyqGNBDr3qwUl8rJZgrwFCgNUWpnxKc3 rqXm5g98E2/lP/SO7W1J2W0Q9lP7KgMNzP7KV2RYEgxQiKO8cBU+Ykgfcoj/tow3zG8W dINNOdmVUlWlhigZB8NwXbQgTf+Rad/or1IpK7F2gWlKvr9hF8LU4qXENpVtk5FXB0f2 l3ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416994; x=1707021794; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XRwZFjq4cQsQYmD6HoikyRyAnRDJPSlCSVsphAQE8HU=; b=M2pMoFT/G8uR7Tl+GaJVLSfxZw/f6x/x6mqsPjnOtmDIgiGjIiI3fNaL6te26M7nhv jpqRPLDA9JX557eulX2kK1K8i8GDowITEw/OKu0MRMTNCOqzagq9qgUffeT0ccsdxecJ FypAaP+ZfoDunXXWVaKXS0kEdHj26qVAcCHK5m+9Gu103QO3x0PSDJ19FNZNcxPwtQYY eY1XP1avnNxuUIbA+7M9kPcIwYdZmN8nB06Eu/lgsc46AGXi5lS6psEBn7k1Qskfgkkv uQ49vpqWBrQ5ZEk3oiGP1Rr05e/awljWS0LaOV64rBQLLN91FANQcdin4itNqHlX9COT H+Uw== X-Gm-Message-State: AOJu0YzPUQq5SyYYedd86xbfMMDVoV/OLXGMQVXhMRyc+IA0/MS59L1c 4nt3Qbrg/okG80/TPYulv3W97ugUVn5pLEmGsEk4lDMoCqBvdv+lr0B2iPEV3EQt+s2Gw3ZbOmx oeT96WA== X-Google-Smtp-Source: AGHT+IFf5VDv0qrWyaCdSk7ZrzOKkG8LZjY13R2JGKdb0BbdNiddE/J4+bBv8HK9sTNp/C4ifdGqHg== X-Received: by 2002:a05:622a:245:b0:42a:7092:c7fd with SMTP id c5-20020a05622a024500b0042a7092c7fdmr4739463qtx.135.1706416994099; Sat, 27 Jan 2024 20:43:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson Subject: [PATCH 22/33] accel/tcg: Rename tcg_ss[] -> tcg_specific_ss[] in meson Date: Sun, 28 Jan 2024 14:42:02 +1000 Message-Id: <20240128044213.316480-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417225093100001 From: Philippe Mathieu-Daud=C3=A9 tcg_ss[] source set contains target-specific units. Rename it as 'tcg_specific_ss[]' for clarity. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20240124101639.30056-2-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/meson.build | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 46f7d53eeb..aef80de967 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -1,8 +1,8 @@ -tcg_ss =3D ss.source_set() common_ss.add(when: 'CONFIG_TCG', if_true: files( 'cpu-exec-common.c', )) -tcg_ss.add(files( +tcg_specific_ss =3D ss.source_set() +tcg_specific_ss.add(files( 'tcg-all.c', 'cpu-exec.c', 'tb-maint.c', @@ -11,12 +11,12 @@ tcg_ss.add(files( 'translate-all.c', 'translator.c', )) -tcg_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c')) -tcg_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files('user-exec-stub.c')) +tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'= )) +tcg_specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files('user-exec= -stub.c')) if get_option('plugins') - tcg_ss.add(files('plugin-gen.c')) + tcg_specific_ss.add(files('plugin-gen.c')) endif -specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) +specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) =20 specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417186; cv=none; d=zohomail.com; s=zohoarc; b=drJA8vpuIVWRgmXH3y6AcMPkc/84og2w/K15mqAEhSu3K5cGgrrwhH047QtQvtnk4R3WQZ1pQn6YBpg6F4Zp1Rmc3/iD0DFhQkbgopAbYyFPtohrMOxoHJVgGrRJUcc6ybqwUbAcUQ+JCd+pDBbXmiD/tCVIpatDbIiQYnxgF/Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417186; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IeBfHlDAifxu4F1/UNQzzGCEUArq4HbYf2mScaRZKZ4=; b=mMuxjeMyq8SsNAoUFbw40RwX6tJ9gq3P0zDK9QB0Tu7cUoT23uSBhVWb83M/+c/AtvgBs1P4JB+ltw/lC8XXsHGSZsGagqK1OPKwWGJKKjdlfVzb54YsLo1DQ7Il6EwvLAZUyaibfal/FOcOas5jFWqKZbAR3s2KeJcjoZzYM0I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417186031319.696059403155; Sat, 27 Jan 2024 20:46:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx0r-00051U-Em; Sat, 27 Jan 2024 23:43:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0p-0004yE-ON for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:19 -0500 Received: from mail-oo1-xc2a.google.com ([2607:f8b0:4864:20::c2a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0o-0004No-67 for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:19 -0500 Received: by mail-oo1-xc2a.google.com with SMTP id 006d021491bc7-59a146e8c85so791279eaf.0 for ; Sat, 27 Jan 2024 20:43:17 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416996; x=1707021796; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IeBfHlDAifxu4F1/UNQzzGCEUArq4HbYf2mScaRZKZ4=; b=f7FzQJha1UfDYDFRCNrnaD3VeweiPjO/5FeGsz/F+3eUdoWLc2ZRvzz4JcaQFkywXy MWw7ae606x3e9OId4KlSfF7a/h+mZfKvtY+PxKOHEelY4llYIoxq6SxqSUd6tNm10S6m unbWAalSfDwgtPgbjMEmwOahddDDb0yVy7lexXmpHxXfhvixYXhrsxfb9v1geXqOah3X 34EVUO2gpmYoj/M+GRD3wRB9kSWyR+3xnuKS+ExKHdikRZG4aCmFEER/VUpcd+2WqhsJ fHpQgFbjtwdfqdsYq14mO8Bbb2+ZQvPi3CQJYW8SUh07KkQR13xuJEFZ32ZlZRmDVEMl LvXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416996; x=1707021796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IeBfHlDAifxu4F1/UNQzzGCEUArq4HbYf2mScaRZKZ4=; b=RXfF5z0FCuy7TXP6qjVy8UmT4Qghp1oXgDpfYOoawDsDFqHH/oxnNoS3U43t5sGd2T JD1B0WJITGgjsc5TPVoQKN4hOQaNfXlKlenldC+5SqikOB3i/rhNQryKgNZvC2U5mvkG zf/9n2045WYnfIS+43xit3EbDkT//H99Suuu9oocDkIGR5MSvHS3lWG6t9VA9vR0j7UI 6nPD9/w/N2xobWPRZUEVDwP4TSdCcMrLkzK6MMMyHHAASYpX74/hMwYF3GvFkk4KPMII QxLRUObBC76ZlfMqd6jwbuqleZZYKYdTKAZuFT3c54Cw7mcoQk0sQl7bxqYwhVrL1D3s oU/w== X-Gm-Message-State: AOJu0YzBeobvUNyDjV9iLFXMDY0G9nhNNDQDTDE2Dw3WmIx5PUmzqaor q9tMxww7epTZNZ6/+aCQTOMDHDW3cQXK+L7my5KuCeD6mivA94sz7YYB0yiaBebdMh4xSr+oqYh p6e12+w== X-Google-Smtp-Source: AGHT+IFIsbMAm27bHgb/fNYmCECZyibW1Is462S9l3popKVjMfdcT4tGfggiA1O1MgCZiQc5lq2ePg== X-Received: by 2002:a05:6358:3a14:b0:176:cf6e:51fc with SMTP id g20-20020a0563583a1400b00176cf6e51fcmr3089000rwe.53.1706416996717; Sat, 27 Jan 2024 20:43:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson Subject: [PATCH 23/33] accel/tcg: Rename tcg_cpus_destroy() -> tcg_cpu_destroy() Date: Sun, 28 Jan 2024 14:42:03 +1000 Message-Id: <20240128044213.316480-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2a; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417186994100003 From: Philippe Mathieu-Daud=C3=A9 tcg_cpus_destroy() operates on a single vCPU, rename it as 'tcg_cpu_destroy'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Message-Id: <20240124101639.30056-3-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/tcg-accel-ops.h | 2 +- accel/tcg/tcg-accel-ops-mttcg.c | 2 +- accel/tcg/tcg-accel-ops-rr.c | 2 +- accel/tcg/tcg-accel-ops.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/accel/tcg/tcg-accel-ops.h b/accel/tcg/tcg-accel-ops.h index f9bc6330e2..17c7ed00eb 100644 --- a/accel/tcg/tcg-accel-ops.h +++ b/accel/tcg/tcg-accel-ops.h @@ -14,7 +14,7 @@ =20 #include "sysemu/cpus.h" =20 -void tcg_cpus_destroy(CPUState *cpu); +void tcg_cpu_destroy(CPUState *cpu); int tcg_cpus_exec(CPUState *cpu); void tcg_handle_interrupt(CPUState *cpu, int mask); void tcg_cpu_init_cflags(CPUState *cpu, bool parallel); diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttc= g.c index af7307013a..bcba314a65 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -118,7 +118,7 @@ static void *mttcg_cpu_thread_fn(void *arg) qemu_wait_io_event(cpu); } while (!cpu->unplug || cpu_can_run(cpu)); =20 - tcg_cpus_destroy(cpu); + tcg_cpu_destroy(cpu); bql_unlock(); rcu_remove_force_rcu_notifier(&force_rcu.notifier); rcu_unregister_thread(); diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 3208035d85..0617f66b5b 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -131,7 +131,7 @@ static void rr_deal_with_unplugged_cpus(void) =20 CPU_FOREACH(cpu) { if (cpu->unplug && !cpu_can_run(cpu)) { - tcg_cpus_destroy(cpu); + tcg_cpu_destroy(cpu); break; } } diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 813065c0ec..9b84b84218 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -63,7 +63,7 @@ void tcg_cpu_init_cflags(CPUState *cpu, bool parallel) cpu->tcg_cflags |=3D cflags; } =20 -void tcg_cpus_destroy(CPUState *cpu) +void tcg_cpu_destroy(CPUState *cpu) { cpu_thread_signal_destroyed(cpu); } --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417071; cv=none; d=zohomail.com; s=zohoarc; b=PgFcbnE0+isD6BQSrMaCs9UxOhY4TZnT8N4TvketyN7PAQX/Uu/wzi1Izwt+WM4A5cMJnWsD17Zu2/Ow/Y/nsvZ8nGnBed3VKaqPP2X7ucXh1tqqGfLo3/Q56arM6hklQjq1kE3scLNZDD2Ub3M2CeErl0OQgt525wKiFtpydSc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417071; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=h0D5wvbqCBKDS3PIRJ2u8mID+Ysdp5Zl/usWtkQWmMI=; b=CBOwpKgoTJ4pMhks/edFrY0scPJ6g7I5q3BSy0aHjVP/KQQb8W60CuHp1MNKK478prfs5jwiCYpX+BEWE3aad9Rc810P9NQrs6gMBTGnHlDwBCqmaNQh6l7aHy2K+PQRktq4tITyv/Nx/yFQ9PMPFO5u4Lu52mEOq0ywYPbytqQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417071242602.8973380985298; Sat, 27 Jan 2024 20:44:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx0w-00059V-9p; Sat, 27 Jan 2024 23:43:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0t-00057j-2D for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:23 -0500 Received: from mail-oo1-xc2c.google.com ([2607:f8b0:4864:20::c2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0r-0004O0-CR for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:22 -0500 Received: by mail-oo1-xc2c.google.com with SMTP id 006d021491bc7-59a146e8c85so791288eaf.0 for ; Sat, 27 Jan 2024 20:43:20 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706416999; x=1707021799; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h0D5wvbqCBKDS3PIRJ2u8mID+Ysdp5Zl/usWtkQWmMI=; b=XVvQXq9b9AZgSDqXxGtk+ZbtbxJxcjbkTID/4TV8dAJ7BFKYSMO+wee1yKBF8zX9AX 0EsL8coekG18V3DienXN6MZLia0u53pO1Uv0Yv2D92AmQuumR44SFO97rZtwlHTDpBmi ST2kBZcvnS/JLitBaR11cSE2BljB/gSjivCKrxGlEUngJYFdl+7BemmMLV1sbCah/rq9 oqGl/BKIsPV6cSSmR1744IETlwxrlX2eK9fTHTwjEMqn1doKP6g/5rKjyxF54rKmP9Cf u3j9OeZW9AceSUYUps4uGltEOo6qWTE8RYa1/bEBSCV5irwsg1K/n0+9b3pkOFWB9+Jj uUMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706416999; x=1707021799; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h0D5wvbqCBKDS3PIRJ2u8mID+Ysdp5Zl/usWtkQWmMI=; b=koI6B73XJYppZ56VElRXGlRNk1BzWXaKeFYXfquSJTrsnRGldD77naxUw917Yh+NEP ocAT5R7l57AfBQFoKGEg/nr6/jTzPX/0IQMqe6BNWGL07B/trMSICTwY63b24/L/yZ7f ye9owoYuOwT/gq/Nbw3/iPfQ8KrsqCb41eYeIilwLySom0ZsI8uza+G3TJc8hwEkSlur ZN7ZT83FN2kyzmVUJhd2ss031s0rRkKtYA1iM+KvwdpjP5BbHjWPK4KvrWawWH8z/oCx aCXIIBpRCy1r7McJz5HXDirVnND9BwPbcOaz2YJOXd1U4coZ2cuQ6QnmkxQCBYP8i4/H mvnQ== X-Gm-Message-State: AOJu0YyUmDbQqO1P/mXQLjbRfADhj5zxhRQXO03E5iW7cwXvguoUJlAN Vh6oVCyVdQ57kWEeHA2T4H9xf77mHOEp9Ew/aFAkY4PV8XY/wdtWT5do+dDhY7Yfp4Nnb3yFe7T nZnkvlA== X-Google-Smtp-Source: AGHT+IHYzL/aBOCLYjBLQ292BGC5ogjO6YZiEBee4x3+woyQD1QpkzzHqB35QvJSUMG64YX+FaxB1g== X-Received: by 2002:a05:6358:9490:b0:170:e2dc:3e19 with SMTP id i16-20020a056358949000b00170e2dc3e19mr2487468rwb.43.1706416999172; Sat, 27 Jan 2024 20:43:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson Subject: [PATCH 24/33] accel/tcg: Rename tcg_cpus_exec() -> tcg_cpu_exec() Date: Sun, 28 Jan 2024 14:42:04 +1000 Message-Id: <20240128044213.316480-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417072718100003 From: Philippe Mathieu-Daud=C3=A9 tcg_cpus_exec() operates on a single vCPU, rename it as 'tcg_cpu_exec'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20240124101639.30056-4-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/tcg-accel-ops.h | 2 +- accel/tcg/tcg-accel-ops-mttcg.c | 2 +- accel/tcg/tcg-accel-ops-rr.c | 2 +- accel/tcg/tcg-accel-ops.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/accel/tcg/tcg-accel-ops.h b/accel/tcg/tcg-accel-ops.h index 17c7ed00eb..44c4079972 100644 --- a/accel/tcg/tcg-accel-ops.h +++ b/accel/tcg/tcg-accel-ops.h @@ -15,7 +15,7 @@ #include "sysemu/cpus.h" =20 void tcg_cpu_destroy(CPUState *cpu); -int tcg_cpus_exec(CPUState *cpu); +int tcg_cpu_exec(CPUState *cpu); void tcg_handle_interrupt(CPUState *cpu, int mask); void tcg_cpu_init_cflags(CPUState *cpu, bool parallel); =20 diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttc= g.c index bcba314a65..c552b45b8e 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -92,7 +92,7 @@ static void *mttcg_cpu_thread_fn(void *arg) if (cpu_can_run(cpu)) { int r; bql_unlock(); - r =3D tcg_cpus_exec(cpu); + r =3D tcg_cpu_exec(cpu); bql_lock(); switch (r) { case EXCP_DEBUG: diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 0617f66b5b..894e73e52c 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -258,7 +258,7 @@ static void *rr_cpu_thread_fn(void *arg) if (icount_enabled()) { icount_prepare_for_run(cpu, cpu_budget); } - r =3D tcg_cpus_exec(cpu); + r =3D tcg_cpu_exec(cpu); if (icount_enabled()) { icount_process_data(cpu); } diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 9b84b84218..9c957f421c 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -68,7 +68,7 @@ void tcg_cpu_destroy(CPUState *cpu) cpu_thread_signal_destroyed(cpu); } =20 -int tcg_cpus_exec(CPUState *cpu) +int tcg_cpu_exec(CPUState *cpu) { int ret; assert(tcg_enabled()); --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417108; cv=none; d=zohomail.com; s=zohoarc; b=d1Wb8n4uvqc9BJsjmUvgkjrG+8q/iOSoSYc2OGzfYQpU0ppur6clZ7U9YUD1iJw72Af8NhN1CaxtM3jT7hYJufcNnB/TCPd2NbKwfO1CTxzcAQxTTZwIl/LD0u5OjfdaCqvPj3ecCIhehzidqtvwejIs8/cTRF5nXr4No532d5M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417108; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zfMhTQxwxgwjYRWhH0P+ZcfoxncjyISGzQ2K+4rTjEw=; b=Pbddx5hwMaH4rvN7woLyQxhizt0DaZEzfTPmDE6veQmk01juFdYyD36/mSukpZ11nP8LF9fVLCGgiyS7a5BwXrPML4FyuWxkqLqGYXxxkD1opq0GqH/YxcQuhJRMT7Y1kKpwv9baTS8o+sqYoURjn+LHs6dhJog9RtgR5OggTtk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417108371933.4397488208317; Sat, 27 Jan 2024 20:45:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx0w-00059o-Tc; Sat, 27 Jan 2024 23:43:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0u-00058j-Qg for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:24 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0t-0004OC-2E for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:24 -0500 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-290d59df3f0so1351615a91.2 for ; Sat, 27 Jan 2024 20:43:22 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706417002; x=1707021802; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zfMhTQxwxgwjYRWhH0P+ZcfoxncjyISGzQ2K+4rTjEw=; b=T7y1ebxaIU/WGVJL0aecfKq+bcNOYUHaHSk/DfSC3zaIoFaglj0uSdOl05AtdTgTvI 5iaOjEi0vimG2jYNlOac8go+brs0MsESjYmeLLL3TtWiGq8xk0ZLAiW8d3fODN5/+x1V WsrXElBk8qwZBT5Pyin0nGL8ragHJRxIu1JdY5rCxSY+wNiGTV+Cl6Ae9CZVxxoJZdnu dEhU55u/R6K32ElRvmzUOn6Bv8+5qma79YTXlbAW5Jvsd6Y1XbzROMBghto+Vt54qz3a RlUUhYSuByhU9BugpkWZX1RwCPQeMzfjKHu0gIAjeejIUr0Lhg1GLI9Rs2gscmh22DRx DZ1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706417002; x=1707021802; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zfMhTQxwxgwjYRWhH0P+ZcfoxncjyISGzQ2K+4rTjEw=; b=j8Ku3xNgP1aBBGDmnsLsvFLFn9s5mDo11aorlq0jfKBxoXmWW1f7Q3h3Dw6rMihf1M rgvGsu9WehRqzGHvNyfcl0Xl5LvTtkcDlLQI1dOSMPdS3uYxW0ysW2LuvH47j/CUmTct 6zBMx41Ovbey81Ixf1M3IR++MOb01FAGz+thPZV+pESTrJSZbFcdcEjvUU4nTaoMHpIi a4Rjzn9Ahowc7DqDg1Xq4caA2z48R3fgPv6Nb15aTs3Sw9CEMtiEwR5PbY8UVysy8geA xRlIRCbo7xlWJf2xcTWJA3S8Y4gY+hP3m+GT4sYbzWgjdV1WAXZiGec1pUHrWKmvzmMb ppig== X-Gm-Message-State: AOJu0YyS5TPjP2SNIqrsSPB8u07QmsolK1KVreMPDSUvvvcmk90ATyVv Udbn1aI9jz8DyLYkwmJJI5Ng00dU7oUMSPa15+mdOuVTQ3h5iuNnvByj/s8Eer0FIHKKoHIkRfF 9dY3J4g== X-Google-Smtp-Source: AGHT+IFt+x+DQT2Oi6Fi2cZra8uEXcbNk4SD2wfKUGSSUS2B+/rqkiIQwYQzs3Z/1PxO9pzA2IASrQ== X-Received: by 2002:a17:90a:b398:b0:290:f7a7:333d with SMTP id e24-20020a17090ab39800b00290f7a7333dmr1569016pjr.36.1706417001755; Sat, 27 Jan 2024 20:43:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson Subject: [PATCH 25/33] accel/tcg: Un-inline icount_exit_request() for clarity Date: Sun, 28 Jan 2024 14:42:05 +1000 Message-Id: <20240128044213.316480-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417108823100001 From: Philippe Mathieu-Daud=C3=A9 Convert packed logic to dumb icount_exit_request() helper. No functional change intended. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20240124101639.30056-5-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 950dad63cb..f2535a2991 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -777,6 +777,17 @@ static inline bool need_replay_interrupt(int interrupt= _request) } #endif /* !CONFIG_USER_ONLY */ =20 +static inline bool icount_exit_request(CPUState *cpu) +{ + if (!icount_enabled()) { + return false; + } + if (cpu->cflags_next_tb !=3D -1 && !(cpu->cflags_next_tb & CF_USE_ICOU= NT)) { + return false; + } + return cpu->neg.icount_decr.u16.low + cpu->icount_extra =3D=3D 0; +} + static inline bool cpu_handle_interrupt(CPUState *cpu, TranslationBlock **last_tb) { @@ -882,10 +893,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, } =20 /* Finally, check if we need to exit to the main loop. */ - if (unlikely(qatomic_read(&cpu->exit_request)) - || (icount_enabled() - && (cpu->cflags_next_tb =3D=3D -1 || cpu->cflags_next_tb & CF_= USE_ICOUNT) - && cpu->neg.icount_decr.u16.low + cpu->icount_extra =3D=3D 0))= { + if (unlikely(qatomic_read(&cpu->exit_request)) || icount_exit_request(= cpu)) { qatomic_set(&cpu->exit_request, 0); if (cpu->exception_index =3D=3D -1) { cpu->exception_index =3D EXCP_INTERRUPT; --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417172; cv=none; d=zohomail.com; s=zohoarc; b=PqtjcEDRxAiF/9lNz8Owdz5PsmN4RaT9/3se4ZzwvFMI7Yvc9wlL6YQD4uX4otTVmHvqWO0hYUApwUl2gikcjuAo98+JZb6uKu3WilyNjTpkC1RQqEx8fIqXhQ1hYZRRfaNpuqfSQnbbCqz8+9QWWQbLi6Ovq8kFFQkED9ci9N0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417172; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=fDrlqZJJ0WFNjsqbAt49Vqu9oOvOnIDnuEZmci/Hrlo=; b=Oj7+gs4YcXKA7lrA7vg3Itg/y24ayXL9Bj0GANWJ91CIifh9YRVDz+jUZeMv/itphaxw1xq6RDbQy/n/RDXUcK7p4shb2HQ+YOuFEPlQeUD3tMroA7MNsF/E+1Zwwshk90ihyy7L5sheUvHlebWyra8MCc/7VardKEmnI8BNxBM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417172077597.0652086505887; Sat, 27 Jan 2024 20:46:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx13-0005D8-Fw; Sat, 27 Jan 2024 23:43:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx0y-0005Ah-Cq for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:28 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx0v-0004OO-Gl for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:27 -0500 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1d51ba18e1bso17846945ad.0 for ; Sat, 27 Jan 2024 20:43:25 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706417004; x=1707021804; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fDrlqZJJ0WFNjsqbAt49Vqu9oOvOnIDnuEZmci/Hrlo=; b=G3thYD7Hi0FxzXc24i5PY6XCFBTwwssQngC59XDGDBDBoEVmM9DhxFVOlwgPRZGhiP VQ35llQ3vprFPLI+3y6wMREzePkL5YlZRYrLTx8pWo5L4jvLSqVhuw0dRNz7hNqQYkDX 9BawaxutgHSVqLS2Q/OwxPGQfW+EX1lOvTp1tAmhzpsYfsVFvcYGv8gDoARPBu3a0SZL KtZWJE12610xN4HE9X7taDJWuQF4yUtmlv3cvHoq6hfuAtdEc2d86kQcuptbp93UV6tG yr+6qJ+wahGT/rDmLsVgW0jXVVf1YsAGyCJ9s2WuyUKEy3tDuTkF9RNq/bko7ncCmjum Gtkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706417004; x=1707021804; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fDrlqZJJ0WFNjsqbAt49Vqu9oOvOnIDnuEZmci/Hrlo=; b=Vjt7CGLPJNKETmhnAuHQROUQgqJ5xUWvDquKxD0P4x/z2c2g6U7+A0gpbT8h71+9qZ CtLbJxqp9BZUks/ci+FvfVqCh5c2D6E2t+/bjLAw2Url5yjtZQA+LiHtmtzPKVC5W4vm 0JWQvSXbmmXdE28lXoHwfBS6IW2Crh+yd+tSfgp/w4OrK+PUWCQQcbSvwmXnlk+va3e/ n2qo2QnymJkvGenwrp/Xoq/1AA4WfH+pHAbJSLhSnENzK3kPeKg/BfUC07F408btS8Gr y7/wMe5fw/VeXZ4ewph3r4ZQ3tD0V+M0GAA7/4OFLmgiYvi0RYlneJ5XRUC+djpRlQlK eR/Q== X-Gm-Message-State: AOJu0Ywm78qi1986TPTVMupVYzRJxKgdNyW1cGAHFF72VtwDkpnDKgPG uIH8JZu/mgiFrzzzq2yqqBpsHiURcUscFqXPg+BT5IqlH5FTQNkSFHqQ0mQRLgUHt6PcQcNzaFW J3oQXcg== X-Google-Smtp-Source: AGHT+IHLORWmHjOGBfVxW2ppm2CRKT4gXuHf6Zzm/QGW1hmYU8Ci1BeVSt5LgdYNFh56Rntddnp8RA== X-Received: by 2002:a17:903:41c8:b0:1d8:d3e8:c31c with SMTP id u8-20020a17090341c800b001d8d3e8c31cmr246672ple.105.1706417003986; Sat, 27 Jan 2024 20:43:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 26/33] include/qemu: Add TCGCPUOps typedef to typedefs.h Date: Sun, 28 Jan 2024 14:42:06 +1000 Message-Id: <20240128044213.316480-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417172931100001 Content-Type: text/plain; charset="utf-8" QEMU coding style recommends using structure typedefs. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 5 +---- include/qemu/typedefs.h | 1 + bsd-user/signal.c | 4 ++-- linux-user/signal.c | 4 ++-- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/arm/tcg/cpu32.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 4 ++-- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 26 files changed, 29 insertions(+), 31 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index db58f12233..2c284d6397 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -90,9 +90,6 @@ typedef enum MMUAccessType { =20 typedef struct CPUWatchpoint CPUWatchpoint; =20 -/* see tcg-cpu-ops.h */ -struct TCGCPUOps; - /* see accel-cpu.h */ struct AccelCPUClass; =20 @@ -177,7 +174,7 @@ struct CPUClass { const struct SysemuCPUOps *sysemu_ops; =20 /* when TCG is not available, this pointer is NULL */ - const struct TCGCPUOps *tcg_ops; + const TCGCPUOps *tcg_ops; =20 /* * if not NULL, this is called in order for the CPUClass to initialize diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 5abdbc3874..d7c703b4ae 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -131,6 +131,7 @@ typedef struct Range Range; typedef struct ReservedRegion ReservedRegion; typedef struct SHPCDevice SHPCDevice; typedef struct SSIBus SSIBus; +typedef struct TCGCPUOps TCGCPUOps; typedef struct TCGHelperInfo TCGHelperInfo; typedef struct TranslationBlock TranslationBlock; typedef struct VirtIODevice VirtIODevice; diff --git a/bsd-user/signal.c b/bsd-user/signal.c index ca31470772..f4352e4530 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -1022,7 +1022,7 @@ void process_pending_signals(CPUArchState *env) void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, MMUAccessType access_type, bool maperr, uintptr= _t ra) { - const struct TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; =20 if (tcg_ops->record_sigsegv) { tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); @@ -1038,7 +1038,7 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulon= g addr, void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, MMUAccessType access_type, uintptr_t ra) { - const struct TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; =20 if (tcg_ops->record_sigbus) { tcg_ops->record_sigbus(cpu, addr, access_type, ra); diff --git a/linux-user/signal.c b/linux-user/signal.c index c9527adfa3..d3e62ab030 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -671,7 +671,7 @@ void force_sigsegv(int oldsig) void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, MMUAccessType access_type, bool maperr, uintptr= _t ra) { - const struct TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; =20 if (tcg_ops->record_sigsegv) { tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); @@ -687,7 +687,7 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong = addr, void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, MMUAccessType access_type, uintptr_t ra) { - const struct TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; =20 if (tcg_ops->record_sigbus) { tcg_ops->record_sigbus(cpu, addr, access_type, ra); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index ce20a56270..80760be0f3 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -222,7 +222,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps alpha_tcg_ops =3D { +static const TCGCPUOps alpha_tcg_ops =3D { .initialize =3D alpha_translate_init, .restore_state_to_opc =3D alpha_restore_state_to_opc, =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0ee9a879f0..e050928598 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2456,7 +2456,7 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D { #endif =20 #ifdef CONFIG_TCG -static const struct TCGCPUOps arm_tcg_ops =3D { +static const TCGCPUOps arm_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, .debug_excp_handler =3D arm_debug_excp_handler, diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index d9e0e2a4dd..1125305115 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -1018,7 +1018,7 @@ static void pxa270c5_initfn(Object *obj) cpu->reset_sctlr =3D 0x00000078; } =20 -static const struct TCGCPUOps arm_v7m_tcg_ops =3D { +static const TCGCPUOps arm_v7m_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, .debug_excp_handler =3D arm_debug_excp_handler, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 76dbe56284..41ff121d20 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -233,7 +233,7 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps avr_tcg_ops =3D { +static const TCGCPUOps avr_tcg_ops =3D { .initialize =3D avr_cpu_tcg_init, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, .restore_state_to_opc =3D avr_restore_state_to_opc, diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 6512ef8ee2..93f26542d8 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -192,7 +192,7 @@ static const struct SysemuCPUOps cris_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps crisv10_tcg_ops =3D { +static const TCGCPUOps crisv10_tcg_ops =3D { .initialize =3D cris_initialize_crisv10_tcg, .restore_state_to_opc =3D cris_restore_state_to_opc, =20 @@ -203,7 +203,7 @@ static const struct TCGCPUOps crisv10_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 -static const struct TCGCPUOps crisv32_tcg_ops =3D { +static const TCGCPUOps crisv32_tcg_ops =3D { .initialize =3D cris_initialize_tcg, .restore_state_to_opc =3D cris_restore_state_to_opc, =20 diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index b2bbb21b59..49f05eae99 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -358,7 +358,7 @@ static void hexagon_cpu_init(Object *obj) =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps hexagon_tcg_ops =3D { +static const TCGCPUOps hexagon_tcg_ops =3D { .initialize =3D hexagon_translate_init, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, .restore_state_to_opc =3D hexagon_restore_state_to_opc, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 2cc8e43b33..2d98082306 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -225,7 +225,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps hppa_tcg_ops =3D { +static const TCGCPUOps hppa_tcg_ops =3D { .initialize =3D hppa_translate_init, .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, .restore_state_to_opc =3D hppa_restore_state_to_opc, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index e1405b7be9..8e148e9bc4 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -106,7 +106,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps x86_tcg_ops =3D { +static const TCGCPUOps x86_tcg_ops =3D { .initialize =3D tcg_x86_init, .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, .restore_state_to_opc =3D x86_restore_state_to_opc, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ea4281e177..d9ddab5b9a 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -758,7 +758,7 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, in= t flags) #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 -static struct TCGCPUOps loongarch_tcg_ops =3D { +static TCGCPUOps loongarch_tcg_ops =3D { .initialize =3D loongarch_translate_init, .synchronize_from_tb =3D loongarch_cpu_synchronize_from_tb, .restore_state_to_opc =3D loongarch_restore_state_to_opc, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index f9dc447897..288140c986 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -546,7 +546,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps m68k_tcg_ops =3D { +static const TCGCPUOps m68k_tcg_ops =3D { .initialize =3D m68k_tcg_init, .restore_state_to_opc =3D m68k_restore_state_to_opc, =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4c270e941f..171937564d 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -410,7 +410,7 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps mb_tcg_ops =3D { +static const TCGCPUOps mb_tcg_ops =3D { .initialize =3D mb_tcg_init, .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, .restore_state_to_opc =3D mb_restore_state_to_opc, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 4c3e1ec2d9..dfe82f93ef 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -563,7 +563,7 @@ static const struct SysemuCPUOps mips_sysemu_ops =3D { * NB: cannot be const, as some elements are changed for specific * mips hardware (see hw/mips/jazz.c). */ -static const struct TCGCPUOps mips_tcg_ops =3D { +static const TCGCPUOps mips_tcg_ops =3D { .initialize =3D mips_tcg_init, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, .restore_state_to_opc =3D mips_restore_state_to_opc, diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 3e42889ce6..bff35f835a 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -372,7 +372,7 @@ static const struct SysemuCPUOps nios2_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps nios2_tcg_ops =3D { +static const TCGCPUOps nios2_tcg_ops =3D { .initialize =3D nios2_tcg_init, .restore_state_to_opc =3D nios2_restore_state_to_opc, =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index fda0dc9470..bc54e7ccd0 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -235,7 +235,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps openrisc_tcg_ops =3D { +static const TCGCPUOps openrisc_tcg_ops =3D { .initialize =3D openrisc_translate_init, .synchronize_from_tb =3D openrisc_cpu_synchronize_from_tb, .restore_state_to_opc =3D openrisc_restore_state_to_opc, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 344196a8ce..23eb5522b6 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7332,7 +7332,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps ppc_tcg_ops =3D { +static const TCGCPUOps ppc_tcg_ops =3D { .initialize =3D ppc_translate_init, .restore_state_to_opc =3D ppc_restore_state_to_opc, =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 994ca1cdf9..b7da92783b 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -129,7 +129,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, env->bins =3D data[1]; } =20 -static const struct TCGCPUOps riscv_tcg_ops =3D { +static const TCGCPUOps riscv_tcg_ops =3D { .initialize =3D riscv_translate_init, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, .restore_state_to_opc =3D riscv_restore_state_to_opc, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index de1cc7a5e6..cfc97d06e7 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -192,7 +192,7 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps rx_tcg_ops =3D { +static const TCGCPUOps rx_tcg_ops =3D { .initialize =3D rx_translate_init, .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, .restore_state_to_opc =3D rx_restore_state_to_opc, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index db1590472e..b783e1e2e6 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -372,7 +372,7 @@ static void s390_cpu_reset_full(DeviceState *dev) #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps s390_tcg_ops =3D { +static const TCGCPUOps s390_tcg_ops =3D { .initialize =3D s390x_translate_init, .restore_state_to_opc =3D s390x_restore_state_to_opc, =20 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index eb7eb6f30a..89a42e0e22 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -265,7 +265,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps superh_tcg_ops =3D { +static const TCGCPUOps superh_tcg_ops =3D { .initialize =3D sh4_translate_init, .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, .restore_state_to_opc =3D superh_restore_state_to_opc, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 99d57cc209..8385c8a2b0 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -935,7 +935,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops =3D { #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps sparc_tcg_ops =3D { +static const TCGCPUOps sparc_tcg_ops =3D { .initialize =3D sparc_tcg_init, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, .restore_state_to_opc =3D sparc_restore_state_to_opc, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index dff88184c9..2f07fdbfab 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -190,7 +190,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops =3D= { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps tricore_tcg_ops =3D { +static const TCGCPUOps tricore_tcg_ops =3D { .initialize =3D tricore_tcg_init, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, .restore_state_to_opc =3D tricore_restore_state_to_opc, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index dfe0ff5c98..0da5409742 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -294,7 +294,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops =3D { =20 #include "hw/core/tcg-cpu-ops.h" =20 -static const struct TCGCPUOps xtensa_tcg_ops =3D { +static const TCGCPUOps xtensa_tcg_ops =3D { .initialize =3D xtensa_translate_init, .debug_excp_handler =3D xtensa_breakpoint_handler, .restore_state_to_opc =3D xtensa_restore_state_to_opc, --=20 2.34.1 From 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417080711100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/loongarch/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index d9ddab5b9a..d663d46b00 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -758,7 +758,7 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, in= t flags) #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 -static TCGCPUOps loongarch_tcg_ops =3D { +static const TCGCPUOps loongarch_tcg_ops =3D { .initialize =3D loongarch_translate_init, .synchronize_from_tb =3D loongarch_cpu_synchronize_from_tb, .restore_state_to_opc =3D loongarch_restore_state_to_opc, --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706417008; x=1707021808; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7BY3FC/8lb12NjJs4/taRcBSMiYCFRNyNU57iKW6Ebg=; b=Rk6V89NaQ9icL4rT9U76dtMW8t78gfF1qsPfCwP0SI2mx149Vokv0vdlUMJyngv2ZP HR+5NM1T9Dq4IR1hiAy5hoOSoATMb2N/6o46CNoprAXX/LhXfKnnuDgGD1/LKh8RUKHF IsAWXVMU1CEYzUtjX8eiSawfjz8v8DIqbzVlu6y6ceboxq1DXvDgqZeaWSk7Hkzudbe+ Br2DUnbFKC/ilUTxARFboTzDq5OfgDVz/NCrR4XFsALJ/Cv3lcbY7kPuD3iKq0CSxVfi GQoV94mVpvzzhXSmqXFvJ/MLI4YCJeXLnY+BH6iefZ4D4JIP9mrnanepTLRAhxvu6t88 WWvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706417008; x=1707021808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7BY3FC/8lb12NjJs4/taRcBSMiYCFRNyNU57iKW6Ebg=; b=BRhhEFjUoVwCcGJDK6WzM2k5Sk4tCYZWDvB/bUNHGbwjpOV6MO7cJtt7BZJIuHbch/ jJGzqBe59M9joxg3dZA7Wv77q+S94/Cr0faljzn1TqS3LIF2V+Uwrmer570ei5G9Ckhm CrG3wGbOrtGw070jVCYF2x9YtUQFF9Gp8MRpBT7Cxm00GO/wJ9kA/w/UOZ5wGhI1DhNk vmR1qXrW+jdgasK7qA7u9+5GWevRywSdBrUvrqy/r86RzNL6yADS3huR9aI+9vWyMWPA h18N9mecZ55N9PnEzbJEBlmHi/x60Yp5/3xOwZh7YmIl2opWRl4cn3EDaIR97m2c2m7v pprg== X-Gm-Message-State: AOJu0YyMitMW8EOKSQVCJWIFzHWIqlHBD5PrYg8VhQ/D6UgcJ0aY2WkK DRorKbC3gEmVxKUir7BJyHBs5zBrCmO0sYIu6D7pyO95ijOYWWT/m875NkLgKXdlC+KmwaCllfs BSYGc1g== X-Google-Smtp-Source: AGHT+IGrjlQTyhetVRWQ90PNwW1LSwCCbMh/5RdlgfUu+qIrCHZzD/UABKgq02AZUOzlil8hD9wFgw== X-Received: by 2002:ac8:5953:0:b0:42a:7a08:73b9 with SMTP id 19-20020ac85953000000b0042a7a0873b9mr3248532qtz.103.1706417007875; Sat, 27 Jan 2024 20:43:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 28/33] accel/tcg: Use CPUState.cc instead of CPU_GET_CLASS in cpu-exec.c Date: Sun, 28 Jan 2024 14:42:08 +1000 Message-Id: <20240128044213.316480-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417038684100001 Content-Type: text/plain; charset="utf-8" CPU_GET_CLASS does runtime type checking; use the cached copy of the class instead. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 109 ++++++++++++++++++++++--------------------- 1 file changed, 56 insertions(+), 53 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f2535a2991..3aebf46849 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -343,9 +343,9 @@ static bool check_for_breakpoints_slow(CPUState *cpu, v= addr pc, #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - CPUClass *cc =3D CPU_GET_CLASS(cpu); - assert(cc->tcg_ops->debug_check_breakpoint); - match_bp =3D cc->tcg_ops->debug_check_breakpoint(cpu); + const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; + assert(tcg_ops->debug_check_breakpoint); + match_bp =3D tcg_ops->debug_check_breakpoint(cpu); #endif } =20 @@ -462,10 +462,11 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int= *tb_exit) * counter hit zero); we must restore the guest PC to the address * of the start of the TB. */ - CPUClass *cc =3D CPU_GET_CLASS(cpu); + CPUClass *cc =3D cpu->cc; + const TCGCPUOps *tcg_ops =3D cc->tcg_ops; =20 - if (cc->tcg_ops->synchronize_from_tb) { - cc->tcg_ops->synchronize_from_tb(cpu, last_tb); + if (tcg_ops->synchronize_from_tb) { + tcg_ops->synchronize_from_tb(cpu, last_tb); } else { tcg_debug_assert(!(tb_cflags(last_tb) & CF_PCREL)); assert(cc->set_pc); @@ -497,19 +498,19 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int= *tb_exit) =20 static void cpu_exec_enter(CPUState *cpu) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); + const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; =20 - if (cc->tcg_ops->cpu_exec_enter) { - cc->tcg_ops->cpu_exec_enter(cpu); + if (tcg_ops->cpu_exec_enter) { + tcg_ops->cpu_exec_enter(cpu); } } =20 static void cpu_exec_exit(CPUState *cpu) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); + const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; =20 - if (cc->tcg_ops->cpu_exec_exit) { - cc->tcg_ops->cpu_exec_exit(cpu); + if (tcg_ops->cpu_exec_exit) { + tcg_ops->cpu_exec_exit(cpu); } } =20 @@ -685,7 +686,7 @@ static inline bool cpu_handle_halt(CPUState *cpu) =20 static inline void cpu_handle_debug_exception(CPUState *cpu) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); + const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; CPUWatchpoint *wp; =20 if (!cpu->watchpoint_hit) { @@ -694,8 +695,8 @@ static inline void cpu_handle_debug_exception(CPUState = *cpu) } } =20 - if (cc->tcg_ops->debug_excp_handler) { - cc->tcg_ops->debug_excp_handler(cpu); + if (tcg_ops->debug_excp_handler) { + tcg_ops->debug_excp_handler(cpu); } } =20 @@ -712,6 +713,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) #endif return false; } + if (cpu->exception_index >=3D EXCP_INTERRUPT) { /* exit request from the cpu execution loop */ *ret =3D cpu->exception_index; @@ -720,43 +722,45 @@ static inline bool cpu_handle_exception(CPUState *cpu= , int *ret) } cpu->exception_index =3D -1; return true; - } else { -#if defined(CONFIG_USER_ONLY) - /* if user mode only, we simulate a fake exception - which will be handled outside the cpu execution - loop */ -#if defined(TARGET_I386) - CPUClass *cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops->fake_user_interrupt(cpu); -#endif /* TARGET_I386 */ - *ret =3D cpu->exception_index; - cpu->exception_index =3D -1; - return true; -#else - if (replay_exception()) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); - bql_lock(); - cc->tcg_ops->do_interrupt(cpu); - bql_unlock(); - cpu->exception_index =3D -1; + } =20 - if (unlikely(cpu->singlestep_enabled)) { - /* - * After processing the exception, ensure an EXCP_DEBUG is - * raised when single-stepping so that GDB doesn't miss the - * next instruction. - */ - *ret =3D EXCP_DEBUG; - cpu_handle_debug_exception(cpu); - return true; - } - } else if (!replay_has_interrupt()) { - /* give a chance to iothread in replay mode */ - *ret =3D EXCP_INTERRUPT; +#if defined(CONFIG_USER_ONLY) + /* + * If user mode only, we simulate a fake exception which will be + * handled outside the cpu execution loop. + */ +#if defined(TARGET_I386) + const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; + tcg_ops->fake_user_interrupt(cpu); +#endif /* TARGET_I386 */ + *ret =3D cpu->exception_index; + cpu->exception_index =3D -1; + return true; +#else + if (replay_exception()) { + const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; + + bql_lock(); + tcg_ops->do_interrupt(cpu); + bql_unlock(); + cpu->exception_index =3D -1; + + if (unlikely(cpu->singlestep_enabled)) { + /* + * After processing the exception, ensure an EXCP_DEBUG is + * raised when single-stepping so that GDB doesn't miss the + * next instruction. + */ + *ret =3D EXCP_DEBUG; + cpu_handle_debug_exception(cpu); return true; } -#endif + } else if (!replay_has_interrupt()) { + /* give a chance to iothread in replay mode */ + *ret =3D EXCP_INTERRUPT; + return true; } +#endif =20 return false; } @@ -856,10 +860,10 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, True when it is, and we should restart on a new TB, and via longjmp via cpu_loop_exit. */ else { - CPUClass *cc =3D CPU_GET_CLASS(cpu); + const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; =20 - if (cc->tcg_ops->cpu_exec_interrupt && - cc->tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { + if (tcg_ops->cpu_exec_interrupt && + tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { if (need_replay_interrupt(interrupt_request)) { replay_interrupt(); } @@ -1078,10 +1082,9 @@ int cpu_exec(CPUState *cpu) bool tcg_exec_realizefn(CPUState *cpu, Error **errp) { static bool tcg_target_initialized; - CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 if (!tcg_target_initialized) { - cc->tcg_ops->initialize(); + cpu->cc->tcg_ops->initialize(); tcg_target_initialized =3D true; } =20 --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417100; cv=none; d=zohomail.com; s=zohoarc; b=S+Eq8I2CjhIjXsCxlnOtHC+Gh5fmQehnHLtiMbHtTaiwJz4fQagxjg+ae593LzV2qHpQyWzuf8gQg2ksHwOYiBpboZtbPcgqctEIsa5Tb1TUYkiu9aDNWomxa+89wcHy9H+wOLt+D1ZQH51zV0LZZ8hI//Iy2zuaMVOZftPrdL0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706417011; x=1707021811; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qg3ZIcWG7UYKvaB8+csAeQhagpxbl+IqGiAj8oTWzCY=; b=StlyHfKMb0LHjd4ZewQe1QsID+2+iuXKlqSeFEdQnS3VgA5Xcnmo0Ol84wvZJQieVU /rjYBqmO2LtTNGaB/g/F3VO5RM86BKl0gIcYVe7hLZhHloybqLyZs6rRpFHvSjZWQ2rN ShfuE1rhSIYGyQGGE8TM8Aje67I70nuoT7/E7/OfqTOuhs94AjtpDf11znZe4kfXLYo1 8B0ew09pDzfc9JdRoCDqoVCw73QrJrfm3MhPDK0zyWqVrfLN0rKi6Y0IJ44dcu8Yto1f ZpYG+39osUPCb7pZvFEsZj0ADmYO1pm715JzB26hz7MQHeR9MemaSwWswy4shTUJq4ap sGYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706417011; x=1707021811; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qg3ZIcWG7UYKvaB8+csAeQhagpxbl+IqGiAj8oTWzCY=; b=D5hRY4HSmg0jE2+JchcC4v9A44TK2eBz7EM2j6SKlnN//967Ac9L0o+z6P0+ciGq0A 522fc5BCcKZeYVGd9ckMMyFKT/uqslNRebTF4ejcBIpHBPYt01IUEN9a6QfaH4gENjYF kjfvTRQgfehkpEeBA3HIaJuLrfjYHErOUtgeaBN/+JMpcciFAlCDVj29Zcau0YmHAO5B 6mLStscW25SKE0yyP5Yr7X3HyJay8TeOFp76n/5oA+QqtY64GhwgSPKCr/eXqhNP49qC ttHhn5zY4f9OC5/Gvm2ruTg3i5v0xnY4lCd5E1ct/kwLGFGn8ryVy/U1Wjt86ZTvibrO qSpg== X-Gm-Message-State: AOJu0YxmVj/+r/yAUD2/C/8XKIOZRpkhKA80bUOutDs/074YelYSf5Wx IbbrYkE3cqtkpa1khRznZXwct/Zl2EiAl6+85bKWUtNQSh4xtfPmMhul0UPX9Kz4y82pMRrKuzG cXr04BA== X-Google-Smtp-Source: AGHT+IHytXqW2/yfFlmP56TDc9ZuGQJGqJl06KeRkEMjv+HymexrcpKzJRPs4wOUYj6o2YToe3TozA== X-Received: by 2002:a05:6358:2910:b0:176:abf:3777 with SMTP id y16-20020a056358291000b001760abf3777mr3576077rwb.28.1706417010678; Sat, 27 Jan 2024 20:43:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson , Pavel Dovgalyuk Subject: [PATCH 29/33] accel/tcg: Introduce TCGCPUOps::need_replay_interrupt() handler Date: Sun, 28 Jan 2024 14:42:09 +1000 Message-Id: <20240128044213.316480-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c29; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417101130100001 From: Philippe Mathieu-Daud=C3=A9 In order to make accel/tcg/ target agnostic, introduce the need_replay_interrupt() handler. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Anton Johansson Reviewed-by: Pavel Dovgalyuk Message-Id: <20240124101639.30056-7-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 5 +++++ accel/tcg/cpu-exec.c | 8 +++++--- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 3ed279836f..013867b890 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -166,6 +166,11 @@ struct TCGCPUOps { */ bool (*io_recompile_replay_branch)(CPUState *cpu, const TranslationBlock *tb); + /** + * @need_replay_interrupt: Return %true if @interrupt_request + * needs to be recorded for replay purposes. + */ + bool (*need_replay_interrupt)(int interrupt_request); #endif /* !CONFIG_USER_ONLY */ #endif /* NEED_CPU_H */ =20 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 3aebf46849..34d10eb173 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -771,12 +771,14 @@ static inline bool cpu_handle_exception(CPUState *cpu= , int *ret) * "real" interrupt event later. It does not need to be recorded for * replay purposes. */ -static inline bool need_replay_interrupt(int interrupt_request) +static inline bool need_replay_interrupt(CPUState *cpu, int interrupt_requ= est) { #if defined(TARGET_I386) return !(interrupt_request & CPU_INTERRUPT_POLL); #else - return true; + const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; + return !tcg_ops->need_replay_interrupt + || tcg_ops->need_replay_interrupt(interrupt_request); #endif } #endif /* !CONFIG_USER_ONLY */ @@ -864,7 +866,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, =20 if (tcg_ops->cpu_exec_interrupt && tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { - if (need_replay_interrupt(interrupt_request)) { + if (need_replay_interrupt(cpu, interrupt_request)) { replay_interrupt(); } /* --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417126; cv=none; d=zohomail.com; s=zohoarc; b=muqgJ9yMAtx32Wzz7adY62FNNNibNtpsEG0RXuubfwX3QYL+/zlQciWRiIRAwJ96pYRoBl0MjYB2uqImlxhh5RLQiSokV722v2RulAHNlLD2g2QQ/r3QXmSvHUw3Jq9cAs7WSdfcDoRIuEk8ZLn7vdnJ1CZYKwymz06C9JInZOg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417126; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4tMFQE97q4aUbL8LMPU5R9Llk18uVwdymUNm4iTykmc=; b=eOOyAi0oIBgDZesiUWl1d15z/o0m3w+B6mvS1UPVc8zjGPj2hmgVurzw9yv5CmBwogUfHdQCXLdaoktytGyeIdPvNh5mk2XLQAmFhjD8C0JR5XhFiSRfsNVWaet8d6obuNkwr1MqxMYOqp7Kqa15GfKN9SZthBCNlEeY0WSEMds= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417126379718.3445837419748; Sat, 27 Jan 2024 20:45:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx1E-0005tZ-UX; Sat, 27 Jan 2024 23:43:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx17-0005fp-Ht for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:38 -0500 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx15-0004Pq-8P for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:36 -0500 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-5c6bd3100fcso743896a12.3 for ; Sat, 27 Jan 2024 20:43:34 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706417014; x=1707021814; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4tMFQE97q4aUbL8LMPU5R9Llk18uVwdymUNm4iTykmc=; b=WsWMU4AeaEeZF7zzGIVLcoj/nff1RQBfB53zM4UgAwgG6MHL+i0kkKxAvErUM6q9tO oOVTg6tXIudUJN6fp15d7hIVvxSYYFTs1IfNbg2baXin8ugQsPln8rRDdqJpDDtHoE9P 39W6u8KR+4F30+fUrni9HDEks47vAtVuLPstZFgV1eMlgSjWPfkGNsQZoDgPJ4JBW1+u JW0KWDL/XH5PTk8voiIGJJe5fPLT/c8NA1VsgElO+Vp45hkKMdjgeWNKJzbaaqu1eEPi byAzCgANmQ60TjEUPtFAahkscRrIPJM3+W8bypy97sXQWhcM92Lvr9Tg67dKCU1L51bY Su9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706417014; x=1707021814; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4tMFQE97q4aUbL8LMPU5R9Llk18uVwdymUNm4iTykmc=; b=ceTD9EucLUlCYLJaKo2TQu1DvJaPiAeCwH8T8wnbBSUJlWdzjT4uSSCkckjnmerEeN dc4pK/jdXXrB4UCmaHpBVqxhHcXtZAgnry0d5BzlY1T1qMD0Ofm7fWZ36pdIpILyPWaX vy/qbrc8Ku/K4PHsJtXoS7cqiqqAiJ8Zn+KPRf2iugh5adllAnzV2QIQSys4Fj3Viyxd 6MZjs4EgJkCjrcw0FLL+BrvEKFzn0SxMpQydDRHCm327t+M0ZfZ22/5CkLEK+MD5y9zL IIYp6tZP6+C2kXakqHeBtVFFI55ORfoXRmi4D0KDEBfKy/PdKUqmiHWSBGRT8bNKHNqm MJJg== X-Gm-Message-State: AOJu0Yxe6CMvvqGGuuRwkmFUgG6qKMp2NClG37fQCxf/Xs4rsCztuJBK H7UbfZhsDBFL81f/okf4KpKwo/QLGfwYvo4agjdfXDzFa0fVqlGYGMm6+PGGf81yQPmP05erzzJ I7B08lg== X-Google-Smtp-Source: AGHT+IEvo4AB7scWrx8GSV37cdjKgTdZh2c1HhwaSrEVzZcN8z7QW/OxUkIzvWkH3xGP2tIZdifkCg== X-Received: by 2002:a17:90a:4593:b0:295:2a35:13b8 with SMTP id v19-20020a17090a459300b002952a3513b8mr464876pjg.0.1706417013764; Sat, 27 Jan 2024 20:43:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson , Pavel Dovgalyuk Subject: [PATCH 30/33] target/i386: Extract x86_need_replay_interrupt() from accel/tcg/ Date: Sun, 28 Jan 2024 14:42:10 +1000 Message-Id: <20240128044213.316480-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417126901100001 From: Philippe Mathieu-Daud=C3=A9 Move this x86-specific code out of the generic accel/tcg/. Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pavel Dovgalyuk Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20240124101639.30056-8-philmd@linaro.org> Signed-off-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 1 + accel/tcg/cpu-exec.c | 4 ---- target/i386/tcg/sysemu/seg_helper.c | 10 ++++++++++ target/i386/tcg/tcg-cpu.c | 1 + 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index ce34b737bb..253b1f561e 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -39,6 +39,7 @@ QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_S= PACE_BITS); */ void x86_cpu_do_interrupt(CPUState *cpu); #ifndef CONFIG_USER_ONLY +bool x86_need_replay_interrupt(int interrupt_request); bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); #endif =20 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 34d10eb173..2eacd694ea 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -773,13 +773,9 @@ static inline bool cpu_handle_exception(CPUState *cpu,= int *ret) */ static inline bool need_replay_interrupt(CPUState *cpu, int interrupt_requ= est) { -#if defined(TARGET_I386) - return !(interrupt_request & CPU_INTERRUPT_POLL); -#else const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; return !tcg_ops->need_replay_interrupt || tcg_ops->need_replay_interrupt(interrupt_request); -#endif } #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/i386/tcg/sysemu/seg_helper.c b/target/i386/tcg/sysemu/s= eg_helper.c index 1cb5a0db45..e6f42282bb 100644 --- a/target/i386/tcg/sysemu/seg_helper.c +++ b/target/i386/tcg/sysemu/seg_helper.c @@ -127,6 +127,16 @@ void x86_cpu_do_interrupt(CPUState *cs) } } =20 +bool x86_need_replay_interrupt(int interrupt_request) +{ + /* + * CPU_INTERRUPT_POLL is a virtual event which gets converted into a + * "real" interrupt event later. It does not need to be recorded for + * replay purposes. + */ + return !(interrupt_request & CPU_INTERRUPT_POLL); +} + bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu =3D X86_CPU(cs); diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 8e148e9bc4..5bdcf45199 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -123,6 +123,7 @@ static const TCGCPUOps x86_tcg_ops =3D { .do_unaligned_access =3D x86_cpu_do_unaligned_access, .debug_excp_handler =3D breakpoint_handler, .debug_check_breakpoint =3D x86_debug_check_breakpoint, + .need_replay_interrupt =3D x86_need_replay_interrupt, #endif /* !CONFIG_USER_ONLY */ }; =20 --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417243; cv=none; d=zohomail.com; s=zohoarc; b=Ne6y1/GfZ/gOM+E60OZWUMvc0zcgRoINyyY/JwWm8xNV9f0BPUDurucKKOkd3kQF3rsYwMFGOzLCgbeQmm9FYKT+wyrSxXoFZXhAfAErHNelIT0AhmwcVyn3cqcnx3i2gPfzRcXcKECBnWXfNsblLIFEV0ixOUY8SlQCI5Gresk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417243; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=2hwCZNX7r6WcP/DB6F59Yv2bYfXzcZik2wXoCrV2EBg=; b=ZDxigLdZ2y89CQ0hy1dlFG3Ebsugc81UKqmhzbJPfjaA0gyF3AdM583gAAxcMHTZHR8xIEaQx5cXGubacFNO7fUkajkgKVeE3rSOWGzg96r5UOFqvHwkbmhnjkzqOFsFEeQ2L0EodmWqVsm5sfrSVTMQrFB9kAaMLKpH8uLNi6o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417243454281.6846517680733; Sat, 27 Jan 2024 20:47:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx1M-0006G0-77; Sat, 27 Jan 2024 23:43:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx19-0005nk-DN for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:41 -0500 Received: from mail-oo1-xc33.google.com ([2607:f8b0:4864:20::c33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx17-0004Qq-8Q for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:39 -0500 Received: by mail-oo1-xc33.google.com with SMTP id 006d021491bc7-5957ede4deaso1180498eaf.1 for ; Sat, 27 Jan 2024 20:43:36 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706417016; x=1707021816; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2hwCZNX7r6WcP/DB6F59Yv2bYfXzcZik2wXoCrV2EBg=; b=ygmUA1MPOgZvcj7ShkZRqbtk+9pD/mRZOryQzNEM7C2sBf2QlrQh8I8pamh5pWXMoo vuJ9HC3SP8etWsKPvPjxZ945ieB//y3k3y72Y8DtxYF2hYMU1sHM/Jg3xOGsN9kpzE+C 0p8Hgj3zUqTxyrsP/WCBxL9PQcrxzyiMAQkMm3mOzKUMLathDxlf57+iwvd7QdVAdzha j2gsYJe4eq71zXVoVX9BLylsA403KBaWq98ql36hUSb7NtFkvS9CXQ9y4EGDgeibpavL VDPM7iIKvcbQPL76CGjX4VybqsOui6DWdJEZB1r8c9H+xMvD2Clk2DBKR2ztqt9BzJMG oKhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706417016; x=1707021816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2hwCZNX7r6WcP/DB6F59Yv2bYfXzcZik2wXoCrV2EBg=; b=JcDxzh6mQOaMeQieuIVI73KqGniN36IxvxdfbWBLj2NeyUZ/0jfrs+NvJuvbRwfwcR AtDUe34iypB8CW9/caqmOyNCVHawcBDlJ9QTjgNcJkJ1+oWiTi+qNR/bqWyZmAMeelvr yPAPxxIj6dgbI5cOzHaA7yx69zuaAYSTX3Opy8vIHP8GtUDE92kZbp8iSGt0pOCG++et Ff5uYJJvcQitrruFW4aH40Hj1p2W5eycFm/Mq1z/APe9pt2DUKyCP7W3lu2ZibsBFRro GcZ8qb2W2u3vQcmMyMbFMNP8BS0XMq97ecy018AgY/g6JdZ1C49SuVKrh0JSGVfdIDdq sBLw== X-Gm-Message-State: AOJu0Yx6Lf9DGIXmE0XIAL0oPvqaLIC0uouI/sogZdA5SOMH4Lq1GMku aSwUKLTzHz/VTHtOnds+h79+3jxthQQSGyNFnY8q9S2xSjzW6dw58QN3vboELdFy/Nae231Vcqz vlV9LVQ== X-Google-Smtp-Source: AGHT+IF2Jhs9mUI8/9R/u+kbEOba5QAX5NNEr/vODx0Z4cNsu0PqqO1+Z6c2I5eNm7yuiK9V0Bv7sw== X-Received: by 2002:a05:6358:52c7:b0:174:f48c:3871 with SMTP id z7-20020a05635852c700b00174f48c3871mr3059615rwz.43.1706417015729; Sat, 27 Jan 2024 20:43:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 31/33] accel/tcg: Inline need_replay_interrupt Date: Sun, 28 Jan 2024 14:42:11 +1000 Message-Id: <20240128044213.316480-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c33; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417245112100003 Content-Type: text/plain; charset="utf-8" The function is now trivial, and with inlining we can re-use the calling function's tcg_ops variable. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2eacd694ea..75f7ba7bed 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -765,20 +765,6 @@ static inline bool cpu_handle_exception(CPUState *cpu,= int *ret) return false; } =20 -#ifndef CONFIG_USER_ONLY -/* - * CPU_INTERRUPT_POLL is a virtual event which gets converted into a - * "real" interrupt event later. It does not need to be recorded for - * replay purposes. - */ -static inline bool need_replay_interrupt(CPUState *cpu, int interrupt_requ= est) -{ - const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; - return !tcg_ops->need_replay_interrupt - || tcg_ops->need_replay_interrupt(interrupt_request); -} -#endif /* !CONFIG_USER_ONLY */ - static inline bool icount_exit_request(CPUState *cpu) { if (!icount_enabled()) { @@ -862,7 +848,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, =20 if (tcg_ops->cpu_exec_interrupt && tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { - if (need_replay_interrupt(cpu, interrupt_request)) { + if (!tcg_ops->need_replay_interrupt || + tcg_ops->need_replay_interrupt(interrupt_request)) { replay_interrupt(); } /* --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417227; cv=none; d=zohomail.com; s=zohoarc; b=fYPy8DmRwbUl3O/QDhlboFOV9+NunT2po5oieS7c8kK5tQGcc7fYTevxaPNPPFaF0YEx9kc3e0qZn/nSUI5KB9USSe6xONnDGetYQkwyAYm6jttF5j2+WkIjGtp7XjDWWdl46TXjhX5UBj3ZPYElcf/YwZoJSatsu9T4it6x/XY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417227; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LMqE9xBix0QLmyhH8Xqft/09pdbioiePfeACz0Kfp3o=; b=foFXV0s+p96PWzd3+la7kOtJcKevjyD9EFR0tru5vDUvIv8SS7FP5FSFZEpP5l39gC0ZGm/3yiqEcafy6Z4hZix1tMNbhHYxqGX4cF0kR+Jwrwcy5pjK/60/i7ZT0nGZ5UnQ+Kp3Ju6gC8OisOjOmnTTAEwIiKZdP8BHSSwWBx8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417227034477.6419937471612; Sat, 27 Jan 2024 20:47:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx1M-0006Hm-Eb; Sat, 27 Jan 2024 23:43:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx1C-0005qS-3o for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:42 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx1A-0004RA-GL for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:41 -0500 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-29065efa06fso1553948a91.1 for ; Sat, 27 Jan 2024 20:43:39 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706417018; x=1707021818; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LMqE9xBix0QLmyhH8Xqft/09pdbioiePfeACz0Kfp3o=; b=yWyFvs5GLPW9XgHMsmDwAVGUO25QwbfifYhUo0UrG+4jTdK/Xp26ERHYL4Ywsig+63 CtK6V/N8P88Mjr2hHibPWBaEJr9k88sP67bnemrYmN0kGpc9mZ96bGqZ1pA3lmkDE5O3 mJkd1LKpS+8qoDTWCzxjKd/26mvUltaOU3yfp6lw82Y19H/99M4kpyOT81FwDqsnb9pv s3wk6gxoe+2aMjEKv0x7RrhTkNMwQ0b1PHVZGeqNPPQMrILnqjlsnLQRkYXpZ33kTSxD EepXEQiK0opgXFkTFnsrobAkajcR70EF2fdKK9fsQb8KM4Ghy4EZepYpJZuZgFKxSckR mR9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706417018; x=1707021818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LMqE9xBix0QLmyhH8Xqft/09pdbioiePfeACz0Kfp3o=; b=e61Cc6Sc65T0rvWijzouoisXMqQ1Ov+SxRgfCaU2Dw/3wXQsGOinnj/MUK2TIRU6+H M5fg3Q/Kua5eq4+Z3cFyJ8vY/UKBliryjyHQmeg0GC4Zg2tMeufEy/jcN1GopHPj4yrb J19ySOS93UqUEoX0tfHMKnDIiBrxaF0zaUvdzeXhlDvGm5+gfzVMYYl7l7gKnBhVDbLL irFXFinUeUpAghJv24otlPGP02/BLdtzozQZwseheciQ7LzWGbIHQAGNmy1kgr9sxbyn zIMr1UBBJKm91Vv2BxopS6hIi9ONIDLWnmpeNT475xrqVExbtXAOhVfzNzK5GAAHtCXA W6oQ== X-Gm-Message-State: AOJu0YxtKVcnieCdgeTfwpyUd0caL8x582Yd4J9AhJQtkfdl8L3QXvkl wIWapxKirohhGBSliHIQv+d6hPChsPybDTXZSj6AMjV17Kh5VCd2SlV1du+faAzM0Wz/ZCjGhV+ iT7eaWA== X-Google-Smtp-Source: AGHT+IEoTkgNygjlQX+xOaKcSFVmDunG/JqWg05qSiM3srH71iwE99c7dgHabEs9hukxMbJAfWZGTg== X-Received: by 2002:a17:90b:88c:b0:28c:ea35:44f8 with SMTP id bj12-20020a17090b088c00b0028cea3544f8mr1631535pjb.79.1706417018287; Sat, 27 Jan 2024 20:43:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson Subject: [PATCH 32/33] accel/tcg: Introduce TCGCPUOps::cpu_exec_halt() handler Date: Sun, 28 Jan 2024 14:42:12 +1000 Message-Id: <20240128044213.316480-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417229029100007 From: Philippe Mathieu-Daud=C3=A9 In order to make accel/tcg/ target agnostic, introduce the cpu_exec_halt() handler. Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20240124101639.30056-9-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 2 ++ accel/tcg/cpu-exec.c | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 013867b890..bf8ff8e3ee 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -112,6 +112,8 @@ struct TCGCPUOps { void (*do_interrupt)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** @cpu_exec_halt: Callback for handling halt in cpu_exec */ + void (*cpu_exec_halt)(CPUState *cpu); /** * @tlb_fill: Handle a softmmu tlb miss * diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 75f7ba7bed..82627b12b8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -664,6 +664,8 @@ static inline bool cpu_handle_halt(CPUState *cpu) { #ifndef CONFIG_USER_ONLY if (cpu->halted) { + const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; + #if defined(TARGET_I386) if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { X86CPU *x86_cpu =3D X86_CPU(cpu); @@ -673,6 +675,9 @@ static inline bool cpu_handle_halt(CPUState *cpu) bql_unlock(); } #endif /* TARGET_I386 */ + if (tcg_ops->cpu_exec_halt) { + tcg_ops->cpu_exec_halt(cpu); + } if (!cpu_has_work(cpu)) { return true; } --=20 2.34.1 From nobody Tue Nov 26 14:19:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706417165; cv=none; d=zohomail.com; s=zohoarc; b=YxxNIu0rYR094J5DEJlHL2jRCvCAysjC7TIusTWHF6SkvoX0wuMCDw8Fku5T17p+Fle6e/wmG9N/X0+pzYaaAs3o9b2M3Bi9AJXicZP5tcRNA7GWa5iZeB6mOcIvCrHWHouHTED3DFRbL4uTCc1s8BbKiqDdDK0ThfzMDMHRm2M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706417165; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=T/uaC3GU2r5ag1NYLRtG0R3ws3tDO6FtLPMPWrHI/7I=; b=Uelvq7YYrhzg45TD8F4B5C9gnc+dH7c2eQeDcpOMlC0TdT6oHY+mHsIiRb/j7bPneJnef8t94+vIE/K6fbH55P0dKWmwg4Nv11Lq9P3CNS5i32dT3ej8uTnmCiCOTZ2X1IpJo3MAHTKJEtaNivqJ3dDaqJFKpe8/uixLZmz8VD4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706417165564416.5845626346555; Sat, 27 Jan 2024 20:46:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTx1L-0006AX-IR; Sat, 27 Jan 2024 23:43:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTx1D-0005tV-OY for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:44 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTx1C-0004Rz-29 for qemu-devel@nongnu.org; Sat, 27 Jan 2024 23:43:43 -0500 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-290a55f3feaso1323687a91.2 for ; Sat, 27 Jan 2024 20:43:41 -0800 (PST) Received: from stoup.. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706417021; x=1707021821; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T/uaC3GU2r5ag1NYLRtG0R3ws3tDO6FtLPMPWrHI/7I=; b=CNxCRIliyLjf9CoTLwX8GO3Z5MEGmw2wP9TOXBqMoZJvkvuPG5BrD8DqkFD7tj6wxV crEeyLOqppnVh25HGOyRofwxwjLWS29OLgmVaSjmPzfG4m70ell9QEmSr0FJt1576bh2 V4FQQbKSDEhh1TdLetpbtDXeuDVIwl4q+kO2lghBxV3SAT+YicVhF1Mq5ue82jD7K6ff VR28ARbIlVdycaIN4QXEcRarhYyCR/z7DlnXma6eUyIZ/r5EGnNjqEGVppmY5zA+WdTF SBocA01VF4oZBWZ6PJLOEPR6JJl+PgUtmHasFcMX73+ciECgRJQMkSXtK1a5vLK4oVUD 9iTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706417021; x=1707021821; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T/uaC3GU2r5ag1NYLRtG0R3ws3tDO6FtLPMPWrHI/7I=; b=DVHTb3EIOCqVmqVT9yq109Khg4TNpWt/xplFd7gmJFbSbf72KoMHmkAUAob2IiiTrz pi+Lgz99pKlVrYr6iRML3AZ64o9tZiqDkcaSqx8YDcWhgQoBVoKV2+jC490UoaCUYPme yKms9X4p79rC4Bzl1WWCcuvl3A4Agn9EnNkCaY9JBUadkzddMsJJj1IjQWtuqPqrHts1 WWl+KsQbRPG1ECyV/YB93FpXoyjelwXwa2s/kTKxTYW9mcxAkhGxO3N2x1uzC6bojeSM B5NotKpWujgkNFg0ILcqrgoWtWZkU+XGOcF9oJRKIDcLQiijxYAWvfhB7EYP0iaas/lA B82g== X-Gm-Message-State: AOJu0Yyw11y5BrnlFoOy0dAJFLDG0X4TvH0HCNYDs4vYAg6/gqZseAfw hVJWI72ZFbANgFjIa55+ZRuDNAVdo0+gH2BmGm05dghLGopgGxzrvVux9qll+2b8iB5bpa7qR0V H483uLA== X-Google-Smtp-Source: AGHT+IH6+V9twuxV00uYp9p82Ezc0zV35qoKn2bXtI0imI19KZLlgZmXOaMB0zBw8WMknq4OZWR3Kg== X-Received: by 2002:a17:902:ec85:b0:1d7:79c5:8f5a with SMTP id x5-20020a170902ec8500b001d779c58f5amr3414450plg.134.1706417020940; Sat, 27 Jan 2024 20:43:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson Subject: [PATCH 33/33] target/i386: Extract x86_cpu_exec_halt() from accel/tcg/ Date: Sun, 28 Jan 2024 14:42:13 +1000 Message-Id: <20240128044213.316480-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706417166862100003 From: Philippe Mathieu-Daud=C3=A9 Move this x86-specific code out of the generic accel/tcg/. Reported-by: Anton Johansson Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20240124101639.30056-10-philmd@linaro.org> Signed-off-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 1 + accel/tcg/cpu-exec.c | 12 ------------ target/i386/tcg/sysemu/seg_helper.c | 13 +++++++++++++ target/i386/tcg/tcg-cpu.c | 1 + 4 files changed, 15 insertions(+), 12 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 253b1f561e..effc2c1c98 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -39,6 +39,7 @@ QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_S= PACE_BITS); */ void x86_cpu_do_interrupt(CPUState *cpu); #ifndef CONFIG_USER_ONLY +void x86_cpu_exec_halt(CPUState *cpu); bool x86_need_replay_interrupt(int interrupt_request); bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); #endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 82627b12b8..977576ca14 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -30,9 +30,6 @@ #include "qemu/rcu.h" #include "exec/log.h" #include "qemu/main-loop.h" -#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) -#include "hw/i386/apic.h" -#endif #include "sysemu/cpus.h" #include "exec/cpu-all.h" #include "sysemu/cpu-timers.h" @@ -666,15 +663,6 @@ static inline bool cpu_handle_halt(CPUState *cpu) if (cpu->halted) { const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; =20 -#if defined(TARGET_I386) - if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - bql_lock(); - apic_poll_irq(x86_cpu->apic_state); - cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); - bql_unlock(); - } -#endif /* TARGET_I386 */ if (tcg_ops->cpu_exec_halt) { tcg_ops->cpu_exec_halt(cpu); } diff --git a/target/i386/tcg/sysemu/seg_helper.c b/target/i386/tcg/sysemu/s= eg_helper.c index e6f42282bb..2db8083748 100644 --- a/target/i386/tcg/sysemu/seg_helper.c +++ b/target/i386/tcg/sysemu/seg_helper.c @@ -20,6 +20,7 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" @@ -127,6 +128,18 @@ void x86_cpu_do_interrupt(CPUState *cs) } } =20 +void x86_cpu_exec_halt(CPUState *cpu) +{ + if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { + X86CPU *x86_cpu =3D X86_CPU(cpu); + + bql_lock(); + apic_poll_irq(x86_cpu->apic_state); + cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); + bql_unlock(); + } +} + bool x86_need_replay_interrupt(int interrupt_request) { /* diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 5bdcf45199..cca19cd40e 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -119,6 +119,7 @@ static const TCGCPUOps x86_tcg_ops =3D { #else .tlb_fill =3D x86_cpu_tlb_fill, .do_interrupt =3D x86_cpu_do_interrupt, + .cpu_exec_halt =3D x86_cpu_exec_halt, .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, .do_unaligned_access =3D x86_cpu_do_unaligned_access, .debug_excp_handler =3D breakpoint_handler, --=20 2.34.1