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Iglesias" Subject: [PATCH v2 07/23] target/cris: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Fri, 26 Jan 2024 23:03:49 +0100 Message-ID: <20240126220407.95022-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240126220407.95022-1-philmd@linaro.org> References: <20240126220407.95022-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=philmd@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706306852730100003 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/cris/cpu.c | 5 +---- target/cris/gdbstub.c | 9 +++------ target/cris/helper.c | 12 ++++-------- target/cris/translate.c | 3 +-- 4 files changed, 9 insertions(+), 20 deletions(-) diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 9ba08e8b0c..8ec32fade8 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -142,10 +142,7 @@ static void cris_cpu_set_irq(void *opaque, int irq, in= t level) =20 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) { - CRISCPU *cc =3D CRIS_CPU(cpu); - CPUCRISState *env =3D &cc->env; - - if (env->pregs[PR_VR] !=3D 32) { + if (cpu_env(cpu)->pregs[PR_VR] !=3D 32) { info->mach =3D bfd_mach_cris_v0_v10; info->print_insn =3D print_insn_crisv10; } else { diff --git a/target/cris/gdbstub.c b/target/cris/gdbstub.c index 25c0ca33a5..9e87069da8 100644 --- a/target/cris/gdbstub.c +++ b/target/cris/gdbstub.c @@ -23,8 +23,7 @@ =20 int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); =20 if (n < 15) { return gdb_get_reg32(mem_buf, env->regs[n]); @@ -55,8 +54,7 @@ int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArra= y *mem_buf, int n) =20 int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); uint8_t srs; =20 srs =3D env->pregs[PR_SRS]; @@ -90,8 +88,7 @@ int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *= mem_buf, int n) =20 int cris_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); uint32_t tmp; =20 if (n > 49) { diff --git a/target/cris/helper.c b/target/cris/helper.c index c0bf987e3e..1c3f86876f 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -53,8 +53,7 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); struct cris_mmu_result res; int prot, miss; target_ulong phy; @@ -97,8 +96,7 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, =20 void crisv10_cpu_do_interrupt(CPUState *cs) { - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); int ex_vec =3D -1; =20 D_LOG("exception index=3D%d interrupt_req=3D%d\n", @@ -159,8 +157,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) =20 void cris_cpu_do_interrupt(CPUState *cs) { - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); int ex_vec =3D -1; =20 D_LOG("exception index=3D%d interrupt_req=3D%d\n", @@ -262,8 +259,7 @@ hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); bool ret =3D false; =20 if (interrupt_request & CPU_INTERRUPT_HARD diff --git a/target/cris/translate.c b/target/cris/translate.c index b3974ba0bb..a935167f00 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3180,8 +3180,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int *max_insns, =20 void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; + CPUCRISState *env =3D cpu_env(cs); const char * const *regnames; const char * const *pregnames; int i; --=20 2.41.0