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Fri, 26 Jan 2024 14:04:46 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Thomas Huth , qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Eduardo Habkost , kvm@vger.kernel.org, qemu-ppc@nongnu.org, Richard Henderson , Vladimir Sementsov-Ogievskiy , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Michael Rolnik Subject: [PATCH v2 06/23] target/avr: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Fri, 26 Jan 2024 23:03:48 +0100 Message-ID: <20240126220407.95022-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240126220407.95022-1-philmd@linaro.org> References: <20240126220407.95022-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=philmd@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706306758545100003 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/avr/cpu.c | 27 +++++++-------------------- target/avr/gdbstub.c | 6 ++---- target/avr/helper.c | 10 +++------- 3 files changed, 12 insertions(+), 31 deletions(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index f5cbdc4a8c..2ad24373a8 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -43,31 +43,22 @@ static vaddr avr_cpu_get_pc(CPUState *cs) =20 static bool avr_cpu_has_work(CPUState *cs) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; - return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RE= SET)) - && cpu_interrupts_enabled(env); + && cpu_interrupts_enabled(cpu_env(cs)); } =20 static void avr_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - env->pc_w =3D tb->pc / 2; /* internally PC points to words */ + cpu_env(cs)->pc_w =3D tb->pc / 2; /* internally PC points to words */ } =20 static void avr_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; - - env->pc_w =3D data[0]; + cpu_env(cs)->pc_w =3D data[0]; } =20 static void avr_cpu_reset_hold(Object *obj) @@ -165,8 +156,7 @@ static ObjectClass *avr_cpu_class_by_name(const char *c= pu_model) =20 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(cs); int i; =20 qemu_fprintf(f, "\n"); @@ -276,8 +266,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) */ static void avr_avr5_initfn(Object *obj) { - AVRCPU *cpu =3D AVR_CPU(obj); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(CPU(obj)); =20 set_avr_feature(env, AVR_FEATURE_LPM); set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); @@ -305,8 +294,7 @@ static void avr_avr5_initfn(Object *obj) */ static void avr_avr51_initfn(Object *obj) { - AVRCPU *cpu =3D AVR_CPU(obj); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(CPU(obj)); =20 set_avr_feature(env, AVR_FEATURE_LPM); set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); @@ -335,8 +323,7 @@ static void avr_avr51_initfn(Object *obj) */ static void avr_avr6_initfn(Object *obj) { - AVRCPU *cpu =3D AVR_CPU(obj); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(CPU(obj)); =20 set_avr_feature(env, AVR_FEATURE_LPM); set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); diff --git a/target/avr/gdbstub.c b/target/avr/gdbstub.c index 150344d8b9..2eeee2bf4e 100644 --- a/target/avr/gdbstub.c +++ b/target/avr/gdbstub.c @@ -23,8 +23,7 @@ =20 int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(cs); =20 /* R */ if (n < 32) { @@ -53,8 +52,7 @@ int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *m= em_buf, int n) =20 int avr_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(cs); =20 /* R */ if (n < 32) { diff --git a/target/avr/helper.c b/target/avr/helper.c index fdc9884ea0..eeca415c43 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -30,8 +30,7 @@ =20 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(cs); =20 /* * We cannot separate a skip from the next instruction, @@ -69,8 +68,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_r= equest) =20 void avr_cpu_do_interrupt(CPUState *cs) { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; + CPUAVRState *env =3D cpu_env(cs); =20 uint32_t ret =3D env->pc_w; int vector =3D 0; @@ -144,9 +142,7 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, if (probe) { page_size =3D 1; } else { - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; - env->fullacc =3D 1; + cpu_env(cs)->fullacc =3D 1; cpu_loop_exit_restore(cs, retaddr); } } --=20 2.41.0