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Fri, 26 Jan 2024 14:04:28 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Thomas Huth , qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Eduardo Habkost , kvm@vger.kernel.org, qemu-ppc@nongnu.org, Richard Henderson , Vladimir Sementsov-Ogievskiy , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , Reinoud Zandijk , Sunil Muthuswamy , Song Gao , Yoshinori Sato Subject: [PATCH v2 03/23] bulk: Call in place single use cpu_env() Date: Fri, 26 Jan 2024 23:03:45 +0100 Message-ID: <20240126220407.95022-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240126220407.95022-1-philmd@linaro.org> References: <20240126220407.95022-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philmd@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706306774600100006 Avoid CPUArchState local variable when cpu_env() is used once. Mechanical patch using the following Coccinelle spatch script: @@ type CPUArchState; identifier env; expression cs; @@ { - CPUArchState *env =3D cpu_env(cs); ... when !=3D env - env + cpu_env(cs) ... when !=3D env } Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec.c | 3 +-- linux-user/i386/cpu_loop.c | 4 ++-- target/hppa/mem_helper.c | 3 +-- target/hppa/translate.c | 3 +-- target/i386/nvmm/nvmm-all.c | 6 ++---- target/i386/whpx/whpx-all.c | 18 ++++++------------ target/loongarch/tcg/translate.c | 3 +-- target/rx/translate.c | 3 +-- target/sh4/op_helper.c | 4 +--- 9 files changed, 16 insertions(+), 31 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 67eda9865e..86206484f8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -445,7 +445,6 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) static inline TranslationBlock * QEMU_DISABLE_CFI cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) { - CPUArchState *env =3D cpu_env(cpu); uintptr_t ret; TranslationBlock *last_tb; const void *tb_ptr =3D itb->tc.ptr; @@ -455,7 +454,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *= tb_exit) } =20 qemu_thread_jit_execute(); - ret =3D tcg_qemu_tb_exec(env, tb_ptr); + ret =3D tcg_qemu_tb_exec(cpu_env(cpu), tb_ptr); cpu->neg.can_do_io =3D true; qemu_plugin_disable_mem_helpers(cpu); /* diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index 42ecb4bf0a..92beb6830c 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -323,8 +323,8 @@ void cpu_loop(CPUX86State *env) =20 static void target_cpu_free(void *obj) { - CPUArchState *env =3D cpu_env(obj); - target_munmap(env->gdt.base, sizeof(uint64_t) * TARGET_GDT_ENTRIES); + target_munmap(cpu_env(obj)->gdt.base, + sizeof(uint64_t) * TARGET_GDT_ENTRIES); g_free(obj); } =20 diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 4fcc612754..bb85962d50 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -518,7 +518,6 @@ void HELPER(iitlbt_pa20)(CPUHPPAState *env, target_ulon= g r1, target_ulong r2) /* Purge (Insn/Data) TLB. */ static void ptlb_work(CPUState *cpu, run_on_cpu_data data) { - CPUHPPAState *env =3D cpu_env(cpu); vaddr start =3D data.target_ptr; vaddr end; =20 @@ -532,7 +531,7 @@ static void ptlb_work(CPUState *cpu, run_on_cpu_data da= ta) end =3D (vaddr)TARGET_PAGE_SIZE << (2 * end); end =3D start + end - 1; =20 - hppa_flush_tlb_range(env, start, end); + hppa_flush_tlb_range(cpu_env(cpu), start, end); } =20 /* This is local to the current cpu. */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3ef39b1bd7..5735335254 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3805,8 +3805,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gat= e *a) =20 #ifndef CONFIG_USER_ONLY if (ctx->tb_flags & PSW_C) { - CPUHPPAState *env =3D cpu_env(ctx->cs); - int type =3D hppa_artype_for_page(env, ctx->base.pc_next); + int type =3D hppa_artype_for_page(cpu_env(ctx->cs), ctx->base.pc_n= ext); /* If we could not find a TLB entry, then we need to generate an ITLB miss exception so the kernel will provide it. The resulting TLB fill operation will invalidate this TB and diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index cfdca91123..49a3a3b916 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -340,7 +340,6 @@ nvmm_get_registers(CPUState *cpu) static bool nvmm_can_take_int(CPUState *cpu) { - CPUX86State *env =3D cpu_env(cpu); AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_machine *mach =3D get_nvmm_mach(); @@ -349,7 +348,7 @@ nvmm_can_take_int(CPUState *cpu) return false; } =20 - if (qcpu->int_shadow || !(env->eflags & IF_MASK)) { + if (qcpu->int_shadow || !(cpu_env(cpu)->eflags & IF_MASK)) { struct nvmm_x64_state *state =3D vcpu->state; =20 /* Exit on interrupt window. */ @@ -645,13 +644,12 @@ static int nvmm_handle_halted(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - CPUX86State *env =3D cpu_env(cpu); int ret =3D 0; =20 bql_lock(); =20 if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && - (env->eflags & IF_MASK)) && + (cpu_env(cpu)->eflags & IF_MASK)) && !(cpu->interrupt_request & CPU_INTERRUPT_NMI)) { cpu->exception_index =3D EXCP_HLT; cpu->halted =3D true; diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index a7262654ac..31eec7048c 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -300,7 +300,6 @@ static SegmentCache whpx_seg_h2q(const WHV_X64_SEGMENT_= REGISTER *hs) /* X64 Extended Control Registers */ static void whpx_set_xcrs(CPUState *cpu) { - CPUX86State *env =3D cpu_env(cpu); HRESULT hr; struct whpx_state *whpx =3D &whpx_global; WHV_REGISTER_VALUE xcr0; @@ -311,7 +310,7 @@ static void whpx_set_xcrs(CPUState *cpu) } =20 /* Only xcr0 is supported by the hypervisor currently */ - xcr0.Reg64 =3D env->xcr0; + xcr0.Reg64 =3D cpu_env(cpu)->xcr0; hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters( whpx->partition, cpu->cpu_index, &xcr0_name, 1, &xcr0); if (FAILED(hr)) { @@ -321,7 +320,6 @@ static void whpx_set_xcrs(CPUState *cpu) =20 static int whpx_set_tsc(CPUState *cpu) { - CPUX86State *env =3D cpu_env(cpu); WHV_REGISTER_NAME tsc_reg =3D WHvX64RegisterTsc; WHV_REGISTER_VALUE tsc_val; HRESULT hr; @@ -345,7 +343,7 @@ static int whpx_set_tsc(CPUState *cpu) } } =20 - tsc_val.Reg64 =3D env->tsc; + tsc_val.Reg64 =3D cpu_env(cpu)->tsc; hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters( whpx->partition, cpu->cpu_index, &tsc_reg, 1, &tsc_val); if (FAILED(hr)) { @@ -556,7 +554,6 @@ static void whpx_set_registers(CPUState *cpu, int level) =20 static int whpx_get_tsc(CPUState *cpu) { - CPUX86State *env =3D cpu_env(cpu); WHV_REGISTER_NAME tsc_reg =3D WHvX64RegisterTsc; WHV_REGISTER_VALUE tsc_val; HRESULT hr; @@ -569,14 +566,13 @@ static int whpx_get_tsc(CPUState *cpu) return -1; } =20 - env->tsc =3D tsc_val.Reg64; + cpu_env(cpu)->tsc =3D tsc_val.Reg64; return 0; } =20 /* X64 Extended Control Registers */ static void whpx_get_xcrs(CPUState *cpu) { - CPUX86State *env =3D cpu_env(cpu); HRESULT hr; struct whpx_state *whpx =3D &whpx_global; WHV_REGISTER_VALUE xcr0; @@ -594,7 +590,7 @@ static void whpx_get_xcrs(CPUState *cpu) return; } =20 - env->xcr0 =3D xcr0.Reg64; + cpu_env(cpu)->xcr0 =3D xcr0.Reg64; } =20 static void whpx_get_registers(CPUState *cpu) @@ -1400,8 +1396,7 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exi= t_context_valid) { if (cpu->vcpu_dirty) { /* The CPU registers have been modified by other parts of QEMU. */ - CPUArchState *env =3D cpu_env(cpu); - return env->eip; + return cpu_env(cpu)->eip; } else if (exit_context_valid) { /* * The CPU registers have not been modified by neither other parts @@ -1439,12 +1434,11 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool e= xit_context_valid) =20 static int whpx_handle_halt(CPUState *cpu) { - CPUX86State *env =3D cpu_env(cpu); int ret =3D 0; =20 bql_lock(); if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && - (env->eflags & IF_MASK)) && + (cpu_env(cpu)->eflags & IF_MASK)) && !(cpu->interrupt_request & CPU_INTERRUPT_NMI)) { cpu->exception_index =3D EXCP_HLT; cpu->halted =3D true; diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/transl= ate.c index 21f4db6fbd..7bb8cecab3 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -282,10 +282,9 @@ static uint64_t make_address_pc(DisasContext *ctx, uin= t64_t addr) =20 static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState= *cs) { - CPULoongArchState *env =3D cpu_env(cs); DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - ctx->opcode =3D translator_ldl(env, &ctx->base, ctx->base.pc_next); + ctx->opcode =3D translator_ldl(cpu_env(cs), &ctx->base, ctx->base.pc_n= ext); =20 if (!decode(ctx, ctx->opcode)) { qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. " diff --git a/target/rx/translate.c b/target/rx/translate.c index c6ce717a95..1829a0b1cd 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2195,9 +2195,8 @@ static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) =20 static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *c= s) { - CPURXState *env =3D cpu_env(cs); DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - ctx->env =3D env; + ctx->env =3D cpu_env(cs); ctx->tb_flags =3D ctx->base.tb->flags; } =20 diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 54d390fe1f..4559d0d376 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -29,9 +29,7 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - CPUSH4State *env =3D cpu_env(cs); - - env->tea =3D addr; + cpu_env(cs)->tea =3D addr; switch (access_type) { case MMU_INST_FETCH: case MMU_DATA_LOAD: --=20 2.41.0