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Fri, 26 Jan 2024 14:06:27 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Thomas Huth , qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Eduardo Habkost , kvm@vger.kernel.org, qemu-ppc@nongnu.org, Richard Henderson , Vladimir Sementsov-Ogievskiy , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Max Filippov Subject: [PATCH v2 22/23] target/xtensa: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Fri, 26 Jan 2024 23:04:04 +0100 Message-ID: <20240126220407.95022-23-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240126220407.95022-1-philmd@linaro.org> References: <20240126220407.95022-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706307081261100004 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/xtensa/dbg_helper.c | 3 +-- target/xtensa/exc_helper.c | 3 +-- target/xtensa/gdbstub.c | 6 ++---- target/xtensa/helper.c | 9 +++------ target/xtensa/translate.c | 3 +-- 5 files changed, 8 insertions(+), 16 deletions(-) diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index 497dafca71..5546c82ecd 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -66,8 +66,7 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i,= uint32_t v) =20 bool xtensa_debug_check_breakpoint(CPUState *cs) { - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); unsigned int i; =20 if (xtensa_get_cintlevel(env) >=3D env->config->debug_level) { diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index 168419a505..0514c2c1f3 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -205,8 +205,7 @@ static void handle_interrupt(CPUXtensaState *env) /* Called from cpu_handle_interrupt with BQL held */ void xtensa_cpu_do_interrupt(CPUState *cs) { - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); =20 if (cs->exception_index =3D=3D EXC_IRQ) { qemu_log_mask(CPU_LOG_INT, diff --git a/target/xtensa/gdbstub.c b/target/xtensa/gdbstub.c index 4b3bfb7e59..4748fb6532 100644 --- a/target/xtensa/gdbstub.c +++ b/target/xtensa/gdbstub.c @@ -65,8 +65,7 @@ void xtensa_count_regs(const XtensaConfig *config, =20 int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); const XtensaGdbReg *reg =3D env->config->gdb_regmap.reg + n; #ifdef CONFIG_USER_ONLY int num_regs =3D env->config->gdb_regmap.num_core_regs; @@ -120,8 +119,7 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArr= ay *mem_buf, int n) =20 int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); uint32_t tmp; const XtensaGdbReg *reg =3D env->config->gdb_regmap.reg + n; #ifdef CONFIG_USER_ONLY diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index a9f8907083..ca214b948a 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -217,8 +217,7 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *en= v) =20 void xtensa_breakpoint_handler(CPUState *cs) { - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); =20 if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { @@ -266,8 +265,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); uint32_t paddr; uint32_t page_size; unsigned access; @@ -297,8 +295,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t reta= ddr) { - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); =20 cpu_restore_state(cs, retaddr); HELPER(exception_cause_vaddr)(env, env->pc, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 87947236ca..426dcb6169 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1248,8 +1248,7 @@ void gen_intermediate_code(CPUState *cpu, Translation= Block *tb, int *max_insns, =20 void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; + CPUXtensaState *env =3D cpu_env(cs); xtensa_isa isa =3D env->config->isa; int i, j; =20 --=20 2.41.0