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Fri, 26 Jan 2024 14:05:54 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Thomas Huth , qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Eduardo Habkost , kvm@vger.kernel.org, qemu-ppc@nongnu.org, Richard Henderson , Vladimir Sementsov-Ogievskiy , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH v2 17/23] target/riscv: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Fri, 26 Jan 2024 23:03:59 +0100 Message-ID: <20240126220407.95022-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240126220407.95022-1-philmd@linaro.org> References: <20240126220407.95022-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706306941015100003 Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/riscv/arch_dump.c | 6 ++---- target/riscv/cpu.c | 17 +++++------------ target/riscv/cpu_helper.c | 14 ++++---------- target/riscv/debug.c | 9 +++------ target/riscv/gdbstub.c | 6 ++---- target/riscv/kvm/kvm-cpu.c | 6 ++---- target/riscv/tcg/tcg-cpu.c | 9 +++------ target/riscv/translate.c | 3 +-- 8 files changed, 22 insertions(+), 48 deletions(-) diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c index 434c8a3dbb..994709647f 100644 --- a/target/riscv/arch_dump.c +++ b/target/riscv/arch_dump.c @@ -68,8 +68,7 @@ int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, C= PUState *cs, int cpuid, DumpState *s) { struct riscv64_note note; - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); int ret, i =3D 0; const char name[] =3D "CORE"; =20 @@ -137,8 +136,7 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f,= CPUState *cs, int cpuid, DumpState *s) { struct riscv32_note note; - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); int ret, i; const char name[] =3D "CORE"; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8cbfc7e781..fe21393655 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -419,8 +419,7 @@ static void riscv_any_cpu_init(Object *obj) =20 static void riscv_max_cpu_init(Object *obj) { - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(CPU(obj)); RISCVMXL mlx =3D MXL_RV64; =20 #ifdef TARGET_RISCV32 @@ -828,8 +827,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) =20 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); =20 if (env->xl =3D=3D MXL_RV32) { env->pc =3D (int32_t)value; @@ -840,8 +838,7 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value) =20 static vaddr riscv_cpu_get_pc(CPUState *cs) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); =20 /* Match cpu_get_tb_cpu_state. */ if (env->xl =3D=3D MXL_RV32) { @@ -853,8 +850,7 @@ static vaddr riscv_cpu_get_pc(CPUState *cs) static bool riscv_cpu_has_work(CPUState *cs) { #ifndef CONFIG_USER_ONLY - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); /* * Definition of the WFI instruction requires it to ignore the privile= ge * mode and delegation registers, but respect individual enables @@ -1642,10 +1638,7 @@ static void rva22s64_profile_cpu_init(Object *obj) =20 static const gchar *riscv_gdb_arch_name(CPUState *cs) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - - switch (riscv_cpu_mxl(env)) { + switch (riscv_cpu_mxl(cpu_env(cs))) { case MXL_RV32: return "riscv:rv32"; case MXL_RV64: diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c7cc7eb423..9d4798b841 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -493,9 +493,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *e= nv) bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - int interruptno =3D riscv_cpu_local_irq_pending(env); + int interruptno =3D riscv_cpu_local_irq_pending(cpu_env(cs)); if (interruptno >=3D 0) { cs->exception_index =3D RISCV_EXCP_INT_FLAG | interruptno; riscv_cpu_do_interrupt(cs); @@ -1223,8 +1221,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hw= addr physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retad= dr) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); =20 if (access_type =3D=3D MMU_DATA_STORE) { cs->exception_index =3D RISCV_EXCP_STORE_AMO_ACCESS_FAULT; @@ -1244,8 +1241,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); switch (access_type) { case MMU_INST_FETCH: cs->exception_index =3D RISCV_EXCP_INST_ADDR_MIS; @@ -1631,9 +1627,7 @@ static target_ulong riscv_transformed_insn(CPURISCVSt= ate *env, void riscv_cpu_do_interrupt(CPUState *cs) { #if !defined(CONFIG_USER_ONLY) - - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); bool write_gva =3D false; uint64_t s; =20 diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 4945d1a1f2..c8df9812be 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -757,8 +757,7 @@ target_ulong tinfo_csr_read(CPURISCVState *env) =20 void riscv_cpu_debug_excp_handler(CPUState *cs) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); =20 if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { @@ -773,8 +772,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) =20 bool riscv_cpu_debug_check_breakpoint(CPUState *cs) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); CPUBreakpoint *bp; target_ulong ctrl; target_ulong pc; @@ -832,8 +830,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) =20 bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); target_ulong ctrl; target_ulong addr; int trigger_type; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 58b3ace0fe..999d815b34 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -49,8 +49,7 @@ static const struct TypeSize vec_lanes[] =3D { =20 int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); target_ulong tmp; =20 if (n < 32) { @@ -75,8 +74,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) =20 int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); int length =3D 0; target_ulong tmp; =20 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 680a729cd8..cf0cae813b 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -171,8 +171,7 @@ static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visit= or *v, { KVMCPUConfig *misa_ext_cfg =3D opaque; target_ulong misa_bit =3D misa_ext_cfg->offset; - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(CPU(obj)); bool value =3D env->misa_ext_mask & misa_bit; =20 visit_type_bool(v, name, &value, errp); @@ -184,8 +183,7 @@ static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visit= or *v, { KVMCPUConfig *misa_ext_cfg =3D opaque; target_ulong misa_bit =3D misa_ext_cfg->offset; - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(CPU(obj)); bool value, host_bit; =20 if (!visit_type_bool(v, name, &value, errp)) { diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 994ca1cdf9..c7c4d9ac92 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -92,8 +92,7 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { if (!(tb_cflags(tb) & CF_PCREL)) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); =20 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); @@ -110,8 +109,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); target_ulong pc; =20 @@ -1030,8 +1028,7 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor= *v, const char *name, { const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; target_ulong misa_bit =3D misa_ext_cfg->misa_bit; - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(CPU(obj)); bool value; =20 value =3D env->misa_ext & misa_bit; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 071fbad7ef..e94fb107e0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1265,8 +1265,7 @@ static void riscv_tr_disas_log(const DisasContextBase= *dcbase, CPUState *cpu, FILE *logfile) { #ifndef CONFIG_USER_ONLY - RISCVCPU *rvcpu =3D RISCV_CPU(cpu); - CPURISCVState *env =3D &rvcpu->env; + CPURISCVState *env =3D cpu_env(cpu); #endif =20 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); --=20 2.41.0