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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706279623; x=1706884423; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=zP/lYKNH4Nfu30L6dAxijOyJutxvSbBpVMIqdo7k2Lk=; b=MtSdYjv0YRMbg/lqAnQ0kgiyHcQG1633SNqoMzaxxNbqfbO0bRVB694tZ2GmlDB3Za JsYjgAmdpr/CoYTX/wGVei6JG4M9GxDkW/1EyT2K6POKT5+xjSh5vbRA0txDYHcW2I64 asH24uO/bCw95eG4dx2noITXt8eNDunk0HBxxw+qj6Dib5rzyLE7/0yhVfERGIMxogxI w2e8JIpdxo534AofEGYkb2GbXwMVJzDqQ85Ze5YlG9BkZKVYL10mZg93IHeGS6pOTUlF Vcso7l/+nO0suBYroeN4lu3k4+SqxHm+9IomCEf2MB1kFLa+sf11c7EnUbnMH8on2VS/ I/PA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706279623; x=1706884423; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zP/lYKNH4Nfu30L6dAxijOyJutxvSbBpVMIqdo7k2Lk=; b=sVzrBdrMWURDgd1ay9R7SWCiAgL5Qwl+DquFfpVCCBMERG1qbgUGk1ls4p+0nqSpMN JfPtHhvQxnhM/MVF932x3Q97ORZ5SFupVf6ZAitu9a8mnWwYNnR640ym1UdFOozkVMJA 5wF0QeoNjIJiuy2Y8JDFEWVwGwYvkVbZlMXCwMzOQclsSIOviEfQOGKOePwVO5W8OHWV o1ZSYv5CrOSyj7VlaQ60GEJE/3UaCmmxo1XVA/fTjopkfVP8GXy3s8A6xWSNqoutxqcU 7zsYpIRiRRbiJI6U3Z0/RorbewtH8bphlsmRHygn9SPne31Ot3yDBEr4xaaQAg/m2mAN +kJA== X-Gm-Message-State: AOJu0YxPmlfxw35ceFqnFqbcGl4t890PEjr8eLo/nOZoI7PoJpzMlqNH TZSNPfGZq7ztiUwdM4C1MHhzl06PKwKtgtU5kiOO5wnu45/fQD/fJfAlc2LB36W3H/Jyw5v4dkx 2 X-Google-Smtp-Source: AGHT+IFTxB9KxuSb/3KhnTp6lA0Kc+/qfeKdIS95NSRlIDuRfp5nUksU6beol6ljAHM11MONk7EpUg== X-Received: by 2002:adf:fd07:0:b0:339:431b:90f4 with SMTP id e7-20020adffd07000000b00339431b90f4mr1125247wrr.100.1706279622995; Fri, 26 Jan 2024 06:33:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/36] target/xtensa: fix OOB TLB entry access Date: Fri, 26 Jan 2024 14:33:06 +0000 Message-Id: <20240126143341.2101237-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706279660725100003 Content-Type: text/plain; charset="utf-8" From: Max Filippov r[id]tlb[01], [iw][id]tlb opcodes use TLB way index passed in a register by the guest. The host uses 3 bits of the index for ITLB indexing and 4 bits for DTLB, but there's only 7 entries in the ITLB array and 10 in the DTLB array, so a malicious guest may trigger out-of-bound access to these arrays. Change split_tlb_entry_spec return type to bool to indicate whether TLB way passed to it is valid. Change get_tlb_entry to return NULL in case invalid TLB way is requested. Add assertion to xtensa_tlb_get_entry that requested TLB way and entry indices are valid. Add checks to the [rwi]tlb helpers that requested TLB way is valid and return 0 or do nothing when it's not. Cc: qemu-stable@nongnu.org Fixes: b67ea0cd7441 ("target-xtensa: implement memory protection options") Signed-off-by: Max Filippov Reviewed-by: Peter Maydell Message-id: 20231215120307.545381-1-jcmvbkbc@gmail.com Signed-off-by: Peter Maydell --- target/xtensa/mmu_helper.c | 47 ++++++++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 12 deletions(-) diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 12552a33470..2fda4e887cc 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -224,22 +224,31 @@ static void split_tlb_entry_spec_way(const CPUXtensaS= tate *env, uint32_t v, * Split TLB address into TLB way, entry index and VPN (with index). * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format */ -static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtl= b, - uint32_t *vpn, uint32_t *wi, uint32_t *ei) +static bool split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtl= b, + uint32_t *vpn, uint32_t *wi, uint32_t *ei) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { *wi =3D v & (dtlb ? 0xf : 0x7); - split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); + if (*wi < (dtlb ? env->config->dtlb.nways : env->config->itlb.nway= s)) { + split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); + return true; + } else { + return false; + } } else { *vpn =3D v & REGION_PAGE_MASK; *wi =3D 0; *ei =3D (v >> 29) & 0x7; + return true; } } =20 static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dt= lb, unsigned wi, unsigned ei) { + const xtensa_tlb *tlb =3D dtlb ? &env->config->dtlb : &env->config->it= lb; + + assert(wi < tlb->nways && ei < tlb->way_size[wi]); return dtlb ? env->dtlb[wi] + ei : env->itlb[wi] + ei; @@ -252,11 +261,14 @@ static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState= *env, uint32_t wi; uint32_t ei; =20 - split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); - if (pwi) { - *pwi =3D wi; + if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { + if (pwi) { + *pwi =3D wi; + } + return xtensa_tlb_get_entry(env, dtlb, wi, ei); + } else { + return NULL; } - return xtensa_tlb_get_entry(env, dtlb, wi, ei); } =20 static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, @@ -482,7 +494,12 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v= , uint32_t dtlb) if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { uint32_t wi; const xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, &wi); - return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; + + if (entry) { + return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->a= sid; + } else { + return 0; + } } else { return v & REGION_PAGE_MASK; } @@ -491,7 +508,12 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v= , uint32_t dtlb) uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) { const xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, NULL); - return entry->paddr | entry->attr; + + if (entry) { + return entry->paddr | entry->attr; + } else { + return 0; + } } =20 void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) @@ -499,7 +521,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint= 32_t dtlb) if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { uint32_t wi; xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, &wi); - if (entry->variable && entry->asid) { + if (entry && entry->variable && entry->asid) { tlb_flush_page(env_cpu(env), entry->vaddr); entry->asid =3D 0; } @@ -537,8 +559,9 @@ void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint= 32_t v, uint32_t dtlb) uint32_t vpn; uint32_t wi; uint32_t ei; - split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); - xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); + if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { + xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); + } } =20 /*! --=20 2.34.1