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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706279630; x=1706884430; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WClEbAYEMyFm8PZOzcgu+oaG2+JFImSPU42hTK0ft1A=; b=J8ACLJhTqUyC6BSIeavmxU63mbOZ4aVM4fEa6rI6oj3O5W8BsfvPdfDomJBw1OGbgd pmMn5lRyYCdM87DO8Qo6nMnMmFnMOOlpNog8Z3qhBWo6BWg3yq+19xwugnbA7iJAKuVQ hFtEuWmIy5/+SZ/40sBqD4YAtbu/Y626nEXF7UQeTChAxHm2Sjn77OMI5XcQnVTDovZ3 NahNhjLOySEE8JjzfYqNFPUF0SJltQtOuAuHOIJZXOz/lkYNlxyfMMr4PK5ZVo3SG0ei JErfceYCQd5xY3+m6ls2eDQsLyt6OfPEkCchBzGOg4fGNrKZfM5FZLe0zGjJT2j7mjt4 npDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706279630; x=1706884430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WClEbAYEMyFm8PZOzcgu+oaG2+JFImSPU42hTK0ft1A=; b=u9R+w/R9l7kQZquNmuyqGGjh3BPfkhTggsUu+S6bTxn1RHq3IIW3R2sXE0ueUORbWD VP1ZHR7cSQv14bsgqqY77sW06VPHS5qO4Ak3AIsgs22AwBQreae/xhEsyP1TRnIBZvKt O17P+H9D3bD6cwzjlVulDapDqCKaXf21edaLZhgGgXlag7l+KuhX7LTAGG8BJrh/lw87 XznoWmOgFn9bUhx7jZKvFxPv2KSU+1Qy/H+X/deC/QIRJcMjhW22eLL9vb8rhBEUA6LG VYhY2aZK58rLtPdq+0nNLLnUdExSxLy/P43BWN2lcaIKicc/yL7zzidERLOKsNLuGVLT NCOQ== X-Gm-Message-State: AOJu0YzZ71vBm9fjXYJKN+5wNDeG6PbhqXXlBi3WUTY8KE8EeNg9XMPC RPuGd5+GZsycjE/TvfFx/IZqaQaThwJ+rqsd7UcWVoP/6dx3Nx/ePE04LZClPg4MZAU3hcsGZcP I X-Google-Smtp-Source: AGHT+IFXYAmbA0yQ357CN2Vl743xnyR22dtdITRCAc9YmFw6WksHPVI0eHUL7Qn6BMFWRz6FnKQOpA== X-Received: by 2002:adf:f88d:0:b0:339:6114:c90e with SMTP id u13-20020adff88d000000b003396114c90emr1162100wrp.27.1706279629792; Fri, 26 Jan 2024 06:33:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/36] target/arm: Rename arm_cpu_mp_affinity Date: Fri, 26 Jan 2024 14:33:22 +0000 Message-Id: <20240126143341.2101237-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706279760718100001 From: Richard Henderson Rename to arm_build_mp_affinity. This frees up the name for other usage, and emphasizes that the cpu object is not involved. Signed-off-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-9-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- hw/arm/npcm7xx.c | 2 +- hw/arm/sbsa-ref.c | 2 +- hw/arm/virt.c | 2 +- target/arm/cpu.c | 6 +++--- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ec276fcd57c..55a19e8539e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1171,7 +1171,7 @@ void arm_cpu_post_init(Object *obj); (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) =20 -uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); +uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_arm_cpu; diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 15ff21d0472..7fb0a233b2d 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -474,7 +474,7 @@ static void npcm7xx_realize(DeviceState *dev, Error **e= rrp) /* CPUs */ for (i =3D 0; i < nc->num_cpus; i++) { object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", - arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPU= S), + arm_build_mp_affinity(i, NPCM7XX_MAX_NUM_C= PUS), &error_abort); object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", NPCM7XX_GIC_CPU_IF_ADDR, &error_abort); diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 477dca06373..b8857d1e9e4 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -148,7 +148,7 @@ static const int sbsa_ref_irqmap[] =3D { static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) { uint8_t clustersz =3D ARM_DEFAULT_CPUS_PER_CLUSTER; - return arm_cpu_mp_affinity(idx, clustersz); + return arm_build_mp_affinity(idx, clustersz); } =20 static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ed4ed9f4142..eecde04fc77 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1676,7 +1676,7 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState= *vms, int idx) clustersz =3D GICV3_TARGETLIST_BITS; } } - return arm_cpu_mp_affinity(idx, clustersz); + return arm_build_mp_affinity(idx, clustersz); } =20 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 593695b4247..5b5af7d4e1e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1307,7 +1307,7 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f,= int flags) } } =20 -uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) +uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) { uint32_t Aff1 =3D idx / clustersz; uint32_t Aff0 =3D idx % clustersz; @@ -2113,8 +2113,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * so these bits always RAZ. */ if (cpu->mp_affinity =3D=3D ARM64_AFFINITY_INVALID) { - cpu->mp_affinity =3D arm_cpu_mp_affinity(cs->cpu_index, - ARM_DEFAULT_CPUS_PER_CLUSTE= R); + cpu->mp_affinity =3D arm_build_mp_affinity(cs->cpu_index, + ARM_DEFAULT_CPUS_PER_CLUS= TER); } =20 if (cpu->reset_hivecs) { --=20 2.34.1