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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706279626; x=1706884426; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Udpnn055t0nLxzR8Pti1GosKKa+Y1FeGstBsF+O1OxU=; b=ydvtwDbDaaCGkIjSQwpDYN2+5T9grVPZB0PoTH7XxMaMEVdsAqQuTFE5aV70X94kb1 dcsJfWjyqE7fPchVAVHEYL4It6MvGT0ASNuP4y5tcCrheUdDYI5zzEYHawQVZ2AjBbom bA8SDDu7WD4fusfUPA130Aa0m9ZsGJQalT01U96K4qfm45doblR1WFDv16ElDqIOn0Z2 8kf9gsl2gzXE2XU+KBwhbNZYYhK9Mg9/o4Zp0QM2NiDVBQjvIZzzCnfineK3vqX2zEk7 hf5eoVuDTDvGrrE18Tqbl9Au26QBxfPvXFFlJWDW9JZErKlxZmW3v33jqD5DmZaj05Jo 2nPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706279626; x=1706884426; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Udpnn055t0nLxzR8Pti1GosKKa+Y1FeGstBsF+O1OxU=; b=fMhPkDo3tiYZisUnrOUBtzQGiD+Hfg6Oig9HCp4QJ+esvI5JkXaQNYwN5D4zY1nPis sSs3DdJAmX5LdILA3cMm5OzQssk/uCYy6JgH0Zy+qyoMbLYT7swrqIbrlntGKO8XJz96 Nv42AqJaEI32ehUCDKCL/oxdevnR1OEbAw+Y5fPOz+Lnu+EBE/pkmsf2p1b+6xshIw6v ws8UJxlqimvSzuZsFmmp6Jihidz9e4x5bIanbqxgoDsguO/7+5vw2mKCXWZFIfa2yeIa CpW8d9I86Jsr0v2PhTUc9BO5zTkxo5Fhb2EwzFGSkE3FlAiFQQojJhkygDgQzPOjd4vm XARQ== X-Gm-Message-State: AOJu0YxgJoYx/q6eAvth5ec79zJ6thJEA3SQgIClsQBFVEOc69m+/YtV HTrA6U2nM2rY6nJTufluGKjGbCxvH4d/uQwd0hj3HJjpAiFXD96syrkY9pH6fEAykPBad0N68/O R X-Google-Smtp-Source: AGHT+IHd8H7A+VKO0VcP2llvADpxZw7CkJSdtwA8kyZ0GyZSwSc2uNnHeMfInQY6i1KFQlYwTzFb7g== X-Received: by 2002:a5d:5302:0:b0:339:3edd:1435 with SMTP id e2-20020a5d5302000000b003393edd1435mr1085643wrv.56.1706279626461; Fri, 26 Jan 2024 06:33:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/36] hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board Date: Fri, 26 Jan 2024 14:33:14 +0000 Message-Id: <20240126143341.2101237-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706279925115100001 Content-Type: text/plain; charset="utf-8" From: Guenter Roeck Add watchdog timer support to Allwinner-H40 and Bananapi. The watchdog timer is added as an overlay to the Timer module memory map. Signed-off-by: Guenter Roeck Reviewed-by: Strahinja Jankovic Message-id: 20240115182757.1095012-4-linux@roeck-us.net Signed-off-by: Peter Maydell --- docs/system/arm/bananapi_m2u.rst | 2 +- include/hw/arm/allwinner-r40.h | 3 +++ hw/arm/allwinner-r40.c | 8 ++++++++ hw/arm/Kconfig | 1 + 4 files changed, 13 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/bananapi_m2u.rst b/docs/system/arm/bananapi_m2= u.rst index 542310591d6..587b4886553 100644 --- a/docs/system/arm/bananapi_m2u.rst +++ b/docs/system/arm/bananapi_m2u.rst @@ -25,6 +25,7 @@ The Banana Pi M2U machine supports the following devices: * SATA * TWI (I2C) * USB 2.0 + * Hardware Watchdog =20 Limitations """"""""""" @@ -33,7 +34,6 @@ Currently, Banana Pi M2U does *not* support the following= features: =20 - Graphical output via HDMI, GPU and/or the Display Engine - Audio output -- Hardware Watchdog - Real Time Clock =20 Also see the 'unimplemented' array in the Allwinner R40 SoC module diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h index c589fcc1c15..66c38e7d907 100644 --- a/include/hw/arm/allwinner-r40.h +++ b/include/hw/arm/allwinner-r40.h @@ -33,6 +33,7 @@ #include "hw/net/allwinner-sun8i-emac.h" #include "hw/usb/hcd-ohci.h" #include "hw/usb/hcd-ehci.h" +#include "hw/watchdog/allwinner-wdt.h" #include "target/arm/cpu.h" #include "sysemu/block-backend.h" =20 @@ -54,6 +55,7 @@ enum { AW_R40_DEV_OHCI2, AW_R40_DEV_CCU, AW_R40_DEV_PIT, + AW_R40_DEV_WDT, AW_R40_DEV_UART0, AW_R40_DEV_UART1, AW_R40_DEV_UART2, @@ -114,6 +116,7 @@ struct AwR40State { const hwaddr *memmap; AwSRAMCState sramc; AwA10PITState timer; + AwWdtState wdt; AllwinnerAHCIState sata; AwSdHostState mmc[AW_R40_NUM_MMCS]; EHCISysBusState ehci[AW_R40_NUM_USB]; diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c index 534be4a735d..a28e5b3886a 100644 --- a/hw/arm/allwinner-r40.c +++ b/hw/arm/allwinner-r40.c @@ -53,6 +53,7 @@ const hwaddr allwinner_r40_memmap[] =3D { [AW_R40_DEV_OHCI2] =3D 0x01c1c400, [AW_R40_DEV_CCU] =3D 0x01c20000, [AW_R40_DEV_PIT] =3D 0x01c20c00, + [AW_R40_DEV_WDT] =3D 0x01c20c90, [AW_R40_DEV_UART0] =3D 0x01c28000, [AW_R40_DEV_UART1] =3D 0x01c28400, [AW_R40_DEV_UART2] =3D 0x01c28800, @@ -279,6 +280,8 @@ static void allwinner_r40_init(Object *obj) object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), "clk1-freq"); =20 + object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I); + object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_R40_CCU); =20 for (int i =3D 0; i < AW_R40_NUM_MMCS; i++) { @@ -545,6 +548,11 @@ static void allwinner_r40_realize(DeviceState *dev, Er= ror **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0, qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_EM= AC)); =20 + /* WDT */ + sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal); + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0, + allwinner_r40_memmap[AW_R40_DEV_WDT], 1); + /* Unimplemented devices */ for (unsigned i =3D 0; i < ARRAY_SIZE(r40_unimplemented); i++) { create_unimplemented_device(r40_unimplemented[i].device_name, diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 704517edd4f..2bc3ea3425e 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -411,6 +411,7 @@ config ALLWINNER_R40 select AHCI select ALLWINNER_SRAMC select ALLWINNER_A10_PIT + select ALLWINNER_WDT select AXP2XX_PMU select SERIAL select ARM_TIMER --=20 2.34.1