From nobody Tue Nov 26 16:28:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706276049413679.7723725040695; Fri, 26 Jan 2024 05:34:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTMKC-0003z0-UV; Fri, 26 Jan 2024 08:32:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTMK4-0003AI-AF; Fri, 26 Jan 2024 08:32:44 -0500 Received: from gandalf.ozlabs.org ([150.107.74.76]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTMK1-00080i-T6; Fri, 26 Jan 2024 08:32:43 -0500 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4TLzCC3P5Tz4wdD; Sat, 27 Jan 2024 00:32:39 +1100 (AEDT) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4TLzC93H8vz4wny; Sat, 27 Jan 2024 00:32:37 +1100 (AEDT) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Richard Henderson , Gavin Shan Subject: [PULL 06/17] hw/arm/aspeed: Check for CPU types in machine_run_board_init() Date: Fri, 26 Jan 2024 14:32:05 +0100 Message-ID: <20240126133217.996306-7-clg@kaod.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240126133217.996306-1-clg@kaod.org> References: <20240126133217.996306-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=5gEp=JE=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1706276049897100004 From: Philippe Mathieu-Daud=C3=A9 Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type). Convert it to a NULL-terminated array (of a single non-NULL element). Set MachineClass::valid_cpu_types[] to use the common machine code to provide hints when the requested CPU is invalid (see commit e702cbc19e ("machine: Improve is_cpu_type_supported()"). Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 3 ++- hw/arm/aspeed.c | 1 + hw/arm/aspeed_ast10x0.c | 6 +++++- hw/arm/aspeed_ast2400.c | 12 ++++++++++-- hw/arm/aspeed_ast2600.c | 6 +++++- hw/arm/aspeed_soc_common.c | 5 ++++- 6 files changed, 27 insertions(+), 6 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index a060a5991874..0db5a41e7170 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -128,7 +128,8 @@ struct AspeedSoCClass { DeviceClass parent_class; =20 const char *name; - const char *cpu_type; + /** valid_cpu_types: NULL terminated array of a single CPU type. */ + const char * const *valid_cpu_types; uint32_t silicon_rev; uint64_t sram_size; uint64_t secsram_size; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index d2d490a6d142..fc8355cdce14 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1149,6 +1149,7 @@ static void aspeed_machine_class_init_cpus_defaults(M= achineClass *mc) mc->default_cpus =3D sc->num_cpus; mc->min_cpus =3D sc->num_cpus; mc->max_cpus =3D sc->num_cpus; + mc->valid_cpu_types =3D sc->valid_cpu_types; } =20 static void aspeed_machine_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index dca601a3f9b6..c3b5116a6a9d 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -417,13 +417,17 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) =20 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */ + NULL + }; DeviceClass *dc =3D DEVICE_CLASS(klass); AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(dc); =20 dc->realize =3D aspeed_soc_ast1030_realize; =20 sc->name =3D "ast1030-a1"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */ + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST1030_A1_SILICON_REV; sc->sram_size =3D 0xc0000; sc->secsram_size =3D 0x40000; /* 256 * KiB */ diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index 789e591f3ad0..c613e58144dd 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -502,6 +502,10 @@ static void aspeed_ast2400_soc_realize(DeviceState *de= v, Error **errp) =20 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("arm926"), + NULL + }; AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 @@ -510,7 +514,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *= oc, void *data) dc->user_creatable =3D false; =20 sc->name =3D "ast2400-a1"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("arm926"); + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2400_A1_SILICON_REV; sc->sram_size =3D 0x8000; sc->spis_num =3D 1; @@ -526,6 +530,10 @@ static void aspeed_soc_ast2400_class_init(ObjectClass = *oc, void *data) =20 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("arm1176"), + NULL + }; AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 @@ -534,7 +542,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *= oc, void *data) dc->user_creatable =3D false; =20 sc->name =3D "ast2500-a1"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("arm1176"); + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2500_A1_SILICON_REV; sc->sram_size =3D 0x9000; sc->spis_num =3D 2; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 589a4a6eea10..24541b5284d4 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -628,13 +628,17 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) =20 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a7"), + NULL + }; DeviceClass *dc =3D DEVICE_CLASS(oc); AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); =20 dc->realize =3D aspeed_soc_ast2600_realize; =20 sc->name =3D "ast2600-a3"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2600_A3_SILICON_REV; sc->sram_size =3D 0x16400; sc->spis_num =3D 2; diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index 36ca189ce960..123a0c432cfd 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -20,7 +20,10 @@ =20 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc) { - return sc->cpu_type; + assert(sc->valid_cpu_types); + assert(sc->valid_cpu_types[0]); + assert(!sc->valid_cpu_types[1]); + return sc->valid_cpu_types[0]; } =20 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) --=20 2.43.0