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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id h20-20020a170906111400b00a312e352dacsm624861eja.181.2024.01.26.05.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 05:31:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1706275871; x=1706880671; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QiekAr7rZgYcU2IGkVrfbUPYTKoPVa5QUXzJp79BZr4=; b=GozLm+OitaiA0LKWYasEq44fKd4DhSXF11uqW7/dD/ZcSk8qpuCYi1CH3/juq/2Mpi MKdoYR5OSfwJYED8eRaZTWY2CFsCHYUMnefxuHF6p6c8fRlZe1Xgzsu4b7ogI6HcTgM5 3LFdNm5dfHOQrxYaYAVXApwxDaCurH8jA5AP9W2JA19c6fZHO2x4tfBQpZavg2oBWVXq 58rKfzg/p/CRHM372oVBBvn9gQ/rVwpvkyTB13a35ntrav80PIYzBKS5NTqWkoPu+4Fx eQfKYhqqg0cZAIAh3hIjcE1ur58FBPVwFT9TxUAL9peZlbnosH/kdgC2dr+700qSngVA xEeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706275871; x=1706880671; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QiekAr7rZgYcU2IGkVrfbUPYTKoPVa5QUXzJp79BZr4=; b=Oxo4x1nuD1+SfbVhP91vjzKpTEtOlLSiCrCBEqawM1MmpP7Tm2if+cGIrOQ7KV0D3D YXaOaD0KEld6+3N7gUlOMhVf9SyZXntrDixby4hs1yUwrCKzT9ITjPROSr5qzYsQ5vd/ nbRpy8Vv7h/DSIqoOhPVhR30KkxzDvSfqJEfOcKsWBsRdQgaJPccp68FeB00TcnjM/OG XgJm0jnO80rUASKEIfMx1lVtl3ELpGYIQtcHDpzhsTSl1ZVTcty2E2jG5iuzaJjgAopw iimg3svUQDTOZWkLTMU1ss9XAVC6MZ/k5gJZzq17Ho1jH2WWj5MrP+kZqyufhCVN7NBv lQlQ== X-Gm-Message-State: AOJu0YzB1/UI3nyXWlcgFJPD0glQRLqbdIHg/2/yIaj9NPRw5oaQWs5X fvBcd0dlANDm9XpMrSEMoRbatRQPZmPRhwZBMhPB7q4wpAPmI4RSSDq2VCdVhbzkBF/i8DFl3ow y X-Google-Smtp-Source: AGHT+IGA8SflCD9biBxv5FT4LbxrUj9L2yjkOdahc/csT8XM/1sdud8oSbh46LjSrZK0tGEWW7sOjw== X-Received: by 2002:a17:906:1d0b:b0:a31:5b30:6f54 with SMTP id n11-20020a1709061d0b00b00a315b306f54mr857524ejh.30.1706275871393; Fri, 26 Jan 2024 05:31:11 -0800 (PST) From: Andrew Jones To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, dbarboza@ventanamicro.com Subject: [PATCH v2 6/6] target/riscv: Promote svade to a normal extension Date: Fri, 26 Jan 2024 14:31:08 +0100 Message-ID: <20240126133101.61344-14-ajones@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240126133101.61344-8-ajones@ventanamicro.com> References: <20240126133101.61344-8-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1706275989744100004 Content-Type: text/plain; charset="utf-8" Named features are extensions which don't make sense for users to control and are therefore not exposed on the command line. However, svade is an extension which makes sense for users to control, so treat it like a "normal" extension. The default is false, even for the max cpu type, since QEMU has always implemented hardware A/D PTE bit updating, so users must opt into svade (or get it from a CPU type which enables it by default). Reviewed-by: Daniel Henrique Barboza Signed-off-by: Andrew Jones --- target/riscv/cpu.c | 8 +++----- target/riscv/tcg/tcg-cpu.c | 6 ++++++ 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a56c2ff91d6d..4ddde2541233 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1421,6 +1421,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { =20 MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), + MULTI_EXT_CFG_BOOL("svade", ext_svade, false), MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true), MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), @@ -1528,7 +1529,6 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_e= xts[] =3D { * and priv_ver like regular extensions. */ const RISCVCPUMultiExtConfig riscv_cpu_named_features[] =3D { - MULTI_EXT_CFG_BOOL("svade", ext_svade, true), MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), =20 /* @@ -2175,8 +2175,6 @@ static RISCVCPUProfile RVA22U64 =3D { * Other named features that we already implement: Sstvecd, Sstvala, * Sscounterenw * - * Named features that we need to enable: svade - * * The remaining features/extensions comes from RVA22U64. */ static RISCVCPUProfile RVA22S64 =3D { @@ -2188,11 +2186,11 @@ static RISCVCPUProfile RVA22S64 =3D { .ext_offsets =3D { /* rva22s64 exts */ CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt), - CPU_CFG_OFFSET(ext_svinval), + CPU_CFG_OFFSET(ext_svinval), CPU_CFG_OFFSET(ext_svade), =20 /* rva22s64 named features */ CPU_CFG_OFFSET(ext_sstvecd), CPU_CFG_OFFSET(ext_sstvala), - CPU_CFG_OFFSET(ext_sscounterenw), CPU_CFG_OFFSET(ext_svade), + CPU_CFG_OFFSET(ext_sscounterenw), =20 RISCV_PROFILE_EXT_LIST_END } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index bc3c45b11704..b93df1725a79 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1314,6 +1314,12 @@ static void riscv_init_max_cpu_extensions(Object *ob= j) isa_ext_update_enabled(cpu, prop->offset, true); } =20 + /* + * Some extensions can't be added without backward compatibilty concer= ns. + * Disable those, the user can still opt in to them on the command lin= e. + */ + cpu->cfg.ext_svade =3D false; + /* set vector version */ env->vext_ver =3D VEXT_VERSION_1_00_0; =20 --=20 2.43.0