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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id ch21-20020a170906c2d500b00a317346a353sm629974ejb.123.2024.01.26.05.31.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 05:31:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1706275870; x=1706880670; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c+kBSbmB+uu4ccq3+PBWVAG48fqoWqgXKPn/QchcjM0=; b=TxennN52JV8bHgwXoZ4PUTFZejDuxWdNSIUmZ6Gv1uk1T6ciwTQ5hG6HBktjoli1zL zGQrHzW87mYgIFy8w4q/fpnmt2+THZImgHpIr78M2HwDVk32MizEUayCMpyF2Cg8aqRY jKRX2TtCEvDeFDy/jwktwPPeZUIYcC3pNfl+IFJj57VBeyHUg86ZoTZ3x327LnJzxHbE 7O5BpvPE3u7KWoauEEmaDWm5FjXz46FmQRxdWw3jGljSOCMfdtBcBKROC8vePqC8E5hW XYXiYMg62oJtD26e1qkaJcwcsLfW178WuPay00k4GwW985XsOcqMcAuMUADeSZavIU+W zijg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706275870; x=1706880670; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c+kBSbmB+uu4ccq3+PBWVAG48fqoWqgXKPn/QchcjM0=; b=wQP8LajPyGDD2jj5Y3KWNDo4yOMz+R9CCEM1ClSLWyUNFFDrHlk6zHUpvt2hNxJfI2 hJwgjVYxuXgrr23dLIlAoL9O8le4kLLPemI5XvIXWMNQRpLoiZRujV4ih8jlggg0XFTS 21UxKlnTB2uXYjNpSPayMThds/Z3S7iANz6p7taQmXTUhV470p1Jh2633K6HWyUtY8nS G1xlIhhIbBkiekRg8tpDbyZWtYwJ/+24dLhEuIb6u3JWpxjsEtfH8rkKisPg622mmO0L J0aDqsWqlhgpFEgOVXGXVstPiceD6NWTq9aSb+K08Q1V5EsURqPL0e/uj6pUL+id5njv LjIQ== X-Gm-Message-State: AOJu0Yy/+CP8B2MoGwOEg+MHM+3HzzU54HQUZQxpIBGM0t9aMOKRiCiM frnThxocK6Sva7gIWTnji8Cr/QPklAOsvBI37aiMyAY8386CfiZTdjlBP03kuEclhn3jcWTYch8 a X-Google-Smtp-Source: AGHT+IHnMPbpTkj4Cy8/ecQ2CRy1VMACkWyevAHtLHanlI4/I7u4hit1TnA+TN5C8tebRoTW9t0wkA== X-Received: by 2002:a17:906:a2c8:b0:a2f:b9be:66df with SMTP id by8-20020a170906a2c800b00a2fb9be66dfmr783974ejb.17.1706275869993; Fri, 26 Jan 2024 05:31:09 -0800 (PST) From: Andrew Jones To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, dbarboza@ventanamicro.com Subject: [PATCH v2 5/6] target/riscv: Gate hardware A/D PTE bit updating Date: Fri, 26 Jan 2024 14:31:07 +0100 Message-ID: <20240126133101.61344-13-ajones@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240126133101.61344-8-ajones@ventanamicro.com> References: <20240126133101.61344-8-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1706275968243100008 Content-Type: text/plain; charset="utf-8" Gate hardware A/D PTE bit updating on {m,h}envcfg.ADUE and only enable menvcfg.ADUE on reset if svade has not been selected. Now that we also consider svade, we have four possible configurations: 1) !svade && !svadu use hardware updating and there's no way to disable it (the default, which maintains past behavior. Maintaining the default, even with !svadu is a change that fixes [1]) 2) !svade && svadu use hardware updating, but also provide {m,h}envcfg.ADUE, allowing software to switch to exception mode (being able to switch is a change which fixes [1]) 3) svade && !svadu use exception mode and there's no way to switch to hardware updating (this behavior change fixes [2]) 4) svade && svadu use exception mode, but also provide {m,h}envcfg.ADUE, allowing software to switch to hardware updating (this behavior change fixes [2]) Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in addre= ss translation") [1] Fixes: 48531f5adb2a ("target/riscv: implement svade") [2] Reviewed-by: Daniel Henrique Barboza Signed-off-by: Andrew Jones --- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 18 ++++++++++++++---- target/riscv/tcg/tcg-cpu.c | 16 +++++----------- 3 files changed, 20 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7fd433daee74..a56c2ff91d6d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -960,7 +960,7 @@ static void riscv_cpu_reset_hold(Object *obj) env->two_stage_lookup =3D false; =20 env->menvcfg =3D (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | - (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); + (!cpu->cfg.ext_svade && cpu->cfg.ext_svadu ? MENVCFG_AD= UE : 0); env->henvcfg =3D 0; =20 /* Initialized default priorities of local interrupts. */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8da9104da450..9da9758cb4d4 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -907,7 +907,9 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } =20 bool pbmte =3D env->menvcfg & MENVCFG_PBMTE; - bool adue =3D env->menvcfg & MENVCFG_ADUE; + bool svade =3D riscv_cpu_cfg(env)->ext_svade; + bool svadu =3D riscv_cpu_cfg(env)->ext_svadu; + bool adue =3D svadu ? env->menvcfg & MENVCFG_ADUE : !svade; =20 if (first_stage && two_stage && env->virt_enabled) { pbmte =3D pbmte && (env->henvcfg & HENVCFG_PBMTE); @@ -1082,9 +1084,17 @@ restart: return TRANSLATE_FAIL; } =20 - /* If necessary, set accessed and dirty bits. */ - target_ulong updated_pte =3D pte | PTE_A | - (access_type =3D=3D MMU_DATA_STORE ? PTE_D : 0); + target_ulong updated_pte =3D pte; + + /* + * If ADUE is enabled, set accessed and dirty bits. + * Otherwise raise an exception if necessary. + */ + if (adue) { + updated_pte |=3D PTE_A | (access_type =3D=3D MMU_DATA_STORE ? PTE_= D : 0); + } else if (!(pte & PTE_A) || (access_type =3D=3D MMU_DATA_STORE && !(p= te & PTE_D))) { + return TRANSLATE_FAIL; + } =20 /* Page table updates need to be atomic with MTTCG enabled */ if (updated_pte !=3D pte && !is_debug) { diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 6d5028cf84d0..bc3c45b11704 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -196,18 +196,14 @@ static bool cpu_cfg_offset_is_named_feat(uint32_t ext= _offset) =20 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offse= t) { - switch (feat_offset) { - case CPU_CFG_OFFSET(ext_zic64b): + /* + * All other named features are already enabled + * in riscv_tcg_cpu_instance_init(). + */ + if (feat_offset =3D=3D CPU_CFG_OFFSET(ext_zic64b)) { cpu->cfg.cbom_blocksize =3D 64; cpu->cfg.cbop_blocksize =3D 64; cpu->cfg.cboz_blocksize =3D 64; - break; - case CPU_CFG_OFFSET(ext_svade): - cpu->cfg.ext_svadu =3D false; - break; - default: - /* Named feature already enabled in riscv_tcg_cpu_instance_init */ - return; } } =20 @@ -349,8 +345,6 @@ static void riscv_cpu_update_named_features(RISCVCPU *c= pu) cpu->cfg.ext_zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 && cpu->cfg.cbop_blocksize =3D=3D 64 && cpu->cfg.cboz_blocksize =3D=3D 64; - - cpu->cfg.ext_svade =3D !cpu->cfg.ext_svadu; } =20 static void riscv_cpu_validate_g(RISCVCPU *cpu) --=20 2.43.0