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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id fg14-20020a056402548e00b00558a1937dddsm593262edb.63.2024.01.26.05.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 05:31:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1706275868; x=1706880668; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/80PDTg3x6xAn5TJUsK9pPA95tqYtQVDFChFHkikpCo=; b=XYLYNAkYCadnHtyel0Z6HbNEBIoRLxXt9V6b8q05ydoRYAU7kPuMCBD/vxpdzstPsU VN0DV40R1rnjpFRQ/zGdp+1f1wSEdnHsYMlkGYGys5iS7E0QbkRjEa3qep5SxRmDYXvF SW9e4PMLgj8lV1/uSDuVqrMNFZD9e78mWnVp0+KnlXWUdnNF69uG/FQlPGi5bVUscYSs ZQxiZ4Y1aPFlptGeuAFfQlC/ePe2AN4BSooGw60Og1y4vDAVC95wZXnWCYWpX7VjfHf2 8J32gcxqAY5ENWtx5CJtxjxZPbNwz9XlmiXOgBE8jIXMcaJnRh9JCNcsVJsM1G0OunPI s8Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706275868; x=1706880668; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/80PDTg3x6xAn5TJUsK9pPA95tqYtQVDFChFHkikpCo=; b=BtU4QDWRtPtntRE5k0rvkZCD0mhdNlOxO9wQXeKJLGR8vkYdbsVv5uTwYp2PQ84/gz mA0EMj23JAaNu8J8PtHDDoZpnHpyqQTaSuGMfcKyAbAxfFfElugVyytfgHOZP7Usyiog suQiJb9vLz2uKV1eFSF9AHv9ykdwSxoWlBAeTFE8vYOOd0QV7f7TJZyGZ65V8t/j9uHL 3d6GebW47Qgugg3H6w4p+mWzUoK45EfZR6SrJFfD7AXjceATtBsBoizFiivlULOifQtx scv8kOjbu1fZTPykIKaL1aPQKGLAKuccXR5frELnF2ESzI9R03GRaIjNDwuLVG6694mw 6+XA== X-Gm-Message-State: AOJu0YzQ3osXvzdMgQvz6Tj81yMwp80edLSW5ORXOyf7Oql1duUVJqfG 88t9xU93+/M5fK3Jrrxw6F+3mMmDPsCP6cGoj/cr25sQ/46qRgMKQMnDIMU5GJFUuqfWLEOaqhG s X-Google-Smtp-Source: AGHT+IHcZhvt3gp6MF/UCzl1rRpqoqI+Pc8/LpTWj7CPnO0Roc/86vY+PDlVCslk27gI46aED/cirQ== X-Received: by 2002:aa7:dacd:0:b0:55d:4047:52cc with SMTP id x13-20020aa7dacd000000b0055d404752ccmr354308eds.24.1706275868647; Fri, 26 Jan 2024 05:31:08 -0800 (PST) From: Andrew Jones To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, dbarboza@ventanamicro.com Subject: [PATCH v2 4/6] target/riscv: Reset henvcfg to zero Date: Fri, 26 Jan 2024 14:31:06 +0100 Message-ID: <20240126133101.61344-12-ajones@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240126133101.61344-8-ajones@ventanamicro.com> References: <20240126133101.61344-8-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1706275968233100007 Content-Type: text/plain; charset="utf-8" The hypervisor should decide what it wants to enable. Zero all configuration enable bits on reset. Also, commit ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension") missed one reference to 'hade'. Change it now. Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in addre= ss translation") Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extensio= n") Reviewed-by: Daniel Henrique Barboza Signed-off-by: Andrew Jones --- target/riscv/cpu.c | 3 +-- target/riscv/csr.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1ecd8a57ed02..7fd433daee74 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -961,8 +961,7 @@ static void riscv_cpu_reset_hold(Object *obj) =20 env->menvcfg =3D (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); - env->henvcfg =3D (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | - (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0); + env->henvcfg =3D 0; =20 /* Initialized default priorities of local interrupts. */ for (i =3D 0; i < ARRAY_SIZE(env->miprio); i++) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d9a010387f72..93f7bc2cb48f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2115,7 +2115,7 @@ static RISCVException read_henvcfg(CPURISCVState *env= , int csrno, /* * henvcfg.pbmte is read_only 0 when menvcfg.pbmte =3D 0 * henvcfg.stce is read_only 0 when menvcfg.stce =3D 0 - * henvcfg.hade is read_only 0 when menvcfg.hade =3D 0 + * henvcfg.adue is read_only 0 when menvcfg.adue =3D 0 */ *val =3D env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE= ) | env->menvcfg); --=20 2.43.0