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charset="utf-8" From: Hao Wu This patch wires the PCI mailbox module to Nuvoton SoC. Change-Id: I14c42c628258804030f0583889882842bde0d972 Signed-off-by: Hao Wu Signed-off-by: Nabih Estefan Reviewed-by: Tyrone Ting --- docs/system/arm/nuvoton.rst | 2 ++ hw/arm/npcm7xx.c | 17 ++++++++++++++++- include/hw/arm/npcm7xx.h | 2 ++ 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index 0424cae4b0..e611099545 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -50,6 +50,8 @@ Supported devices * Ethernet controller (EMC) * Tachometer * Peripheral SPI controller (PSPI) + * BIOS POST code FIFO + * PCI Mailbox =20 Missing devices --------------- diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 15ff21d047..c9e87162cb 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -53,6 +53,9 @@ /* ADC Module */ #define NPCM7XX_ADC_BA (0xf000c000) =20 +/* PCI Mailbox Module */ +#define NPCM7XX_PCI_MBOX_BA (0xf0848000) + /* Internal AHB SRAM */ #define NPCM7XX_RAM3_BA (0xc0008000) #define NPCM7XX_RAM3_SZ (4 * KiB) @@ -83,6 +86,9 @@ enum NPCM7xxInterrupt { NPCM7XX_UART1_IRQ, NPCM7XX_UART2_IRQ, NPCM7XX_UART3_IRQ, + NPCM7XX_PCI_MBOX_IRQ =3D 8, + NPCM7XX_KCS_HIB_IRQ =3D 9, + NPCM7XX_GMAC1_IRQ =3D 14, NPCM7XX_EMC1RX_IRQ =3D 15, NPCM7XX_EMC1TX_IRQ, NPCM7XX_MMC_IRQ =3D 26, @@ -456,6 +462,8 @@ static void npcm7xx_init(Object *obj) object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSP= I); } =20 + object_initialize_child(obj, "pci-mbox", &s->pci_mbox, + TYPE_NPCM7XX_PCI_MBOX); object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); } =20 @@ -706,6 +714,14 @@ static void npcm7xx_realize(DeviceState *dev, Error **= errp) } } =20 + /* PCI Mailbox. Cannot fail */ + sysbus_realize(SYS_BUS_DEVICE(&s->pci_mbox), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pci_mbox), 0, NPCM7XX_PCI_MBOX_BA); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pci_mbox), 1, + NPCM7XX_PCI_MBOX_BA + NPCM7XX_PCI_MBOX_RAM_SIZE); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pci_mbox), 0, + npcm7xx_irq(s, NPCM7XX_PCI_MBOX_IRQ)); + /* RAM2 (SRAM) */ memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", NPCM7XX_RAM2_SZ, &error_abort); @@ -765,7 +781,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **e= rrp) create_unimplemented_device("npcm7xx.usbd[8]", 0xf0838000, 4 * = KiB); create_unimplemented_device("npcm7xx.usbd[9]", 0xf0839000, 4 * = KiB); create_unimplemented_device("npcm7xx.sd", 0xf0840000, 8 * = KiB); - create_unimplemented_device("npcm7xx.pcimbx", 0xf0848000, 512 * = KiB); create_unimplemented_device("npcm7xx.aes", 0xf0858000, 4 * = KiB); create_unimplemented_device("npcm7xx.des", 0xf0859000, 4 * = KiB); create_unimplemented_device("npcm7xx.sha", 0xf085a000, 4 * = KiB); diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 72c7722096..cec3792a2e 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -26,6 +26,7 @@ #include "hw/misc/npcm7xx_clk.h" #include "hw/misc/npcm7xx_gcr.h" #include "hw/misc/npcm7xx_mft.h" +#include "hw/misc/npcm7xx_pci_mbox.h" #include "hw/misc/npcm7xx_pwm.h" #include "hw/misc/npcm7xx_rng.h" #include "hw/net/npcm7xx_emc.h" @@ -104,6 +105,7 @@ struct NPCM7xxState { OHCISysBusState ohci; NPCM7xxFIUState fiu[2]; NPCM7xxEMCState emc[2]; + NPCM7xxPCIMBoxState pci_mbox; NPCM7xxSDHCIState mmc; NPCMPSPIState pspi[2]; }; --=20 2.43.0.429.g432eaa2c6b-goog