From nobody Tue Nov 26 18:45:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706162302; cv=none; d=zohomail.com; s=zohoarc; b=TsXUtMZDL9w3VrV6KUVlRvN2dy2FJ7PDj09y8Y+0+oc2fCT852RRUtjBaBzRYDtlernlRIQze2F6/v81O3YQO5igf0K0koH/ekQ01IbGgVznkr5Wm8CnPojKH2HUm1YAfPRMM2YgEkJeNghuYhvcmE8KblzY6RJElIfykay7NVc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706162302; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rKDbGwEXvltki2wl7qUZU0z++HxczA7j4HHaOXKhPHg=; b=eR+a8ju9lmhSK9kvn3UCdb2zJ9k8eD3t/1q61HlFELXry3CHLuoQIaZEL0H5vvb0QVXbnS7SBguXstIenFRm6f18QgjuJtpyD2OG/+N3I1OpNvJwyjIxnFLZqpmhiPRtTQ/dPazNIU8B2iGI2FqwJRCuE4uwjsj4UuS+3sKIdDg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706162302978653.7406663199722; Wed, 24 Jan 2024 21:58:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rSsis-0003Pe-By; Thu, 25 Jan 2024 00:56:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rSsip-0003OK-So for qemu-devel@nongnu.org; Thu, 25 Jan 2024 00:56:19 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rSsio-0001JH-58 for qemu-devel@nongnu.org; Thu, 25 Jan 2024 00:56:19 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-40e86a9fc4bso80881935e9.2 for ; Wed, 24 Jan 2024 21:56:17 -0800 (PST) Received: from m1x-phil.lan (lec62-h02-176-184-19-125.dsl.sta.abo.bbox.fr. [176.184.19.125]) by smtp.gmail.com with ESMTPSA id fk15-20020a05600c0ccf00b0040e9f7dadc6sm1247688wmb.25.2024.01.24.21.56.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 24 Jan 2024 21:56:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706162176; x=1706766976; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rKDbGwEXvltki2wl7qUZU0z++HxczA7j4HHaOXKhPHg=; b=zGc/uNZZuYA2Bv/bIf5InCq0tv4CBJGTogFrFQOZKdf+0eZZlgFN6MeXNNkhMaHlu0 WCFCEAuHH+GzmV0uCv/Vp2pSiIZFwrz2UpLLx1GQ/xB5Z1zVsM6iQgKmw+1wnCyeUxdX KyZAm15KAVuF6iSC8g5W8T4eS2eFlgWR8hsWfVjXm3VDvH2Azi3o6BNy/KcrxmZmraHA rddus7ELPQxQlS6lg8PHXUxkWYDvBZFNrI+pWjMSMLnlfi1D6jh/pUOI+1p7iAMWpH/E /7oD4R53a1tNPFoeXsNUI/zgu9Zci5KZXW/QZ+JduGbocbTxyXw+yFCujaG8YvXV3x8P lXYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706162176; x=1706766976; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rKDbGwEXvltki2wl7qUZU0z++HxczA7j4HHaOXKhPHg=; b=afNbXobTqIRXqnsBNCK9aFDZ0bskMUAUphP83rJhRmTANpxkahWYcbmv2mKATMoVhi a3NlyfonNN8MbMc4sqLNnAYVO9FOlOHyagZphX4N1Oo6aYeWxzO6VKGrXGIVfoMmPnXX qJ9LqlBYtYad4BPVSNy96Widf+WQy2P1JFS1ophPLO78zcaUePvV8KIYv30IBtUcEat8 kbO40Tbr+87fIVQSc+YwWtCyVzbMsxhf5mEEGlm/UhSDEd8j2Kl6q6NpBBzBQyJUT6jX i5goZggzd5qTJgNqMbSRebRZ3IDsnXcwx9dWj4NrKyzGB/bT+FPsmCUzO8O0C4HvMLzO lvcQ== X-Gm-Message-State: AOJu0Ywytqxek3JOVPWEFCcXT73ggN7KpE/YvkS26blZ9GfHQ0zAo/Gh aBUy+2p7wGJem+t8hzWy+gMFzAsUiFJLGQjXrGQ21BLhtJvIjHfnvtpVs3AsIzRmv+vNVRJUA73 k X-Google-Smtp-Source: AGHT+IEZGTKPhhwHJUJ8qCGSE69Kj7kaCV3DqfkzQCz5D5mcqBlwkQELql0u1XY8mwVpwFzTmziqvQ== X-Received: by 2002:a05:600c:3581:b0:40e:6a5c:826a with SMTP id p1-20020a05600c358100b0040e6a5c826amr182613wmq.25.1706162176449; Wed, 24 Jan 2024 21:56:16 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-arm@nongnu.org, Andrew Jeffery , Joel Stanley , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PATCH v3 5/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init() Date: Thu, 25 Jan 2024 06:55:44 +0100 Message-ID: <20240125055544.79405-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240125055544.79405-1-philmd@linaro.org> References: <20240125055544.79405-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706162304321100006 Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type). Convert it to a NULL-terminated array (of a single non-NULL element). Set MachineClass::valid_cpu_types[] to use the common machine code to provide hints when the requested CPU is invalid (see commit e702cbc19e ("machine: Improve is_cpu_type_supported()"). Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/aspeed_soc.h | 3 ++- hw/arm/aspeed.c | 1 + hw/arm/aspeed_ast10x0.c | 6 +++++- hw/arm/aspeed_ast2400.c | 12 ++++++++++-- hw/arm/aspeed_ast2600.c | 6 +++++- hw/arm/aspeed_soc_common.c | 5 ++++- 6 files changed, 27 insertions(+), 6 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index a060a59918..0db5a41e71 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -128,7 +128,8 @@ struct AspeedSoCClass { DeviceClass parent_class; =20 const char *name; - const char *cpu_type; + /** valid_cpu_types: NULL terminated array of a single CPU type. */ + const char * const *valid_cpu_types; uint32_t silicon_rev; uint64_t sram_size; uint64_t secsram_size; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index d2d490a6d1..fc8355cdce 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1149,6 +1149,7 @@ static void aspeed_machine_class_init_cpus_defaults(M= achineClass *mc) mc->default_cpus =3D sc->num_cpus; mc->min_cpus =3D sc->num_cpus; mc->max_cpus =3D sc->num_cpus; + mc->valid_cpu_types =3D sc->valid_cpu_types; } =20 static void aspeed_machine_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index dca601a3f9..c3b5116a6a 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -417,13 +417,17 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) =20 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */ + NULL + }; DeviceClass *dc =3D DEVICE_CLASS(klass); AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(dc); =20 dc->realize =3D aspeed_soc_ast1030_realize; =20 sc->name =3D "ast1030-a1"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */ + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST1030_A1_SILICON_REV; sc->sram_size =3D 0xc0000; sc->secsram_size =3D 0x40000; /* 256 * KiB */ diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index 3baf95916d..8829561bb6 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -503,6 +503,10 @@ static void aspeed_ast2400_soc_realize(DeviceState *de= v, Error **errp) =20 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("arm926"), + NULL + }; AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 @@ -511,7 +515,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *= oc, void *data) dc->user_creatable =3D false; =20 sc->name =3D "ast2400-a1"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("arm926"); + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2400_A1_SILICON_REV; sc->sram_size =3D 0x8000; sc->spis_num =3D 1; @@ -527,6 +531,10 @@ static void aspeed_soc_ast2400_class_init(ObjectClass = *oc, void *data) =20 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("arm1176"), + NULL + }; AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 @@ -535,7 +543,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *= oc, void *data) dc->user_creatable =3D false; =20 sc->name =3D "ast2500-a1"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("arm1176"); + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2500_A1_SILICON_REV; sc->sram_size =3D 0x9000; sc->spis_num =3D 2; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index b264433cf0..46baba0e41 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -629,13 +629,17 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) =20 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a7"), + NULL + }; DeviceClass *dc =3D DEVICE_CLASS(oc); AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); =20 dc->realize =3D aspeed_soc_ast2600_realize; =20 sc->name =3D "ast2600-a3"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2600_A3_SILICON_REV; sc->sram_size =3D 0x16400; sc->spis_num =3D 2; diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index 36ca189ce9..123a0c432c 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -20,7 +20,10 @@ =20 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc) { - return sc->cpu_type; + assert(sc->valid_cpu_types); + assert(sc->valid_cpu_types[0]); + assert(!sc->valid_cpu_types[1]); + return sc->valid_cpu_types[0]; } =20 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) --=20 2.41.0