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Tue, 23 Jan 2024 14:49:11 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Joel Stanley , Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 5/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init() Date: Tue, 23 Jan 2024 23:48:42 +0100 Message-ID: <20240123224842.18485-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240123224842.18485-1-philmd@linaro.org> References: <20240123224842.18485-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706050228413100004 Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type). Convert it to a NULL-terminated array (of a single non-NULL element). Set MachineClass::valid_cpu_types[] to use the common machine code to provide hints when the requested CPU is invalid (see commit e702cbc19e ("machine: Improve is_cpu_type_supported()"). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Gavin Shan Reviewed-by: Richard Henderson --- include/hw/arm/aspeed_soc.h | 3 ++- hw/arm/aspeed.c | 1 + hw/arm/aspeed_ast10x0.c | 6 +++++- hw/arm/aspeed_ast2400.c | 12 ++++++++++-- hw/arm/aspeed_ast2600.c | 6 +++++- hw/arm/aspeed_soc_common.c | 5 ++++- 6 files changed, 27 insertions(+), 6 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index a060a59918..0db5a41e71 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -128,7 +128,8 @@ struct AspeedSoCClass { DeviceClass parent_class; =20 const char *name; - const char *cpu_type; + /** valid_cpu_types: NULL terminated array of a single CPU type. */ + const char * const *valid_cpu_types; uint32_t silicon_rev; uint64_t sram_size; uint64_t secsram_size; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 636a6269aa..1be3b6bcae 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1149,6 +1149,7 @@ static void aspeed_machine_class_init_cpus_defaults(M= achineClass *mc) mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D sc->num_cpus; + mc->valid_cpu_types =3D sc->valid_cpu_types; } =20 static void aspeed_machine_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index dca601a3f9..c3b5116a6a 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -417,13 +417,17 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) =20 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */ + NULL + }; DeviceClass *dc =3D DEVICE_CLASS(klass); AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(dc); =20 dc->realize =3D aspeed_soc_ast1030_realize; =20 sc->name =3D "ast1030-a1"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */ + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST1030_A1_SILICON_REV; sc->sram_size =3D 0xc0000; sc->secsram_size =3D 0x40000; /* 256 * KiB */ diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index 3baf95916d..8829561bb6 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -503,6 +503,10 @@ static void aspeed_ast2400_soc_realize(DeviceState *de= v, Error **errp) =20 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("arm926"), + NULL + }; AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 @@ -511,7 +515,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *= oc, void *data) dc->user_creatable =3D false; =20 sc->name =3D "ast2400-a1"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("arm926"); + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2400_A1_SILICON_REV; sc->sram_size =3D 0x8000; sc->spis_num =3D 1; @@ -527,6 +531,10 @@ static void aspeed_soc_ast2400_class_init(ObjectClass = *oc, void *data) =20 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("arm1176"), + NULL + }; AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 @@ -535,7 +543,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *= oc, void *data) dc->user_creatable =3D false; =20 sc->name =3D "ast2500-a1"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("arm1176"); + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2500_A1_SILICON_REV; sc->sram_size =3D 0x9000; sc->spis_num =3D 2; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index b264433cf0..46baba0e41 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -629,13 +629,17 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) =20 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a7"), + NULL + }; DeviceClass *dc =3D DEVICE_CLASS(oc); AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); =20 dc->realize =3D aspeed_soc_ast2600_realize; =20 sc->name =3D "ast2600-a3"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2600_A3_SILICON_REV; sc->sram_size =3D 0x16400; sc->spis_num =3D 2; diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index 36ca189ce9..123a0c432c 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -20,7 +20,10 @@ =20 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc) { - return sc->cpu_type; + assert(sc->valid_cpu_types); + assert(sc->valid_cpu_types[0]); + assert(!sc->valid_cpu_types[1]); + return sc->valid_cpu_types[0]; } =20 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) --=20 2.41.0