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Tue, 23 Jan 2024 14:48:55 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Joel Stanley , Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 2/5] hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus() Date: Tue, 23 Jan 2024 23:48:39 +0100 Message-ID: <20240123224842.18485-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240123224842.18485-1-philmd@linaro.org> References: <20240123224842.18485-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706050210367100003 Since commit b7f1a0cb76 ("arm/aspeed: Compute the number of CPUs from the SoC definition") Aspeed machines use the aspeed_soc_num_cpus() helper to set the number of CPUs. Use it for the ast1030-evb (commit 356b230ed1 "aspeed/soc: Add AST1030 support") and supermicrox11-bmc (commit 40a38df55e "hw/arm/aspeed: Add board model for Supermicro X11 BMC") machines. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Gavin Shan --- hw/arm/aspeed.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 4bc292ff84..5b01a4dd28 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1212,6 +1212,8 @@ static void aspeed_machine_supermicrox11_bmc_class_in= it(ObjectClass *oc, amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init =3D palmetto_bmc_i2c_init; mc->default_ram_size =3D 256 * MiB; + mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D + aspeed_soc_num_cpus(amc->soc_name); } =20 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *o= c, @@ -1586,11 +1588,12 @@ static void aspeed_minibmc_machine_ast1030_evb_clas= s_init(ObjectClass *oc, mc->init =3D aspeed_minibmc_machine_init; amc->i2c_init =3D ast1030_evb_i2c_init; mc->default_ram_size =3D 0; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D 1; amc->fmc_model =3D "sst25vf032b"; amc->spi_model =3D "sst25vf032b"; amc->num_cs =3D 2; amc->macs_mask =3D 0; + mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D + aspeed_soc_num_cpus(amc->soc_name); } =20 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, --=20 2.41.0