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Tue, 23 Jan 2024 14:48:50 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Joel Stanley , Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/5] hw/arm/aspeed: Remove dead code Date: Tue, 23 Jan 2024 23:48:38 +0100 Message-ID: <20240123224842.18485-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240123224842.18485-1-philmd@linaro.org> References: <20240123224842.18485-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706050210363100002 Remove copy/paste typo from commit 6c323aba40 ("hw/arm/aspeed: Adding new machine Tiogapass in QEMU"). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Gavin Shan Reviewed-by: Richard Henderson --- hw/arm/aspeed.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index cc59176563..4bc292ff84 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1301,7 +1301,6 @@ static void aspeed_machine_tiogapass_class_init(Objec= tClass *oc, void *data) mc->default_ram_size =3D 1 * GiB; mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D aspeed_soc_num_cpus(amc->soc_name); - aspeed_soc_num_cpus(amc->soc_name); }; =20 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *da= ta) --=20 2.41.0 From nobody Tue Nov 26 16:23:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706050210367100003 Since commit b7f1a0cb76 ("arm/aspeed: Compute the number of CPUs from the SoC definition") Aspeed machines use the aspeed_soc_num_cpus() helper to set the number of CPUs. Use it for the ast1030-evb (commit 356b230ed1 "aspeed/soc: Add AST1030 support") and supermicrox11-bmc (commit 40a38df55e "hw/arm/aspeed: Add board model for Supermicro X11 BMC") machines. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Gavin Shan --- hw/arm/aspeed.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 4bc292ff84..5b01a4dd28 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1212,6 +1212,8 @@ static void aspeed_machine_supermicrox11_bmc_class_in= it(ObjectClass *oc, amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init =3D palmetto_bmc_i2c_init; mc->default_ram_size =3D 256 * MiB; + mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D + aspeed_soc_num_cpus(amc->soc_name); } =20 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *o= c, @@ -1586,11 +1588,12 @@ static void aspeed_minibmc_machine_ast1030_evb_clas= s_init(ObjectClass *oc, mc->init =3D aspeed_minibmc_machine_init; amc->i2c_init =3D ast1030_evb_i2c_init; mc->default_ram_size =3D 0; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D 1; amc->fmc_model =3D "sst25vf032b"; amc->spi_model =3D "sst25vf032b"; amc->num_cs =3D 2; amc->macs_mask =3D 0; + mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D + aspeed_soc_num_cpus(amc->soc_name); } =20 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, --=20 2.41.0 From nobody Tue Nov 26 16:23:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706050215; cv=none; d=zohomail.com; s=zohoarc; b=FS+BNYxGMDt8PzWwAHV/FKuAUzNncu4RK8VW8LPZzJmsUNnek/lqW0kBGjmaHAqF6dWkAjTq8otbT2boEDp11Jd7tTqyLrep0Gnj6LAB42q/K9PFhgDWVl/NtPCAgZP9v1h9XAgz5GUtXi9N5cZdfiN0AOgUxxGO4O5vlRjkq/g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706050215; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 23 Jan 2024 14:49:00 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Joel Stanley , Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 3/5] hw/arm/aspeed: Init CPU defaults in a common helper Date: Tue, 23 Jan 2024 23:48:40 +0100 Message-ID: <20240123224842.18485-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240123224842.18485-1-philmd@linaro.org> References: <20240123224842.18485-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706050216392100001 Rework aspeed_soc_num_cpus() as a new init_cpus_defaults() helper to reduce code duplication. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Gavin Shan Reviewed-by: Richard Henderson --- hw/arm/aspeed.c | 71 +++++++++++++++++++------------------------------ 1 file changed, 28 insertions(+), 43 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 5b01a4dd28..636a6269aa 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1141,10 +1141,14 @@ static void aspeed_machine_class_props_init(ObjectC= lass *oc) "Change the SPI Flash model"); } =20 -static int aspeed_soc_num_cpus(const char *soc_name) +static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) { - AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(object_class_by_name(soc_name)); - return sc->num_cpus; + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(mc); + AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(object_class_by_name(amc->soc_= name)); + + mc->default_cpus =3D mc->min_cpus + =3D mc->max_cpus + =3D sc->num_cpus; } =20 static void aspeed_machine_class_init(ObjectClass *oc, void *data) @@ -1176,8 +1180,7 @@ static void aspeed_machine_palmetto_class_init(Object= Class *oc, void *data) amc->num_cs =3D 1; amc->i2c_init =3D palmetto_bmc_i2c_init; mc->default_ram_size =3D 256 * MiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; =20 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *d= ata) @@ -1193,8 +1196,7 @@ static void aspeed_machine_quanta_q71l_class_init(Obj= ectClass *oc, void *data) amc->num_cs =3D 1; amc->i2c_init =3D quanta_q71l_bmc_i2c_init; mc->default_ram_size =3D 128 * MiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); } =20 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, @@ -1212,8 +1214,7 @@ static void aspeed_machine_supermicrox11_bmc_class_in= it(ObjectClass *oc, amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init =3D palmetto_bmc_i2c_init; mc->default_ram_size =3D 256 * MiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); } =20 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *o= c, @@ -1231,8 +1232,7 @@ static void aspeed_machine_supermicro_x11spi_bmc_clas= s_init(ObjectClass *oc, amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init =3D palmetto_bmc_i2c_init; mc->default_ram_size =3D 512 * MiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); } =20 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *d= ata) @@ -1248,8 +1248,7 @@ static void aspeed_machine_ast2500_evb_class_init(Obj= ectClass *oc, void *data) amc->num_cs =3D 1; amc->i2c_init =3D ast2500_evb_i2c_init; mc->default_ram_size =3D 512 * MiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; =20 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *da= ta) @@ -1266,8 +1265,7 @@ static void aspeed_machine_yosemitev2_class_init(Obje= ctClass *oc, void *data) amc->num_cs =3D 2; amc->i2c_init =3D yosemitev2_bmc_i2c_init; mc->default_ram_size =3D 512 * MiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; =20 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) @@ -1283,8 +1281,7 @@ static void aspeed_machine_romulus_class_init(ObjectC= lass *oc, void *data) amc->num_cs =3D 2; amc->i2c_init =3D romulus_bmc_i2c_init; mc->default_ram_size =3D 512 * MiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; =20 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *dat= a) @@ -1301,8 +1298,7 @@ static void aspeed_machine_tiogapass_class_init(Objec= tClass *oc, void *data) amc->num_cs =3D 2; amc->i2c_init =3D tiogapass_bmc_i2c_init; mc->default_ram_size =3D 1 * GiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; =20 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *da= ta) @@ -1318,8 +1314,7 @@ static void aspeed_machine_sonorapass_class_init(Obje= ctClass *oc, void *data) amc->num_cs =3D 2; amc->i2c_init =3D sonorapass_bmc_i2c_init; mc->default_ram_size =3D 512 * MiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; =20 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *d= ata) @@ -1335,8 +1330,7 @@ static void aspeed_machine_witherspoon_class_init(Obj= ectClass *oc, void *data) amc->num_cs =3D 2; amc->i2c_init =3D witherspoon_bmc_i2c_init; mc->default_ram_size =3D 512 * MiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; =20 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *d= ata) @@ -1355,8 +1349,7 @@ static void aspeed_machine_ast2600_evb_class_init(Obj= ectClass *oc, void *data) ASPEED_MAC3_ON; amc->i2c_init =3D ast2600_evb_i2c_init; mc->default_ram_size =3D 1 * GiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; =20 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) @@ -1374,8 +1367,7 @@ static void aspeed_machine_tacoma_class_init(ObjectCl= ass *oc, void *data) amc->macs_mask =3D ASPEED_MAC2_ON; amc->i2c_init =3D witherspoon_bmc_i2c_init; /* Same board layout */ mc->default_ram_size =3D 1 * GiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; =20 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) @@ -1392,8 +1384,7 @@ static void aspeed_machine_g220a_class_init(ObjectCla= ss *oc, void *data) amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init =3D g220a_bmc_i2c_init; mc->default_ram_size =3D 1024 * MiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; =20 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) @@ -1410,8 +1401,7 @@ static void aspeed_machine_fp5280g2_class_init(Object= Class *oc, void *data) amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init =3D fp5280g2_bmc_i2c_init; mc->default_ram_size =3D 512 * MiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; =20 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) @@ -1429,8 +1419,7 @@ static void aspeed_machine_rainier_class_init(ObjectC= lass *oc, void *data) amc->macs_mask =3D ASPEED_MAC2_ON | ASPEED_MAC3_ON; amc->i2c_init =3D rainier_bmc_i2c_init; mc->default_ram_size =3D 1 * GiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; =20 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) @@ -1451,8 +1440,7 @@ static void aspeed_machine_fuji_class_init(ObjectClas= s *oc, void *data) amc->i2c_init =3D fuji_bmc_i2c_init; amc->uart_default =3D ASPEED_DEV_UART1; mc->default_ram_size =3D FUJI_BMC_RAM_SIZE; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; =20 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) @@ -1472,8 +1460,7 @@ static void aspeed_machine_bletchley_class_init(Objec= tClass *oc, void *data) amc->macs_mask =3D ASPEED_MAC2_ON; amc->i2c_init =3D bletchley_bmc_i2c_init; mc->default_ram_size =3D BLETCHLEY_BMC_RAM_SIZE; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); } =20 static void fby35_reset(MachineState *state, ShutdownCause reason) @@ -1515,6 +1502,7 @@ static void aspeed_machine_fby35_class_init(ObjectCla= ss *oc, void *data) amc->i2c_init =3D fby35_i2c_init; /* FIXME: Replace this macro with something more general */ mc->default_ram_size =3D FUJI_BMC_RAM_SIZE; + aspeed_machine_class_init_cpus_defaults(mc); // } =20 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) @@ -1592,8 +1580,7 @@ static void aspeed_minibmc_machine_ast1030_evb_class_= init(ObjectClass *oc, amc->spi_model =3D "sst25vf032b"; amc->num_cs =3D 2; amc->macs_mask =3D 0; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); } =20 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, @@ -1612,8 +1599,7 @@ static void aspeed_machine_qcom_dc_scm_v1_class_init(= ObjectClass *oc, amc->macs_mask =3D ASPEED_MAC2_ON | ASPEED_MAC3_ON; amc->i2c_init =3D qcom_dc_scm_bmc_i2c_init; mc->default_ram_size =3D 1 * GiB; - mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; =20 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, @@ -1632,8 +1618,7 @@ static void aspeed_machine_qcom_firework_class_init(O= bjectClass *oc, amc->macs_mask =3D ASPEED_MAC2_ON | ASPEED_MAC3_ON; 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Tue, 23 Jan 2024 14:49:06 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Joel Stanley , Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 4/5] hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper Date: Tue, 23 Jan 2024 23:48:41 +0100 Message-ID: <20240123224842.18485-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240123224842.18485-1-philmd@linaro.org> References: <20240123224842.18485-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706050228411100003 In order to alter AspeedSoCClass::cpu_type in the next commit, introduce the aspeed_soc_cpu_type() helper to retrieve the per-SoC CPU type from AspeedSoCClass. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Gavin Shan Reviewed-by: Richard Henderson --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast10x0.c | 2 +- hw/arm/aspeed_ast2400.c | 3 ++- hw/arm/aspeed_ast2600.c | 3 ++- hw/arm/aspeed_soc_common.c | 5 +++++ 5 files changed, 11 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index cb832bc1ee..a060a59918 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -143,6 +143,7 @@ struct AspeedSoCClass { qemu_irq (*get_irq)(AspeedSoCState *s, int dev); }; =20 +const char *aspeed_soc_cpu_type(AspeedSoCClass *sc); =20 enum { ASPEED_DEV_SPI_BOOT, diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 8becb146a8..dca601a3f9 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -211,7 +211,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) /* AST1030 CPU Core */ armv7m =3D DEVICE(&a->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 256); - qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc)); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); object_property_set_link(OBJECT(&a->armv7m), "memory", OBJECT(s->memory), &error_abort); diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index ad76035528..3baf95916d 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -156,7 +156,8 @@ static void aspeed_ast2400_soc_init(Object *obj) } =20 for (i =3D 0; i < sc->num_cpus; i++) { - object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type); + object_initialize_child(obj, "cpu[*]", &a->cpu[i], + aspeed_soc_cpu_type(sc)); } =20 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 386a88d4e0..b264433cf0 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -158,7 +158,8 @@ static void aspeed_soc_ast2600_init(Object *obj) } =20 for (i =3D 0; i < sc->num_cpus; i++) { - object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type); + object_initialize_child(obj, "cpu[*]", &a->cpu[i], + aspeed_soc_cpu_type(sc)); } =20 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index 828f61093b..36ca189ce9 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -18,6 +18,11 @@ #include "hw/char/serial.h" =20 =20 +const char *aspeed_soc_cpu_type(AspeedSoCClass *sc) +{ + return sc->cpu_type; +} + qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) { return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); --=20 2.41.0 From nobody Tue Nov 26 16:23:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706050228413100004 Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type). Convert it to a NULL-terminated array (of a single non-NULL element). Set MachineClass::valid_cpu_types[] to use the common machine code to provide hints when the requested CPU is invalid (see commit e702cbc19e ("machine: Improve is_cpu_type_supported()"). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Gavin Shan Reviewed-by: Richard Henderson --- include/hw/arm/aspeed_soc.h | 3 ++- hw/arm/aspeed.c | 1 + hw/arm/aspeed_ast10x0.c | 6 +++++- hw/arm/aspeed_ast2400.c | 12 ++++++++++-- hw/arm/aspeed_ast2600.c | 6 +++++- hw/arm/aspeed_soc_common.c | 5 ++++- 6 files changed, 27 insertions(+), 6 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index a060a59918..0db5a41e71 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -128,7 +128,8 @@ struct AspeedSoCClass { DeviceClass parent_class; =20 const char *name; - const char *cpu_type; + /** valid_cpu_types: NULL terminated array of a single CPU type. */ + const char * const *valid_cpu_types; uint32_t silicon_rev; uint64_t sram_size; uint64_t secsram_size; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 636a6269aa..1be3b6bcae 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1149,6 +1149,7 @@ static void aspeed_machine_class_init_cpus_defaults(M= achineClass *mc) mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D sc->num_cpus; + mc->valid_cpu_types =3D sc->valid_cpu_types; } =20 static void aspeed_machine_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index dca601a3f9..c3b5116a6a 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -417,13 +417,17 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) =20 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */ + NULL + }; DeviceClass *dc =3D DEVICE_CLASS(klass); AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(dc); =20 dc->realize =3D aspeed_soc_ast1030_realize; =20 sc->name =3D "ast1030-a1"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */ + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST1030_A1_SILICON_REV; sc->sram_size =3D 0xc0000; sc->secsram_size =3D 0x40000; /* 256 * KiB */ diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index 3baf95916d..8829561bb6 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -503,6 +503,10 @@ static void aspeed_ast2400_soc_realize(DeviceState *de= v, Error **errp) =20 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("arm926"), + NULL + }; AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 @@ -511,7 +515,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *= oc, void *data) dc->user_creatable =3D false; =20 sc->name =3D "ast2400-a1"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("arm926"); + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2400_A1_SILICON_REV; sc->sram_size =3D 0x8000; sc->spis_num =3D 1; @@ -527,6 +531,10 @@ static void aspeed_soc_ast2400_class_init(ObjectClass = *oc, void *data) =20 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("arm1176"), + NULL + }; AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 @@ -535,7 +543,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *= oc, void *data) dc->user_creatable =3D false; =20 sc->name =3D "ast2500-a1"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("arm1176"); + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2500_A1_SILICON_REV; sc->sram_size =3D 0x9000; sc->spis_num =3D 2; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index b264433cf0..46baba0e41 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -629,13 +629,17 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) =20 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a7"), + NULL + }; DeviceClass *dc =3D DEVICE_CLASS(oc); AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); =20 dc->realize =3D aspeed_soc_ast2600_realize; =20 sc->name =3D "ast2600-a3"; - sc->cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); + sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2600_A3_SILICON_REV; sc->sram_size =3D 0x16400; sc->spis_num =3D 2; diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index 36ca189ce9..123a0c432c 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -20,7 +20,10 @@ =20 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc) { - return sc->cpu_type; + assert(sc->valid_cpu_types); + assert(sc->valid_cpu_types[0]); + assert(!sc->valid_cpu_types[1]); + return sc->valid_cpu_types[0]; } =20 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) --=20 2.41.0