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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding; s=pp1; bh=FyMg7DyGtb9KE308hqwf8QEanwme8lOdWQT1vUdNquQ=; b=Mw7S6teYYwtr9/8dbcMbUis6AJ1K4O2XiLM0HYcVz7hU4AFp9Y2fvmHQrm3VVmio+LY0 UmV0KZhwLhxf56eijA0xWYMV6qOZ3wIDQaBpWKd4U3I8tCqubc9ts1i6zAypBqEOLC+q 0hHW0ti3yR8OXjh1kyYjkslmXZo7Or1kFL5maoK9/4HsIt+VFndxrJik514s1pjQVxFN VpvcA5J+HUtwNfjoQbfmkgBUtrAfC9AFniBGYG4+ljLL+BeXmKf2eVvZh73FjnFWzXlM dvdfDhZ+DwXd0L8D/9aZ33fyxCsgnXizBPYI58UT+Gm51PXuCU+DrNTuIR9zACedzRRU fw== From: Caleb Schlossin To: qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, danielhb413@gmail.com Subject: [PATCH] ppc/pnv: Improve pervasive topology calculation for big-core Date: Tue, 23 Jan 2024 13:50:05 -0600 Message-Id: <20240123195005.8965-1-calebs@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: uVeOJngu5TqTPO2w44j9ssOcy90pcwBt X-Proofpoint-ORIG-GUID: 9XuIJBRKJa8E192k5E4NFA5eA-hD_XSM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-23_11,2024-01-23_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 bulkscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 mlxscore=0 spamscore=0 mlxlogscore=999 impostorscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401230147 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.156.1; envelope-from=calebs@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 23 Jan 2024 16:24:01 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1706045102660100003 Content-Type: text/plain; charset="utf-8" Big (SMT8) cores have a complicated function to map the core, thread ID to pervasive topology (PIR). Fix this for power8, power9, and power10. Signed-off-by: Caleb Schlossin Reviewed-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv_chip.h | 2 +- include/hw/ppc/pnv_core.h | 1 + hw/ppc/pnv.c | 60 ++++++++++++++++++++++++++------------- hw/ppc/pnv_core.c | 8 +++--- target/ppc/misc_helper.c | 3 -- 5 files changed, 46 insertions(+), 28 deletions(-) diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 0ab5c42308..d77e63b0a4 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -142,7 +142,7 @@ struct PnvChipClass { =20 DeviceRealize parent_realize; =20 - uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); + uint32_t (*chip_pir)(PnvChip *chip, uint32_t core_id, uint32_t thread_= id); void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index 4db21229a6..c6d62fd145 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -36,6 +36,7 @@ struct PnvCore { /*< public >*/ PowerPCCPU **threads; uint32_t pir; + uint32_t hwid; uint64_t hrmor; PnvChip *chip; =20 diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0297871bdd..9964f2665a 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -141,8 +141,10 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, vo= id *fdt) int smt_threads =3D CPU_CORE(pc)->nr_threads; CPUPPCState *env =3D &cpu->env; PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cs); + PnvChipClass *pnv_cc =3D PNV_CHIP_GET_CLASS(chip); g_autofree uint32_t *servers_prop =3D g_new(uint32_t, smt_threads); int i; + uint32_t pir; uint32_t segs[] =3D {cpu_to_be32(28), cpu_to_be32(40), 0xffffffff, 0xffffffff}; uint32_t tbfreq =3D PNV_TIMEBASE_FREQ; @@ -158,15 +160,17 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, v= oid *fdt) char *nodename; int cpus_offset =3D get_cpus_node(fdt); =20 - nodename =3D g_strdup_printf("%s@%x", dc->fw_name, pc->pir); + pir =3D pnv_cc->chip_pir(chip, pc->hwid, 0); + + nodename =3D g_strdup_printf("%s@%x", dc->fw_name, pir); offset =3D fdt_add_subnode(fdt, cpus_offset, nodename); _FDT(offset); g_free(nodename); =20 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); =20 - _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); - _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); + _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); + _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); =20 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))= ); @@ -241,15 +245,17 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, v= oid *fdt) =20 /* Build interrupt servers properties */ for (i =3D 0; i < smt_threads; i++) { - servers_prop[i] =3D cpu_to_be32(pc->pir + i); + servers_prop[i] =3D cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i= )); } _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", servers_prop, sizeof(*servers_prop) * smt_threads))= ); } =20 -static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, +static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, uint32_t nr_threads) { + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); + uint32_t pir =3D pcc->chip_pir(chip, hwid, 0); uint64_t addr =3D PNV_ICP_BASE(chip) | (pir << 12); char *name; const char compat[] =3D "IBM,power8-icp\0IBM,ppc-xicp"; @@ -263,6 +269,7 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32= _t pir, rsize =3D sizeof(uint64_t) * 2 * nr_threads; reg =3D g_malloc(rsize); for (i =3D 0; i < nr_threads; i++) { + /* We know P8 PIR is linear with thread id */ reg[i * 2] =3D cpu_to_be64(addr | ((pir + i) * 0x1000)); reg[i * 2 + 1] =3D cpu_to_be64(0x1000); } @@ -315,7 +322,7 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, = void *fdt) pnv_dt_core(chip, pnv_core, fdt); =20 /* Interrupt Control Presenters (ICP). One per core. */ - pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_thread= s); + pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threa= ds); } =20 if (chip->ram_size) { @@ -987,9 +994,10 @@ static void pnv_init(MachineState *machine) * 25:28 Core number * 29:31 Thread ID */ -static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) +static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id, + uint32_t thread_id) { - return (chip->chip_id << 7) | (core_id << 3); + return (chip->chip_id << 7) | (core_id << 3) | thread_id; } =20 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, @@ -1041,14 +1049,26 @@ static void pnv_chip_power8_intc_print_info(PnvChip= *chip, PowerPCCPU *cpu, * * We only care about the lower bits. uint32_t is fine for the moment. */ -static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) +static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id, + uint32_t thread_id) { - return (chip->chip_id << 8) | (core_id << 2); + if (chip->nr_threads =3D=3D 8) { + return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id <<= 3) | + (thread_id >> 1); + } else { + return (chip->chip_id << 8) | (core_id << 2) | thread_id; + } } =20 -static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) +static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id, + uint32_t thread_id) { - return (chip->chip_id << 8) | (core_id << 2); + if (chip->nr_threads =3D=3D 8) { + return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id <<= 3) | + (thread_id >> 1); + } else { + return (chip->chip_id << 8) | (core_id << 2) | thread_id; + } } =20 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, @@ -1227,7 +1247,7 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Err= or **errp) int core_hwid =3D CPU_CORE(pnv_core)->core_id; =20 for (j =3D 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { - uint32_t pir =3D pcc->core_pir(chip, core_hwid) + j; + uint32_t pir =3D pcc->chip_pir(chip, core_hwid, j); PnvICPState *icp =3D PNV_ICP(xics_icp_get(chip8->xics, pir)); =20 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, @@ -1340,7 +1360,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *= klass, void *data) k->chip_cfam_id =3D 0x221ef04980000000ull; /* P8 Murano DD2.1 */ k->cores_mask =3D POWER8E_CORE_MASK; k->num_phbs =3D 3; - k->core_pir =3D pnv_chip_core_pir_p8; + k->chip_pir =3D pnv_chip_pir_p8; k->intc_create =3D pnv_chip_power8_intc_create; k->intc_reset =3D pnv_chip_power8_intc_reset; k->intc_destroy =3D pnv_chip_power8_intc_destroy; @@ -1364,7 +1384,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */ k->cores_mask =3D POWER8_CORE_MASK; k->num_phbs =3D 3; - k->core_pir =3D pnv_chip_core_pir_p8; + k->chip_pir =3D pnv_chip_pir_p8; k->intc_create =3D pnv_chip_power8_intc_create; k->intc_reset =3D pnv_chip_power8_intc_reset; k->intc_destroy =3D pnv_chip_power8_intc_destroy; @@ -1388,7 +1408,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) k->chip_cfam_id =3D 0x120d304980000000ull; /* P8 Naples DD1.0 */ k->cores_mask =3D POWER8_CORE_MASK; k->num_phbs =3D 4; - k->core_pir =3D pnv_chip_core_pir_p8; + k->chip_pir =3D pnv_chip_pir_p8; k->intc_create =3D pnv_chip_power8_intc_create; k->intc_reset =3D pnv_chip_power8_intc_reset; k->intc_destroy =3D pnv_chip_power8_intc_destroy; @@ -1646,7 +1666,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) =20 k->chip_cfam_id =3D 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ k->cores_mask =3D POWER9_CORE_MASK; - k->core_pir =3D pnv_chip_core_pir_p9; + k->chip_pir =3D pnv_chip_pir_p9; k->intc_create =3D pnv_chip_power9_intc_create; k->intc_reset =3D pnv_chip_power9_intc_reset; k->intc_destroy =3D pnv_chip_power9_intc_destroy; @@ -1895,7 +1915,7 @@ static void pnv_chip_power10_class_init(ObjectClass *= klass, void *data) =20 k->chip_cfam_id =3D 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ k->cores_mask =3D POWER10_CORE_MASK; - k->core_pir =3D pnv_chip_core_pir_p10; + k->chip_pir =3D pnv_chip_pir_p10; k->intc_create =3D pnv_chip_power10_intc_create; k->intc_reset =3D pnv_chip_power10_intc_reset; k->intc_destroy =3D pnv_chip_power10_intc_destroy; @@ -1985,8 +2005,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Erro= r **errp) chip->nr_threads, &error_fatal); object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, core_hwid, &error_fatal); - object_property_set_int(OBJECT(pnv_core), "pir", - pcc->core_pir(chip, core_hwid), &error_fat= al); + object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, + &error_fatal); object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_ad= dr, &error_fatal); object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 8c7afe037f..f40ab721d6 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -226,7 +226,7 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCP= U *cpu, Error **errp, int thread_index) { CPUPPCState *env =3D &cpu->env; - int core_pir; + int core_hwid; ppc_spr_t *pir =3D &env->spr_cb[SPR_PIR]; ppc_spr_t *tir =3D &env->spr_cb[SPR_TIR]; Error *local_err =3D NULL; @@ -242,10 +242,10 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPC= CPU *cpu, Error **errp, return; } =20 - core_pir =3D object_property_get_uint(OBJECT(pc), "pir", &error_abort); + core_hwid =3D object_property_get_uint(OBJECT(pc), "hwid", &error_abor= t); =20 tir->default_value =3D thread_index; - pir->default_value =3D core_pir + thread_index; + pir->default_value =3D pcc->chip_pir(pc->chip, core_hwid, thread_index= ); =20 /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); @@ -342,7 +342,7 @@ static void pnv_core_unrealize(DeviceState *dev) } =20 static Property pnv_core_properties[] =3D { - DEFINE_PROP_UINT32("pir", PnvCore, pir, 0), + DEFINE_PROP_UINT32("hwid", PnvCore, hwid, 0), DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0), DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *), DEFINE_PROP_END_OF_LIST(), diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index a9d41d2802..58e808dc96 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -49,9 +49,6 @@ void helper_spr_core_write_generic(CPUPPCState *env, uint= 32_t sprn, CPUState *cs =3D env_cpu(env); CPUState *ccs; uint32_t nr_threads =3D cs->nr_threads; - uint32_t core_id =3D env->spr[SPR_PIR] & ~(nr_threads - 1); - - assert(core_id =3D=3D env->spr[SPR_PIR] - env->spr[SPR_TIR]); =20 if (nr_threads =3D=3D 1) { env->spr[sprn] =3D val; --=20 2.31.1