From nobody Sat Sep 21 04:37:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170602497302718.355188423706863; Tue, 23 Jan 2024 07:49:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rSJ0a-00034e-Ul; Tue, 23 Jan 2024 10:48:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rSIzx-0002oa-CR; Tue, 23 Jan 2024 10:47:37 -0500 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rSIzs-0000h1-Vf; Tue, 23 Jan 2024 10:47:37 -0500 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 4B41646921; Tue, 23 Jan 2024 18:47:50 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 4699469EB0; Tue, 23 Jan 2024 18:47:09 +0300 (MSK) Received: (nullmailer pid 3847906 invoked by uid 1000); Tue, 23 Jan 2024 15:47:08 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Paolo Bonzini , Mark Cave-Ayland , Richard Henderson , Michael Tokarev Subject: [Stable-8.2.1 42/54] target/i386: pcrel: store low bits of physical address in data[0] Date: Tue, 23 Jan 2024 18:46:43 +0300 Message-Id: <20240123154708.3847837-4-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1706024973943100001 Content-Type: text/plain; charset="utf-8" From: Paolo Bonzini For PC-relative translation blocks, env->eip changes during the execution of a translation block, Therefore, QEMU must be able to recover an instruction's PC just from the TranslationBlock struct and the instruction data with. Because a TB will not span two pages, QEMU stores all the low bits of EIP in the instruction data and replaces them in x86_restore_state_to_opc. Bits 12 and higher (which may vary between executions of a PCREL TB, since these only use the physical address in the hash key) are kept unmodified from env->eip. The assumption is that these bits of EIP, unlike bits 0-11, will not change as the translation block executes. Unfortunately, this is incorrect when the CS base is not aligned to a page. Then the linear address of the instructions (i.e. the one with the CS base addred) indeed will never span two pages, but bits 12+ of EIP can actually change. For example, if CS base is 0x80262200 and EIP =3D 0x6FF4, the first instruction in the translation block will be at linear address 0x802691F4. Even a very small TB will cross to EIP =3D 0x7xxx, while the linear addresses will remain comfortably within a single page. The fix is simply to use the low bits of the linear address for data[0], since those don't change. Then x86_restore_state_to_opc uses tb->cs_base to compute a temporary linear address (referring to some unknown instruction in the TB, but with the correct values of bits 12 and higher); the low bits are replaced with data[0], and EIP is obtained by subtracting again the CS base. Huge thanks to Mark Cave-Ayland for the image and initial debugging, and to Gitlab user @kjliew for help with bisecting another occurrence of (hopefully!) the same bug. It should be relatively easy to write a testcase that performs MMIO on an EIP with different bits 12+ than the first instruction of the translation block; any help is welcome. Fixes: e3a79e0e878 ("target/i386: Enable TARGET_TB_PCREL", 2022-10-11) Cc: qemu-stable@nongnu.org Cc: Mark Cave-Ayland Cc: Richard Henderson Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1759 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1964 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2012 Signed-off-by: Paolo Bonzini (cherry picked from commit 729ba8e933f8af5800c3a92b37e630e9bdaa9f1e) Signed-off-by: Michael Tokarev diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 6e881e9e27..1d54164bdf 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -68,14 +68,26 @@ static void x86_restore_state_to_opc(CPUState *cs, X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; int cc_op =3D data[1]; + uint64_t new_pc; =20 if (tb_cflags(tb) & CF_PCREL) { - env->eip =3D (env->eip & TARGET_PAGE_MASK) | data[0]; - } else if (tb->flags & HF_CS64_MASK) { - env->eip =3D data[0]; + /* + * data[0] in PC-relative TBs is also a linear address, i.e. an ad= dress with + * the CS base added, because it is not guaranteed that EIP bits 1= 2 and higher + * stay the same across the translation block. Add the CS base ba= ck before + * replacing the low bits, and subtract it below just like for !CF= _PCREL. + */ + uint64_t pc =3D env->eip + tb->cs_base; + new_pc =3D (pc & TARGET_PAGE_MASK) | data[0]; } else { - env->eip =3D (uint32_t)(data[0] - tb->cs_base); + new_pc =3D data[0]; } + if (tb->flags & HF_CS64_MASK) { + env->eip =3D new_pc; + } else { + env->eip =3D (uint32_t)(new_pc - tb->cs_base); + } + if (cc_op !=3D CC_OP_DYNAMIC) { env->cc_op =3D cc_op; } diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 312ca0d594..8fd49ff474 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -6972,7 +6972,6 @@ static void i386_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) =20 dc->prev_insn_end =3D tcg_last_op(); if (tb_cflags(dcbase->tb) & CF_PCREL) { - pc_arg -=3D dc->cs_base; pc_arg &=3D ~TARGET_PAGE_MASK; } tcg_gen_insn_start(pc_arg, dc->cc_op); --=20 2.39.2