From nobody Wed Nov 13 07:18:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706025105517872.0134899232786; Tue, 23 Jan 2024 07:51:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rSJ1b-0005Ki-LF; Tue, 23 Jan 2024 10:49:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rSJ0G-0002r8-Px; Tue, 23 Jan 2024 10:47:57 -0500 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rSJ0C-0000kZ-WD; Tue, 23 Jan 2024 10:47:55 -0500 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 1693B46928; Tue, 23 Jan 2024 18:47:52 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 1F07A69EB7; Tue, 23 Jan 2024 18:47:11 +0300 (MSK) Received: (nullmailer pid 3847927 invoked by uid 1000); Tue, 23 Jan 2024 15:47:08 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Mark Cave-Ayland , Guenter Roeck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Michael Tokarev Subject: [Stable-8.2.1 49/54] hw/scsi/esp-pci: generate PCI interrupt from separate ESP and PCI sources Date: Tue, 23 Jan 2024 18:46:50 +0300 Message-Id: <20240123154708.3847837-11-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1706025106584100005 From: Mark Cave-Ayland The am53c974/dc390 PCI interrupt has two separate sources: the first is fro= m the internal ESP device, and the second is from the PCI DMA transfer logic. Update the ESP interrupt handler so that it sets DMA_STAT_SCSIINT rather th= an driving the PCI IRQ directly, and introduce a new esp_pci_update_irq() func= tion to generate the correct PCI IRQ level. In particular this fixes spurious in= terrupts being generated by setting DMA_STAT_DONE at the end of a transfer if DMA_CM= D_INTE_D isn't set in the DMA_CMD register. Signed-off-by: Mark Cave-Ayland Reviewed-by: Guenter Roeck Tested-by: Guenter Roeck Message-ID: <20240112131529.515642-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daud=C3=A9 (cherry picked from commit 6b41417d934b2640b7ccf893544d656eea92a2e7) Signed-off-by: Michael Tokarev diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c index ac5d752876..d29c8c25bd 100644 --- a/hw/scsi/esp-pci.c +++ b/hw/scsi/esp-pci.c @@ -77,6 +77,29 @@ struct PCIESPState { ESPState esp; }; =20 +static void esp_pci_update_irq(PCIESPState *pci) +{ + int scsi_level =3D !!(pci->dma_regs[DMA_STAT] & DMA_STAT_SCSIINT); + int dma_level =3D (pci->dma_regs[DMA_CMD] & DMA_CMD_INTE_D) ? + !!(pci->dma_regs[DMA_STAT] & DMA_STAT_DONE) : 0; + int level =3D scsi_level || dma_level; + + pci_set_irq(PCI_DEVICE(pci), level); +} + +static void esp_irq_handler(void *opaque, int irq_num, int level) +{ + PCIESPState *pci =3D PCI_ESP(opaque); + + if (level) { + pci->dma_regs[DMA_STAT] |=3D DMA_STAT_SCSIINT; + } else { + pci->dma_regs[DMA_STAT] &=3D ~DMA_STAT_SCSIINT; + } + + esp_pci_update_irq(pci); +} + static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val) { ESPState *s =3D &pci->esp; @@ -151,6 +174,7 @@ static void esp_pci_dma_write(PCIESPState *pci, uint32_= t saddr, uint32_t val) /* clear some bits on write */ uint32_t mask =3D DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_D= ONE; pci->dma_regs[DMA_STAT] &=3D ~(val & mask); + esp_pci_update_irq(pci); } break; default: @@ -161,17 +185,14 @@ static void esp_pci_dma_write(PCIESPState *pci, uint3= 2_t saddr, uint32_t val) =20 static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr) { - ESPState *s =3D &pci->esp; uint32_t val; =20 val =3D pci->dma_regs[saddr]; if (saddr =3D=3D DMA_STAT) { - if (s->rregs[ESP_RSTAT] & STAT_INT) { - val |=3D DMA_STAT_SCSIINT; - } if (!(pci->sbac & SBAC_STATUS)) { pci->dma_regs[DMA_STAT] &=3D ~(DMA_STAT_ERROR | DMA_STAT_ABORT= | DMA_STAT_DONE); + esp_pci_update_irq(pci); } } =20 @@ -350,6 +371,7 @@ static void esp_pci_command_complete(SCSIRequest *req, = size_t resid) esp_command_complete(req, resid); pci->dma_regs[DMA_WBC] =3D 0; pci->dma_regs[DMA_STAT] |=3D DMA_STAT_DONE; + esp_pci_update_irq(pci); } =20 static const struct SCSIBusInfo esp_pci_scsi_info =3D { @@ -386,7 +408,7 @@ static void esp_pci_scsi_realize(PCIDevice *dev, Error = **errp) "esp-io", 0x80); =20 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io); - s->irq =3D pci_allocate_irq(dev); + s->irq =3D qemu_allocate_irq(esp_irq_handler, pci, 0); =20 scsi_bus_init(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info); } --=20 2.39.2