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Tue, 23 Jan 2024 01:58:31 -0800 (PST) From: Shlomo Pongratz X-Google-Original-From: Shlomo Pongratz To: qemu-devel@nongnu.org Cc: andrew.sminov@gmail.com, peter.maydell@linaro.com, philmd@linaro.org, shlomop@pliops.com, shlomopongratz@gmail.com Subject: [PATCH v4] Handle wrap around in limit calculation Date: Tue, 23 Jan 2024 11:58:21 +0200 Message-Id: <20240123095821.59625-1-shlomop@pliops.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=shlomopongratz@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1706003962996100003 Content-Type: text/plain; charset="utf-8" Hanlde wrap around when calculating the viewport size caused by the fact that perior to version 460A the limit variable was 32bit quantity and not 64 bits quantity. In the i.MX 6Dual/6Quad Applications Processor Reference Manual document on which the original code was based upon in the description of the iATU Region Upper Base Address Register it is written: Forms bits [63:32] of the start (and end) address of the address region= to be translated. That is in this register is the upper of both base and the limit. In the current implementation this value was ignored for the limit which caused a wrap around of the size calculaiton. Using the documnet example: Base HI: 0x80000000 Base LO: 0xd0000000 Limit LO: 0xd000ffff The correct size is 0x80000000d000ffff - 0x80000000d0000000 + 1 =3D 0x010000 The wrong result is 0xd000ffff - 0x80000000d0000000 + 1 =3D 0x800000000= 0010000 Signed-off-by: Shlomo Pongratz ---- Changes since v3: * Use Peter Maydell's suggestion for fixing the bug, that is compute a 64 bits limit from the upper 32 bits of the base and the given 32 bits limit. Changes since v2: * Don't try to fix the calculation. * Change the limit variable from 32bit to 64 bit * Set the limit bits [63:32] same as the base according to the specification on which the original code was base upon. Changes since v1: * Seperate subject and description --- hw/pci-host/designware.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index dd9e389c07..f81dbe3975 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -269,8 +269,20 @@ static void designware_pcie_update_viewport(Designware= PCIERoot *root, { const uint64_t target =3D viewport->target; const uint64_t base =3D viewport->base; - const uint64_t size =3D (uint64_t)viewport->limit - base + 1; + uint64_t size; const bool enabled =3D viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE; + uint64_t limit; + + /* + * Versions 460A and above of this PCI controller have a + * 64-bit limit register. We currently model the older type + * where the limit register is 32 bits, and the upper 32 bits + * of the end address are the same as the upper 32 bits of + * the start address. + */ + + limit =3D deposit64(viewport->limit, 32, 32, extract64(base, 32, 32)); + size =3D limit - base + 1; =20 MemoryRegion *current, *other; =20 --=20 2.25.1