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Mon, 22 Jan 2024 07:12:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IFU7pIzXU5V0DyNVSgHWiHcTOmKQP8U4GOPOdTx0Yw5yymjpYb1j2I4hHXnfukTf0J8XTdaAQ== X-Received: by 2002:a05:600c:4292:b0:40e:5ad1:5820 with SMTP id v18-20020a05600c429200b0040e5ad15820mr2360851wmc.161.1705936339186; Mon, 22 Jan 2024 07:12:19 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, alex.bennee@linaro.org Subject: [PATCH] cpu-exec: simplify jump cache management Date: Mon, 22 Jan 2024 16:12:17 +0100 Message-ID: <20240122151217.348058-1-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.289, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1705936392923100003 Content-Type: text/plain; charset="utf-8" Unless I'm missing something egregious, the jmp cache is only every populated with a valid entry by the same thread that reads the cache. Therefore, the contents of any valid entry are always consistent and there is no need for any acquire/release magic. Indeed ->tb has to be accessed with atomics, because concurrent invalidations would otherwise cause data races. But ->pc is only ever accessed by one thread, and accesses to ->tb and ->pc within tb_lookup can never race with another tb_lookup. While the TranslationBlock (especially the flags) could be modified by a concurrent invalidation, store-release and load-acquire operations on the cache entry would not add any additional ordering beyond what you get from performing the accesses within a single thread. Because of this, there is really nothing to win in splitting the CF_PCREL and !CF_PCREL paths. It is easier to just always use the ->pc field in the jump cache. I noticed this while working on splitting commit 8ed558ec0cb ("accel/tcg: Introduce TARGET_TB_PCREL", 2022-10-04) into multiple pieces, for the sake of finding a more fine-grained bisection result for https://gitlab.com/qemu-project/qemu/-/issues/2092. It does not (and does not intend to) fix that issue; therefore it may make sense to not commit it until the root cause of issue #2092 is found. Signed-off-by: Paolo Bonzini --- accel/tcg/tb-jmp-cache.h | 8 +++--- accel/tcg/cpu-exec.c | 56 +++++++++++++++------------------------- 2 files changed, 26 insertions(+), 38 deletions(-) diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h index bb424c8a05b..4ab8553afcc 100644 --- a/accel/tcg/tb-jmp-cache.h +++ b/accel/tcg/tb-jmp-cache.h @@ -13,9 +13,11 @@ #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) =20 /* - * Accessed in parallel; all accesses to 'tb' must be atomic. - * For CF_PCREL, accesses to 'pc' must be protected by a - * load_acquire/store_release to 'tb'. + * Invalidated in parallel; all accesses to 'tb' must be atomic. + * A valid entry is read/written by a single CPU, therefore there is + * no need for qatomic_rcu_read() and pc is always consistent with a + * non-NULL value of 'tb'. Strictly speaking pc is only needed for + * CF_PCREL, but it's used always for simplicity. */ struct CPUJumpCache { struct rcu_head rcu; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 67eda9865ee..bdccf375288 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -253,43 +253,29 @@ static inline TranslationBlock *tb_lookup(CPUState *c= pu, vaddr pc, hash =3D tb_jmp_cache_hash_func(pc); jc =3D cpu->tb_jmp_cache; =20 - if (cflags & CF_PCREL) { - /* Use acquire to ensure current load of pc from jc. */ - tb =3D qatomic_load_acquire(&jc->array[hash].tb); - - if (likely(tb && - jc->array[hash].pc =3D=3D pc && - tb->cs_base =3D=3D cs_base && - tb->flags =3D=3D flags && - tb_cflags(tb) =3D=3D cflags)) { - return tb; - } - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cflags); - if (tb =3D=3D NULL) { - return NULL; - } - jc->array[hash].pc =3D pc; - /* Ensure pc is written first. */ - qatomic_store_release(&jc->array[hash].tb, tb); - } else { - /* Use rcu_read to ensure current load of pc from *tb. */ - tb =3D qatomic_rcu_read(&jc->array[hash].tb); - - if (likely(tb && - tb->pc =3D=3D pc && - tb->cs_base =3D=3D cs_base && - tb->flags =3D=3D flags && - tb_cflags(tb) =3D=3D cflags)) { - return tb; - } - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cflags); - if (tb =3D=3D NULL) { - return NULL; - } - /* Use the pc value already stored in tb->pc. */ - qatomic_set(&jc->array[hash].tb, tb); + tb =3D qatomic_read(&jc->array[hash].tb); + if (likely(tb && + jc->array[hash].pc =3D=3D pc && + tb->cs_base =3D=3D cs_base && + tb->flags =3D=3D flags && + tb_cflags(tb) =3D=3D cflags)) { + goto hit; } =20 + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cflags); + if (tb =3D=3D NULL) { + return NULL; + } + + jc->array[hash].pc =3D pc; + qatomic_set(&jc->array[hash].tb, tb); + +hit: + /* + * As long as tb is not NULL, the contents are consistent. Therefore, + * the virtual PC has to match for non-CF_PCREL translations. + */ + assert((tb_cflags(tb) & CF_PCREL) || tb->pc =3D=3D pc); return tb; } =20 --=20 2.43.0