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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id je6-20020a05600c1f8600b0040d8d11bf63sm39559584wmb.41.2024.01.22.06.35.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 06:35:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705934139; x=1706538939; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HadLfbJuSKfaEASuWIUz+ZfyQlTV96EslnoD7jrTY6E=; b=HxsqXuKweKsYaHaDAz4XkvvA2zPQGsjvqKOQZDLEOQ0cWKIgx90VpFsRxQPoH6L2Qy b1GwXvm6tZH2e4Fgq0gUKHejFeJ9kM7SrjPYHV1grBEZW0g/fIa4mFLaCzew/FwDbjwT vmxFpVQYRb7IdEgIIe5F7ADoZdMNx3QAxhh7cRiw8juxpsLHzRVCChCZKPWh+RPNA0d2 OFXPeMbQUgRt2go61vy+s5EJ2SDVyHw3SLXHY1F0kDmklyaR3zp6SFyUfEN1x/rQ64ol Kkt/nKBtf292c3G9Pm8uN0zjEFXdpdQWD1Ftxp57vSzA70ODU05sB/jSsXDQqID4WGDM knlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705934139; x=1706538939; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HadLfbJuSKfaEASuWIUz+ZfyQlTV96EslnoD7jrTY6E=; b=mTAJG9lDnGbZv66MylrKSuup29QdWD155jgiV5eHD/ZNKbyOp6NE897I7xjFTWaS/b qD71xyotajinbMpt3ftvNpRWHHsR83hcnX0R8SsCRorPsHBueRbXOoH8kkZN4dHktZmQ bRcKqGjtG8moDxBxHeBoEjkFjBfcYgRrXvheR6wzO+NCeNyAenwuKpY+u64V8CyXZaEO BFLnUVgIImqDCCvQXO4wJldBJeFzuiENYkcmQt0CH4yxmqF6tIbbAM2A6/uvG6oIMjBk ecqpPfSVOn0fq7qnXsbQVKzmP3rQiM9Fa8dYYHfxgbxOiCa/SiRx9+vlpwJDU1nQ0cWp mIMw== X-Gm-Message-State: AOJu0YybwBFHAB1O7f3vyVG3xVYRpGj7Q3ekmrDV4zvtWNlKGbY5tEXr jgdaEOrdCipSD95XuqdvCsrMJNwpO/ysW7/9p071RBS41b8Z0+0euMoG7TVbnoF9uHXaeWaztjA C X-Google-Smtp-Source: AGHT+IHyEIEgFSAyQSiCzE3hTE9HCyOiWhtY3InBSDQA652Ml2bO7jLXj9LHN9FzBVN9k9v2VEGEFQ== X-Received: by 2002:a05:600c:138a:b0:40e:5933:e2c2 with SMTP id u10-20020a05600c138a00b0040e5933e2c2mr2818825wmf.19.1705934139433; Mon, 22 Jan 2024 06:35:39 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Leif Lindholm , Marcin Juszkiewicz , Ard Biesheuvel , Shannon Zhao , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha Subject: [PATCH v2 1/3] tests/qtest/bios-tables-test: Allow changes to virt GTDT Date: Mon, 22 Jan 2024 14:35:35 +0000 Message-Id: <20240122143537.233498-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240122143537.233498-1-peter.maydell@linaro.org> References: <20240122143537.233498-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1705934207443100001 Content-Type: text/plain; charset="utf-8" Allow changes to the virt GTDT -- we are going to add the IRQ entry for a new timer to it. Signed-off-by: Peter Maydell Reviewed-by: Ard Biesheuvel --- tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8bf..7a6d4f80214 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/FACP", +"tests/data/acpi/virt/GTDT", --=20 2.34.1 From nobody Thu Nov 14 07:12:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1705934199; cv=none; d=zohomail.com; s=zohoarc; b=j9W/KY/twZnMU1K15nW9j5I8cp0lcNqERODPvqmyOHf9YA2NxLTDa3lNDLmdNiy5ABACZa3rqjr6OI0ASsMeNq1cCKifZv0RuBepItPT1uRpSqB4vhhP3EyFsAFoJw4W8v/56OFkjAeBqSoqwMReCvz0cDgqtfbJF4NvWVicxGk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705934199; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qYoo8Fo+6PVAm2eNAIuBwXIrCE8bc+TGcnBab8pzE6U=; b=NwI3IUebtYovn0an1UfzXsRjr7zp+l+GQAB1rdFnSWHfPLvZ+49+aIUvc6i56edgFi0czIOWG2Z5B5PlgstTdryTRXta6XsW8Uam36FtxIbD6jdITsB2TzdHf1NU9ffllhpu5B+gOGZBaLZCkTcnQRUFEoYbzUFcybvnsfxZjQs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705934199060198.182407864663; Mon, 22 Jan 2024 06:36:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rRvOv-0006S2-I8; Mon, 22 Jan 2024 09:35:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rRvOs-0006Ou-K8 for qemu-devel@nongnu.org; Mon, 22 Jan 2024 09:35:47 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rRvOo-0003a6-St for qemu-devel@nongnu.org; Mon, 22 Jan 2024 09:35:46 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-40e86a9fc4bso41903035e9.2 for ; Mon, 22 Jan 2024 06:35:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id je6-20020a05600c1f8600b0040d8d11bf63sm39559584wmb.41.2024.01.22.06.35.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 06:35:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705934140; x=1706538940; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qYoo8Fo+6PVAm2eNAIuBwXIrCE8bc+TGcnBab8pzE6U=; b=kqV8e6Lk6RdAFaBZBo45pYCNEquyz5U2rR3k56D23ngFCBvdnLjTQd0BLVWXqZKYCD Owm6xwO7MfPISMtchHtD2B0k2XRRtUQIE5nREwLpkL8tS+Cm1NzvQ+T7oX0ToQodyJbW tt77zC0lMKxSwDoDA+44/Hrzwr7JlZNqMsur+ayzBj+HXkklwkN+i51YPCdATBtFgEYw W7ix40JBIgt7V7LAbk5h3hKA9f93CG2xI9DVOyUuOhsGgHsl1OLlQg6U3mIJLwwMmNpO sGjklynd/adWrBLMP+ddmqWzjB6HjcO6VGlC9iLa/+bOP4AHtramMjnZAeKrOGhMhqFu t/iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705934140; x=1706538940; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qYoo8Fo+6PVAm2eNAIuBwXIrCE8bc+TGcnBab8pzE6U=; b=ut5bsDpnQ8E3Z3Vvhkd1ZIBcWkUTKEGzz8BRQLHZD25jTsbZwYSdzgaZ9xZ464hStP A/0aMbc9ozXdwqUfTRJgQaYZuGoSuIIKbvDfo1A2Mqf2isr5ifDxCfbBmDR2bA7lv5L1 /Zf9y+taisf/qbhQnmH0cDhFZd3HdR2pxymm6/6JYg8miDhiQywCUlCRHfaU94czio3S ZWZEyng6VA+ax416odK8N83pTotZq9XHRnznZXiQ8ZJwaa2ThfkR7uGoMFDsFAVN7GFK 5wvahQjqLfZzsueJEmhebJfmuFS6gPHKhOqvSzR9tCOBoeyklRW3ZjXzeWRBvoA9k1EY IlEQ== X-Gm-Message-State: AOJu0Yw6LHixyeTUjKcgJS6bxi3vqhtToszdDvg73eFsLPgLT3Bs7u9f dpFMlJa6+JnyHpuxCQZHyN9JPop8R95em60P/HttJeK4aMTUGUHO+lihqoy6+7U= X-Google-Smtp-Source: AGHT+IFWArmvhZKWNpAFOiCKERvH1OBCcdgav2Nh9SX+Am0KIU6Z7cXAJZXmSXgyBfUit4/CzdDGUA== X-Received: by 2002:a05:600c:291:b0:40e:44de:d2a9 with SMTP id 17-20020a05600c029100b0040e44ded2a9mr2566921wmk.208.1705934140027; Mon, 22 Jan 2024 06:35:40 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Leif Lindholm , Marcin Juszkiewicz , Ard Biesheuvel , Shannon Zhao , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha Subject: [PATCH v2 2/3] hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ Date: Mon, 22 Jan 2024 14:35:36 +0000 Message-Id: <20240122143537.233498-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240122143537.233498-1-peter.maydell@linaro.org> References: <20240122143537.233498-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1705934201408100003 Content-Type: text/plain; charset="utf-8" Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds a non-secure EL2 virtual timer. We implemented the timer itself in the CPU model, but never wired up its IRQ line to the GIC. Wire up the IRQ line (this is always safe whether the CPU has the interrupt or not, since it always creates the outbound IRQ line). Report it to the guest via dtb and ACPI if the CPU has the feature. The DTB binding is documented in the kernel's Documentation/devicetree/bindings/timer/arm\,arch_timer.yaml and the ACPI table entries are documented in the ACPI specification version 6.3 or later. Because the IRQ line ACPI binding is new in 6.3, we need to bump the FADT table rev to show that we might be using 6.3 features. Note that exposing this IRQ in the DTB will trigger a bug in EDK2 versions prior to edk2-stable202311, for users who use the virt board with 'virtualization=3Don' to enable EL2 emulation and are booting an EDK2 guest BIOS, if that EDK2 has assertions enabled. The effect is that EDK2 will assert on bootup: ASSERT [ArmTimerDxe] /home/kraxel/projects/qemu/roms/edk2/ArmVirtPkg/Libra= ry/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClientLib.c(72): PropSize =3D=3D= 36 || PropSize =3D=3D 48 If you see that assertion you should do one of: * update your EDK2 binaries to edk2-stable202311 or newer * use the 'virt-8.2' versioned machine type * not use 'virtualization=3Don' (The versions shipped with QEMU itself have the fix.) Signed-off-by: Peter Maydell Reviewed-by: Ard Biesheuvel --- include/hw/arm/virt.h | 2 ++ hw/arm/virt-acpi-build.c | 20 ++++++++++---- hw/arm/virt.c | 60 ++++++++++++++++++++++++++++++++++------ 3 files changed, 67 insertions(+), 15 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index f69239850e6..bb486d36b14 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -130,6 +130,7 @@ struct VirtMachineClass { /* Machines < 6.2 have no support for describing cpu topology to guest= */ bool no_cpu_topology; bool no_tcg_lpa2; + bool no_ns_el2_virt_timer_irq; }; =20 struct VirtMachineState { @@ -173,6 +174,7 @@ struct VirtMachineState { PCIBus *bus; char *oem_id; char *oem_table_id; + bool ns_el2_virt_timer_irq; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index a22a2f43a56..903ddf4a361 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -533,8 +533,8 @@ build_srat(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } =20 /* - * ACPI spec, Revision 5.1 - * 5.2.24 Generic Timer Description Table (GTDT) + * ACPI spec, Revision 6.5 + * 5.2.25 Generic Timer Description Table (GTDT) */ static void build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) @@ -548,7 +548,7 @@ build_gtdt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) uint32_t irqflags =3D vmc->claim_edge_triggered_timers ? 1 : /* Interrupt is Edge triggered */ 0; /* Interrupt is Level triggered */ - AcpiTable table =3D { .sig =3D "GTDT", .rev =3D 2, .oem_id =3D vms->oe= m_id, + AcpiTable table =3D { .sig =3D "GTDT", .rev =3D 3, .oem_id =3D vms->oe= m_id, .oem_table_id =3D vms->oem_table_id }; =20 acpi_table_begin(&table, table_data); @@ -584,7 +584,15 @@ build_gtdt(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) build_append_int_noprefix(table_data, 0, 4); /* Platform Timer Offset */ build_append_int_noprefix(table_data, 0, 4); - + if (vms->ns_el2_virt_timer_irq) { + /* Virtual EL2 Timer GSIV */ + build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, = 4); + /* Virtual EL2 Timer Flags */ + build_append_int_noprefix(table_data, irqflags, 4); + } else { + build_append_int_noprefix(table_data, 0, 4); + build_append_int_noprefix(table_data, 0, 4); + } acpi_table_end(linker, &table); } =20 @@ -771,10 +779,10 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms, unsigned dsdt_tbl_offse= t) { - /* ACPI v6.0 */ + /* ACPI v6.3 */ AcpiFadtData fadt =3D { .rev =3D 6, - .minor_ver =3D 0, + .minor_ver =3D 3, .flags =3D 1 << ACPI_FADT_F_HW_REDUCED_ACPI, .xdsdt_tbl_offset =3D &dsdt_tbl_offset, }; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 5cbc69dff83..fa7c233346e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -218,6 +218,20 @@ static void create_randomness(MachineState *ms, const = char *node) qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)= ); } =20 +/* + * The CPU object always exposes the NS EL2 virt timer IRQ line, + * but we don't want to advertise it to the guest in the dtb or ACPI + * table unless it's really going to do something. + */ +static bool ns_el2_virt_timer_present(void) +{ + ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(0)); + CPUARMState *env =3D &cpu->env; + + return arm_feature(env, ARM_FEATURE_AARCH64) && + arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= ); +} + static void create_fdt(VirtMachineState *vms) { MachineState *ms =3D MACHINE(vms); @@ -335,15 +349,29 @@ static void fdt_add_timer_nodes(const VirtMachineStat= e *vms) "arm,armv7-timer"); } qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); - qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", - GIC_FDT_IRQ_TYPE_PPI, - INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, - GIC_FDT_IRQ_TYPE_PPI, - INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, - GIC_FDT_IRQ_TYPE_PPI, - INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, - GIC_FDT_IRQ_TYPE_PPI, - INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); + if (vms->ns_el2_virt_timer_irq) { + qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflag= s, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqfla= gs, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqfla= gs, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), i= rqflags); + } else { + qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflag= s, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqfla= gs, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqfla= gs); + } } =20 static void fdt_add_cpu_nodes(const VirtMachineState *vms) @@ -786,6 +814,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, + [GTIMER_HYPVIRT] =3D ARCH_TIMER_NS_EL2_VIRT_IRQ, }; =20 for (unsigned irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { @@ -2221,6 +2250,11 @@ static void machvirt_init(MachineState *machine) qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); object_unref(cpuobj); } + + /* Now we've created the CPUs we can see if they have the hypvirt time= r */ + vms->ns_el2_virt_timer_irq =3D ns_el2_virt_timer_present() && + !vmc->no_ns_el2_virt_timer_irq; + fdt_add_timer_nodes(vms); fdt_add_cpu_nodes(vms); =20 @@ -3178,8 +3212,16 @@ DEFINE_VIRT_MACHINE_AS_LATEST(9, 0) =20 static void virt_machine_8_2_options(MachineClass *mc) { + VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_9_0_options(mc); compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); + /* + * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and + * earlier machines. (Exposing it tickles a bug in older EDK2 + * guest BIOS binaries.) + */ + vmc->no_ns_el2_virt_timer_irq =3D true; } DEFINE_VIRT_MACHINE(8, 2) =20 --=20 2.34.1 From nobody Thu Nov 14 07:12:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1705934247; cv=none; d=zohomail.com; s=zohoarc; b=PLLHbbm5H5jVO2MSulpUiJwXFs9koV8hYH60vu3B55g+MZ7L/7pn+8/LSIi0sx9ibEsE9HRBBkMJZdCfX3afkejWJ+vEsr+CNdlnSs+SRbof/coFJsN8Tf8DWD5R7KxVR89ovkpG4gkd830NBI3AFVEY4nw6feFXzqReo48Mjj4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705934247; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2zs7MDPOvZWrmEU8IHVt5IQIX44BpOcVLothjZAQjo0=; b=DrpuZkhzLJLx8KK6IBMcxJ6bFVdHSnUo1kWX0qzpao4+cjWgT41wbb971MTQX44od2ROEWd8mUhAz5l11AjIzhlxycctmodFka0vEKa28GMM85vr36PfF+i1OGPxA8Ev0HP/C+XLRERDCPAl5v2OhqKtZbqu/gmAQbPJ99WZNFM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705934247319525.2640426365697; Mon, 22 Jan 2024 06:37:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rRvOv-0006Ru-Dg; Mon, 22 Jan 2024 09:35:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rRvOt-0006P0-4C for qemu-devel@nongnu.org; Mon, 22 Jan 2024 09:35:47 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rRvOo-0003aP-Tf for qemu-devel@nongnu.org; Mon, 22 Jan 2024 09:35:46 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-40eb033c1b0so6805575e9.2 for ; Mon, 22 Jan 2024 06:35:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Tsirkin" , Igor Mammedov , Ani Sinha Subject: [PATCH v2 3/3] tests/qtest/bios-tables-tests: Update virt golden reference Date: Mon, 22 Jan 2024 14:35:37 +0000 Message-Id: <20240122143537.233498-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240122143537.233498-1-peter.maydell@linaro.org> References: <20240122143537.233498-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1705934249345100003 Content-Type: text/plain; charset="utf-8" Update the virt golden reference files to say that the FACP is ACPI v6.3, and the GTDT table is a revision 3 table with space for the virtual EL2 timer. Diffs from iasl: @@ -1,32 +1,32 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024 + * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024 * * ACPI Data Table [FACP] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "FACP" [Fixed ACPI Descr= iption Table (FADT)] [004h 0004 4] Table Length : 00000114 [008h 0008 1] Revision : 06 -[009h 0009 1] Checksum : 15 +[009h 0009 1] Checksum : 12 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] FACS Address : 00000000 [028h 0040 4] DSDT Address : 00000000 [02Ch 0044 1] Model : 00 [02Dh 0045 1] PM Profile : 00 [Unspecified] [02Eh 0046 2] SCI Interrupt : 0000 [030h 0048 4] SMI Command Port : 00000000 [034h 0052 1] ACPI Enable Value : 00 [035h 0053 1] ACPI Disable Value : 00 [036h 0054 1] S4BIOS Command : 00 [037h 0055 1] P-State Control : 00 @@ -86,33 +86,33 @@ Use APIC Physical Destination Mode (V4) : 0 Hardware Reduced (V5) : 1 Low Power S0 Idle (V5) : 0 [074h 0116 12] Reset Register : [Generic Address Structure] [074h 0116 1] Space ID : 00 [SystemMemory] [075h 0117 1] Bit Width : 00 [076h 0118 1] Bit Offset : 00 [077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] [078h 0120 8] Address : 0000000000000000 [080h 0128 1] Value to cause reset : 00 [081h 0129 2] ARM Flags (decoded below) : 0003 PSCI Compliant : 1 Must use HVC for PSCI : 1 -[083h 0131 1] FADT Minor Revision : 00 +[083h 0131 1] FADT Minor Revision : 03 [084h 0132 8] FACS Address : 0000000000000000 [08Ch 0140 8] DSDT Address : 0000000000000000 [094h 0148 12] PM1A Event Block : [Generic Address Structure] [094h 0148 1] Space ID : 00 [SystemMemory] [095h 0149 1] Bit Width : 00 [096h 0150 1] Bit Offset : 00 [097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] [098h 0152 8] Address : 0000000000000000 [0A0h 0160 12] PM1B Event Block : [Generic Address Structure] [0A0h 0160 1] Space ID : 00 [SystemMemory] [0A1h 0161 1] Bit Width : 00 [0A2h 0162 1] Bit Offset : 00 [0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] [0A4h 0164 8] Address : 0000000000000000 @@ -164,34 +164,34 @@ [0F5h 0245 1] Bit Width : 00 [0F6h 0246 1] Bit Offset : 00 [0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] [0F8h 0248 8] Address : 0000000000000000 [100h 0256 12] Sleep Status Register : [Generic Address Structure] [100h 0256 1] Space ID : 00 [SystemMemory] [101h 0257 1] Bit Width : 00 [102h 0258 1] Bit Offset : 00 [103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] [104h 0260 8] Address : 0000000000000000 [10Ch 0268 8] Hypervisor ID : 00000000554D4551 Raw Table Data: Length 276 (0x114) - 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BO= CHS + 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BO= CHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....= BXPC 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... - 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... + 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............= QEMU 0110: 00 00 00 00 // .... @@ -1,32 +1,32 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024 + * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024 * * ACPI Data Table [GTDT] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "GTDT" [Generic Timer De= scription Table] -[004h 0004 4] Table Length : 00000060 -[008h 0008 1] Revision : 02 -[009h 0009 1] Checksum : 9C +[004h 0004 4] Table Length : 00000068 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 93 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF [02Ch 0044 4] Reserved : 00000000 [030h 0048 4] Secure EL1 Interrupt : 0000001D [034h 0052 4] EL1 Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 Always On : 0 [038h 0056 4] Non-Secure EL1 Interrupt : 0000001E @@ -37,25 +37,28 @@ [040h 0064 4] Virtual Timer Interrupt : 0000001B [044h 0068 4] VT Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 Always On : 0 [048h 0072 4] Non-Secure EL2 Interrupt : 0000001A [04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 Always On : 0 [050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF [058h 0088 4] Platform Timer Count : 00000000 [05Ch 0092 4] Platform Timer Offset : 00000000 +[060h 0096 4] Virtual EL2 Timer GSIV : 00000000 +[064h 0100 4] Virtual EL2 Timer Flags : 00000000 -Raw Table Data: Length 96 (0x60) +Raw Table Data: Length 104 (0x68) - 0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20 // GTDT`.....BO= CHS + 0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20 // GTDTh.....BO= CHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....= BXPC 0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00 // ............= .... 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ............= .... 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ............= .... 0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 // ............= .... + 0060: 00 00 00 00 00 00 00 00 // ........ Signed-off-by: Peter Maydell Reviewed-by: Ard Biesheuvel --- tests/qtest/bios-tables-test-allowed-diff.h | 2 -- tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes 3 files changed, 2 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 7a6d4f80214..dfb8523c8bf 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,3 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/virt/FACP", -"tests/data/acpi/virt/GTDT", diff --git a/tests/data/acpi/virt/FACP b/tests/data/acpi/virt/FACP index ac05c35a69451519bd1152c54d1e741af36390f5..da0c3644cc4536a0a0141603ed4= 70bd11492b678 100644 GIT binary patch delta 25 gcmbQjG=3D+)F&CxkPgpq-PO=3Du!l<;2F$$vli407<0<)c^nh delta 28 kcmbQjG=3D+)F&CxkPgpq-PO>`nx<-|!<6Akz$^DuG%0AAS!ssI20 diff --git a/tests/data/acpi/virt/GTDT b/tests/data/acpi/virt/GTDT index 6f8cb9b8f30b55f4c93fe515982621e3db50feb2..7f330e04d144f9cc22eef06127e= cc19abf9e8009 100644 GIT binary patch delta 25 bcmYeu;BpUf3CUn!U|^m+kt>V?$N&QXMtB4L delta 16 Xcmc~u;BpUf2}xjJU|^avkt+-UB60)u --=20 2.34.1