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([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id l10-20020a056a00140a00b006d9b2694b0csm9414305pfu.200.2024.01.22.04.33.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 04:33:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1705926839; x=1706531639; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q0hQMCB/S+PWSRzizFQ2oD/ShlkoVt1OiHiwqqOUoOI=; b=VEVOuz00lV7Cu2uCZl6HkWi/eHZhTiROHaIraNCsvmRd0fWOUZCFLQSMKiMuY/Ec9U E0tnPRnunL+T52G9Cn7caEXwTwOouUVxJFzLJGP0sXSRVRE4yzG0ml1eKF7IK+aX8pZ8 yQb7CYyyDvOp+nPO6RCQSk6lbXbS7XVqDGHptwjQWo6xGOE5jEpozC4nisFQfEKloS2g Rqwm7UfHPVPkzxhaBlfGPK25M115NgQnE/+2U35/QHUvdy5gcWRSoZYVzDqW1YWC3uTk 8xmmR7lA8/C6IUci7wWO1Yd+BLIZ2sZvoWsRoXddgQiCoFBIFHghw77SE/bes7PFZJhE FRwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705926839; x=1706531639; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q0hQMCB/S+PWSRzizFQ2oD/ShlkoVt1OiHiwqqOUoOI=; b=iwPXP6llKbPgrbGG0VYCgXBJ7RJriljENCkahGY+MxjtL+9ihRBrYogGkaUnEvKcTN AwuEHQeTQE7xOkHEqrbLHn/4tey3wOWFcAx11pPPCf+Ot8iCahCjfHlPQr6baHChVXPk NVlwrFPhJ1UlE3KgH6B0MpO1eJKKNTTwSjF9CmbjvaMzjG5WQYcGvHNu0rh47lVMqCL5 9x5pqOIR7h10ngFudFnWAAA8ieMSD0mSNyQpHr7YKlLPHYB8TrCO9G48/OcE92F23puJ TBRrfWuL4BzBtJ+PyEQbsog39wijvBjEUHQqqfrHLg1YMvXKHm7rmMZnmwlhCoPBU0v+ m1qA== X-Gm-Message-State: AOJu0YzqvWKvmUuoC3aUZRF8/Hjo/TCk7hrG6AenLjOInzCVR9+6ZMkn UHzen/pVF9g9qpUn45u7jbyeqTCYbJT3KCPk59PraxsEVSRp3izL6F+WOPeD3sqLOddnPoZkcEg c X-Google-Smtp-Source: AGHT+IHQ7YdxpyhytqcPW6tCz9RUEKz2FfgFNtigi3C2YhkBZVQLdzKYB3LcIIOimQvBCHHSkzXeYA== X-Received: by 2002:a05:6358:7e55:b0:176:3f63:b7b6 with SMTP id p21-20020a0563587e5500b001763f63b7b6mr4148136rwm.60.1705926838728; Mon, 22 Jan 2024 04:33:58 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v3 1/2] target/riscv/cpu.c: add riscv_bare_cpu_init() Date: Mon, 22 Jan 2024 09:33:47 -0300 Message-ID: <20240122123348.973288-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240122123348.973288-1-dbarboza@ventanamicro.com> References: <20240122123348.973288-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1705926898342100003 Content-Type: text/plain; charset="utf-8" Next patch will add more bare CPUs. Their cpu_init() functions would be glorified copy/pastes of rv64i_bare_cpu_init(), differing only by a riscv_cpu_set_misa() call. Add a new .instance_init for the TYPE_RISCV_BARE_CPU typ to avoid this code repetition. While we're at it, add a better explanation on why we're disabling the timing extensions for bare CPUs. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 45 +++++++++++++++++++++++++++++---------------- 1 file changed, 29 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ad1df2318b..9b6e03a655 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -609,22 +609,6 @@ static void rv64i_bare_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; riscv_cpu_set_misa(env, MXL_RV64, RVI); - - /* Remove the defaults from the parent class */ - RISCV_CPU(obj)->cfg.ext_zicntr =3D false; - RISCV_CPU(obj)->cfg.ext_zihpm =3D false; - - /* Set to QEMU's first supported priv version */ - env->priv_ver =3D PRIV_VERSION_1_10_0; - - /* - * Support all available satp_mode settings. The default - * value will be set to MBARE if the user doesn't set - * satp_mode manually (see set_satp_mode_default()). - */ -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64); -#endif } #else static void rv32_base_cpu_init(Object *obj) @@ -1327,6 +1311,34 @@ static void riscv_cpu_init(Object *obj) cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; } =20 +static void riscv_bare_cpu_init(Object *obj) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + + /* + * Bare CPUs do not inherit the timer and performance + * counters from the parent class (see riscv_cpu_init() + * for info on why the parent enables them). + * + * Users have to explicitly enable these counters for + * bare CPUs. + */ + cpu->cfg.ext_zicntr =3D false; + cpu->cfg.ext_zihpm =3D false; + + /* Set to QEMU's first supported priv version */ + cpu->env.priv_ver =3D PRIV_VERSION_1_10_0; + + /* + * Support all available satp_mode settings. The default + * value will be set to MBARE if the user doesn't set + * satp_mode manually (see set_satp_mode_default()). + */ +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_SV64); +#endif +} + typedef struct misa_ext_info { const char *name; const char *description; @@ -2405,6 +2417,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_BARE_CPU, .parent =3D TYPE_RISCV_CPU, + .instance_init =3D riscv_bare_cpu_init, .abstract =3D true, }, DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), --=20 2.43.0