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c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s= qcppdkim1; bh=fYVV2ySwvqCc/JCk6nfWFvqp64w7jzR306S6mAKE2us=; b=Mi G7Z5ujVWE1w5utuyRXCg1AOQ+qS0oQSv6I5pS3vWc0gMF5Me8WDs+8p0EX3UBUj1 7Ta57lx1rz6qp9JI0w6h2kxIp+kQinP6Y4kzAqn7hZdFf1IjQ8n19vuuRtm5qW1m vB+ZcAZdcWB7HmnyTaJ5yoat2ongiE+ZGRuvLxutjcbOv/k0U4Z74IQ+WUMRcSv9 iMfN2ItwRU15ycsorJcaKStX31BZKdDc3GlxZJc6mcRb47xGxg+7kOTpMOKhxXug 6wdln5D2fyLb5kuMUWENEX/PnQZm74SIAdqRgGDzvfrvcWT/bmx+FKrEJexP8wcm A5II1+9UsLUtDXWP4HRA== From: Brian Cain To: CC: , , , , , , , , , , Subject: [PULL 03/15] Hexagon (target/hexagon) Clean up handling of modifier registers Date: Sun, 21 Jan 2024 22:34:49 -0800 Message-ID: <20240122063501.782041-4-bcain@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240122063501.782041-1-bcain@quicinc.com> References: <20240122063501.782041-1-bcain@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KdcjEZaNMmPXTzqZnrla-hjvCUHpGa90 X-Proofpoint-GUID: KdcjEZaNMmPXTzqZnrla-hjvCUHpGa90 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-21_04,2024-01-19_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 spamscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=475 priorityscore=1501 impostorscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401220046 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=bcain@quicinc.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1705905401206100003 From: Taylor Simpson Currently, the register number (MuN) for modifier registers is the modifier register number rather than the index into hex_gpr. This patch changes MuN to the hex_gpr index, which is consistent with the handling of control registers. Note that HELPER(fcircadd) needs the CS register corresponding to the modifier register specified in the instruction. We create a TCGv variable "CS" to hold the value to pass to the helper. Reviewed-by: Brian Cain Signed-off-by: Taylor Simpson Message-Id: <20231210220712.491494-2-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain --- target/hexagon/gen_tcg.h | 9 ++++----- target/hexagon/gen_tcg_funcs.py | 13 +++++++++---- target/hexagon/idef-parser/parser-helpers.c | 8 +++----- target/hexagon/macros.h | 3 +-- 4 files changed, 17 insertions(+), 16 deletions(-) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index d992059fce..1c4391b415 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -68,15 +68,14 @@ do { \ TCGv tcgv_siV =3D tcg_constant_tl(siV); \ tcg_gen_mov_tl(EA, RxV); \ - gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, \ - hex_gpr[HEX_REG_CS0 + MuN]); \ + gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, CS); \ } while (0) #define GET_EA_pcr(SHIFT) \ do { \ TCGv ireg =3D tcg_temp_new(); \ tcg_gen_mov_tl(EA, RxV); \ gen_read_ireg(ireg, MuV, (SHIFT)); \ - gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN= ]); \ + gen_helper_fcircadd(RxV, RxV, ireg, MuV, CS); \ } while (0) =20 /* Instructions with multiple definitions */ @@ -113,7 +112,7 @@ TCGv ireg =3D tcg_temp_new(); \ tcg_gen_mov_tl(EA, RxV); \ gen_read_ireg(ireg, MuV, SHIFT); \ - gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN= ]); \ + gen_helper_fcircadd(RxV, RxV, ireg, MuV, CS); \ LOAD; \ } while (0) =20 @@ -427,7 +426,7 @@ TCGv BYTE G_GNUC_UNUSED =3D tcg_temp_new(); \ tcg_gen_mov_tl(EA, RxV); \ gen_read_ireg(ireg, MuV, SHIFT); \ - gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN= ]); \ + gen_helper_fcircadd(RxV, RxV, ireg, MuV, CS); \ STORE; \ } while (0) =20 diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index f5246cee6d..02d93bc5ce 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -99,10 +99,15 @@ def genptr_decl(f, tag, regtype, regid, regno): hex_common.bad_register(regtype, regid) elif regtype =3D=3D "M": if regid =3D=3D "u": - f.write(f" const int {regtype}{regid}N =3D " f"insn->regno[= {regno}];\n") f.write( - f" TCGv {regtype}{regid}V =3D hex_gpr[{regtype}{regid}N= + " - "HEX_REG_M0];\n" + f" const int {regN} =3D insn->regno[{regno}] + HEX_REG_= M0;\n" + ) + f.write( + f" TCGv {regtype}{regid}V =3D hex_gpr[{regN}];\n" + ) + f.write( + f" TCGv CS G_GNUC_UNUSED =3D " + f"hex_gpr[{regN} - HEX_REG_M0 + HEX_REG_CS0];\n" ) else: hex_common.bad_register(regtype, regid) @@ -528,7 +533,7 @@ def gen_tcg_func(f, tag, regs, imms): ): declared.append(f"{regtype}{regid}V") if regtype =3D=3D "M": - declared.append(f"{regtype}{regid}N") + declared.append("CS") elif hex_common.is_new_val(regtype, regid, tag): declared.append(f"{regtype}{regid}N") else: diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/i= def-parser/parser-helpers.c index 4af020933a..95f2b43076 100644 --- a/target/hexagon/idef-parser/parser-helpers.c +++ b/target/hexagon/idef-parser/parser-helpers.c @@ -1541,10 +1541,8 @@ void gen_circ_op(Context *c, HexValue *increment, HexValue *modifier) { - HexValue cs =3D gen_tmp(c, locp, 32, UNSIGNED); HexValue increment_m =3D *increment; increment_m =3D rvalue_materialize(c, locp, &increment_m); - OUT(c, locp, "gen_read_reg(", &cs, ", HEX_REG_CS0 + MuN);\n"); OUT(c, locp, "gen_helper_fcircadd(", @@ -1555,7 +1553,7 @@ void gen_circ_op(Context *c, &increment_m, ", ", modifier); - OUT(c, locp, ", ", &cs, ");\n"); + OUT(c, locp, ", CS);\n"); } =20 HexValue gen_locnt_op(Context *c, YYLTYPE *locp, HexValue *src) @@ -2080,9 +2078,9 @@ void emit_arg(Context *c, YYLTYPE *locp, HexValue *ar= g) char reg_id[5]; reg_compose(c, locp, &(arg->reg), reg_id); EMIT_SIG(c, ", %s %s", type, reg_id); - /* MuV register requires also MuN to provide its index */ + /* MuV register requires also CS for circular addressing*/ if (arg->reg.type =3D=3D MODIFIER) { - EMIT_SIG(c, ", int MuN"); + EMIT_SIG(c, ", TCGv CS"); } } break; diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index f99390e2a8..1376d6ccc1 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -462,8 +462,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,= int shift) #define fPM_CIRI(REG, IMM, MVAL) \ do { \ TCGv tcgv_siV =3D tcg_constant_tl(siV); \ - gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, \ - hex_gpr[HEX_REG_CS0 + MuN]); \ + gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, CS); \ } while (0) #else #define fEA_IMM(IMM) do { EA =3D (IMM); } while (0) --=20 2.25.1