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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=OSL2GHUkDheOlsFtGxY+LT4CIeg4LkaX7rfcHlxNROE=; b=JoZcvFDL4p5l0ahQQ5aRsQqT37 cp4yUEEiaMeGy/5bpX5P1urEM380w4LN9H17fuZ9jPXyU6MWTxzdJUlmcFnGx5ZWHZdpgyKHXvnOn 1lPi/LOSULuipkBFPR3EbNKlmcaaCo2P2znVOANiNjQe3+6FEhrLLdexclazGK3Os5mQ=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 19/34] accel/tcg: [CPUTLB] Use TCGContext.addr_type instead of TARGET_LONG_BITS Date: Fri, 19 Jan 2024 15:40:09 +0100 Message-ID: <20240119144024.14289-20-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675505684100006 Content-Type: text/plain; charset="utf-8" [NOTE: We could also use target_long_bits(), which is introduced later] Signed-off-by: Anton Johansson --- include/exec/cpu_ldst.h | 31 ++++++++++++++++--------------- accel/tcg/cputlb.c | 34 ++++++++++++++++++++-------------- 2 files changed, 36 insertions(+), 29 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 24fe322d72..553e0119f9 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -340,7 +340,7 @@ static inline void clear_helper_retaddr(void) =20 #else =20 -#include "tcg/oversized-guest.h" +#include "tcg-target-reg-bits.h" =20 static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry, MMUAccessType access_type) @@ -353,20 +353,21 @@ static inline uint64_t tlb_read_idx(const CPUTLBEntry= *entry, QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=3D MMU_INST_FETCH * sizeof(uint64_t)); =20 -#if TARGET_LONG_BITS =3D=3D 32 - /* Use qatomic_read, in case of addr_write; only care about low bits. = */ - const uint32_t *ptr =3D (uint32_t *)&entry->addr_idx[access_type]; - ptr +=3D HOST_BIG_ENDIAN; - return qatomic_read(ptr); -#else - const uint64_t *ptr =3D &entry->addr_idx[access_type]; -# if TCG_OVERSIZED_GUEST - return *ptr; -# else - /* ofs might correspond to .addr_write, so use qatomic_read */ - return qatomic_read(ptr); -# endif -#endif + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + /* Use qatomic_read, in case of addr_write; only care about low bi= ts. */ + const uint32_t *ptr =3D (uint32_t *)&entry->addr_idx[access_type]; + ptr +=3D HOST_BIG_ENDIAN; + return qatomic_read(ptr); + } else { + const uint64_t *ptr =3D &entry->addr_idx[access_type]; + if (TCG_TARGET_REG_BITS =3D=3D 32) { + /* Oversized guest */ + return *ptr; + } else { + /* ofs might correspond to .addr_write, so use qatomic_read */ + return qatomic_read(ptr); + } + } } =20 static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 449c86301e..967d5da6d4 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -41,7 +41,7 @@ #include "qemu/plugin-memory.h" #endif #include "tcg/tcg-ldst.h" -#include "tcg/oversized-guest.h" +#include "tcg-target-reg-bits.h" =20 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ @@ -815,12 +815,13 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr a= ddr, unsigned bits) { TLBFlushRangeData d; + const unsigned long_bits =3D (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) = ? 32 : 64; =20 /* * If all bits are significant, and len is small, * this devolves to tlb_flush_page. */ - if (bits >=3D TARGET_LONG_BITS && len <=3D TARGET_PAGE_SIZE) { + if (bits >=3D long_bits && len <=3D TARGET_PAGE_SIZE) { tlb_flush_page_by_mmuidx(cpu, addr, idxmap); return; } @@ -858,12 +859,13 @@ void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src= _cpu, { TLBFlushRangeData d; CPUState *dst_cpu; + const unsigned long_bits =3D (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) = ? 32 : 64; =20 /* * If all bits are significant, and len is small, * this devolves to tlb_flush_page. */ - if (bits >=3D TARGET_LONG_BITS && len <=3D TARGET_PAGE_SIZE) { + if (bits >=3D long_bits && len <=3D TARGET_PAGE_SIZE) { tlb_flush_page_by_mmuidx_all_cpus(src_cpu, addr, idxmap); return; } @@ -908,12 +910,13 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUSta= te *src_cpu, { TLBFlushRangeData d, *p; CPUState *dst_cpu; + const unsigned long_bits =3D (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) = ? 32 : 64; =20 /* * If all bits are significant, and len is small, * this devolves to tlb_flush_page. */ - if (bits >=3D TARGET_LONG_BITS && len <=3D TARGET_PAGE_SIZE) { + if (bits >=3D long_bits && len <=3D TARGET_PAGE_SIZE) { tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap); return; } @@ -995,16 +998,19 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry = *tlb_entry, addr &=3D TARGET_PAGE_MASK; addr +=3D tlb_entry->addend; if ((addr - start) < length) { -#if TARGET_LONG_BITS =3D=3D 32 - uint32_t *ptr_write =3D (uint32_t *)&tlb_entry->addr_write; - ptr_write +=3D HOST_BIG_ENDIAN; - qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY); -#elif TCG_OVERSIZED_GUEST - tlb_entry->addr_write |=3D TLB_NOTDIRTY; -#else - qatomic_set(&tlb_entry->addr_write, - tlb_entry->addr_write | TLB_NOTDIRTY); -#endif + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + /* 32-bit */ + uint32_t *ptr_write =3D (uint32_t *)&tlb_entry->addr_write; + ptr_write +=3D HOST_BIG_ENDIAN; + qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY); + } else if (TCG_TARGET_REG_BITS =3D=3D 32) { + /* Oversized guest */ + tlb_entry->addr_write |=3D TLB_NOTDIRTY; + } else { + /* 64-bit */ + qatomic_set(&tlb_entry->addr_write, + tlb_entry->addr_write | TLB_NOTDIRTY); + } } } } --=20 2.43.0