From nobody Tue Nov 26 18:46:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675332; cv=none; d=zohomail.com; s=zohoarc; b=gMla57OpqvpFZe8ykmeiZ7wyG+EndB/hxMaXH9DEvR3CoM4fXL0zHtSj7LyxvVNX/Iq5/T+G39//x2Zdkl0WUKUeoX086K7W87Fy66F+oPWqYEKyZ3vtJ159mZZ4gwzdTt738YYehYUP8uUIY5haz1DUmqNM9fYAfUlKP9LrRWc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675332; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=8VbSSJ+elwAUh/3IBh5c6unmBtljyQ3plo6LsH7WdK4=; b=idSOJQ8Vt2Ye61jYQRlAeK3D3TVcaal/EEKHj7dk2EF+7p4iXbEHfaPe1GrOu+hwDPL9PoF5m/RYVLHb1M1p/fmG+0qn9H2eI7WU67vIfVlgko1BZRT/IW8zv7ycGUTzaCO7gvY2a32EBd2mDycm45+ix9iwpesGgraYo/4DsfM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705675332599118.33299784561166; Fri, 19 Jan 2024 06:42:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQq37-0005y7-5b; Fri, 19 Jan 2024 09:40:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2q-0005pt-7R for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:34 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2k-0003sh-1t for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=8VbSSJ+elwAUh/3IBh5c6unmBtljyQ3plo6LsH7WdK4=; b=FITrlALjFaKVMHTJ9yP75JbGb1 do4NHneJlsothXci4kF3y4HhYLcb8lgMYQMCEqerOYJsvFmFSCdWSgYVQf8MPho6y8fvfoaSL8oPg xAUm+1FrABt1w0SDwHw6NzO4UKUxrJpzZ0Ex2EX3yNHmlUnPwuOiHNTDLxxECrUxleYA=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 13/34] target: Uninline cpu_get_tb_cpu_state() Date: Fri, 19 Jan 2024 15:40:03 +0100 Message-ID: <20240119144024.14289-14-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675333034100005 Content-Type: text/plain; charset="utf-8" Required to compile accel/tcg/translate-all.c once for softmmu targets. The function gets quite big for some targets so uninlining makes sense. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- include/exec/cpu-common.h | 4 +++ target/alpha/cpu.h | 11 ------- target/arm/cpu.h | 3 -- target/avr/cpu.h | 18 ----------- target/cris/cpu.h | 10 ------ target/hexagon/cpu.h | 12 ------- target/hppa/cpu.h | 43 ------------------------- target/i386/cpu.h | 9 ------ target/loongarch/cpu.h | 11 ------- target/m68k/cpu.h | 16 --------- target/microblaze/cpu.h | 8 ----- target/mips/cpu.h | 9 ------ target/nios2/cpu.h | 12 ------- target/openrisc/cpu.h | 10 ------ target/ppc/cpu.h | 13 -------- target/riscv/cpu.h | 3 -- target/rx/cpu.h | 9 ------ target/s390x/cpu.h | 22 ------------- target/sh4/cpu.h | 15 --------- target/sparc/cpu.h | 35 -------------------- target/tricore/cpu.h | 12 ------- target/xtensa/cpu.h | 68 --------------------------------------- target/alpha/cpu.c | 11 +++++++ target/avr/cpu.c | 18 +++++++++++ target/cris/cpu.c | 10 ++++++ target/hexagon/cpu.c | 12 +++++++ target/hppa/cpu.c | 47 +++++++++++++++++++++++++++ target/i386/cpu.c | 9 ++++++ target/loongarch/cpu.c | 11 +++++++ target/m68k/cpu.c | 16 +++++++++ target/microblaze/cpu.c | 7 ++++ target/mips/cpu.c | 9 ++++++ target/nios2/cpu.c | 12 +++++++ target/openrisc/cpu.c | 10 ++++++ target/ppc/cpu.c | 11 +++++++ target/rx/cpu.c | 9 ++++++ target/s390x/cpu.c | 24 ++++++++++++++ target/sh4/cpu.c | 15 +++++++++ target/sparc/cpu.c | 35 ++++++++++++++++++++ target/tricore/cpu.c | 12 +++++++ target/xtensa/cpu.c | 68 +++++++++++++++++++++++++++++++++++++++ 41 files changed, 350 insertions(+), 349 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 12952c481c..b5dae4a9d6 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -70,6 +70,10 @@ unsigned int cpu_list_generation_id_get(void); */ int cpu_mmu_index(CPUArchState *env, bool ifetch); =20 +void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags); + + void tcg_flush_softmmu_tlb(CPUState *cs); void tcg_flush_jmp_cache(CPUState *cs); =20 diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e93186d50e..09937b32a2 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -452,17 +452,6 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, MemTxResult response, uintptr_t retad= dr); #endif =20 -static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *pflags =3D env->flags & ENV_FLAG_TB_MASK; -#ifdef CONFIG_USER_ONLY - *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #ifdef CONFIG_USER_ONLY /* Copied from linux ieee_swcr_to_fpcr. */ static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3dfca8f3ae..9732c836b2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3212,9 +3212,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *en= v) } #endif =20 -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); - enum { QEMU_PSCI_CONDUIT_DISABLED =3D 0, QEMU_PSCI_CONDUIT_SMC =3D 1, diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 581ba54aae..e454f3ac3c 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -183,24 +183,6 @@ enum { TB_FLAGS_SKIP =3D 2, }; =20 -static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - uint32_t flags =3D 0; - - *pc =3D env->pc_w * 2; - *cs_base =3D 0; - - if (env->fullacc) { - flags |=3D TB_FLAGS_FULL_ACCESS; - } - if (env->skip) { - flags |=3D TB_FLAGS_SKIP; - } - - *pflags =3D flags; -} - static inline int cpu_interrupts_enabled(CPUAVRState *env) { return env->sregI !=3D 0; diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 9587a2a229..1312a719b7 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -261,16 +261,6 @@ enum { =20 #include "exec/cpu-all.h" =20 -static inline void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D env->dslot | - (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG - | X_FLAG | PFIX_FLAG)); -} - #define cpu_list cris_cpu_list void cris_cpu_list(void); =20 diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 562b5c7095..8e0b7704ef 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -153,18 +153,6 @@ struct ArchCPU { =20 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) =20 -static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t hex_flags =3D 0; - *pc =3D env->gpr[HEX_REG_PC]; - *cs_base =3D 0; - if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { - hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); - } - *flags =3D hex_flags; -} - typedef HexagonCPU ArchCPU; =20 void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 3da91d41d4..088692db90 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -267,49 +267,6 @@ static inline target_ulong hppa_form_gva(CPUHPPAState = *env, uint64_t spc, #define TB_FLAG_PRIV_SHIFT 8 #define TB_FLAG_UNALIGN 0x400 =20 -static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - uint32_t flags =3D env->psw_n * PSW_N; - - /* TB lookup assumes that PC contains the complete virtual address. - If we leave space+offset separate, we'll get ITLB misses to an - incomplete virtual address. This also means that we must separate - out current cpu privilege from the low bits of IAOQ_F. */ -#ifdef CONFIG_USER_ONLY - *pc =3D env->iaoq_f & -4; - *cs_base =3D env->iaoq_b & -4; - flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#else - /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ - flags |=3D env->psw & (PSW_W | PSW_C | PSW_D); - flags |=3D (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - - *pc =3D (env->psw & PSW_C - ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) - : env->iaoq_f & -4); - *cs_base =3D env->iasq_f; - - /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise = zero - low 32-bits of CS_BASE. This will succeed for all direct branches, - which is the primary case we care about -- using goto_tb within a p= age. - Failure is indicated by a zero difference. */ - if (env->iasq_f =3D=3D env->iasq_b) { - target_sreg diff =3D env->iaoq_b - env->iaoq_f; - if (TARGET_REGISTER_BITS =3D=3D 32 || diff =3D=3D (int32_t)diff) { - *cs_base |=3D (uint32_t)diff; - } - } - if ((env->sr[4] =3D=3D env->sr[5]) - & (env->sr[4] =3D=3D env->sr[6]) - & (env->sr[4] =3D=3D env->sr[7])) { - flags |=3D TB_FLAG_SR_SAME; - } -#endif - - *pflags =3D flags; -} - target_ureg cpu_hppa_get_psw(CPUHPPAState *env); void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg); void cpu_hppa_loaded_fr0(CPUHPPAState *env); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7de2bad701..5e938fdac3 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2278,15 +2278,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *= env) #include "hw/i386/apic.h" #endif =20 -static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *cs_base =3D env->segs[R_CS].base; - *pc =3D *cs_base + env->eip; - *flags =3D env->hflags | - (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); -} - void do_cpu_init(X86CPU *cpu); =20 #define MCE_INJECT_BROADCAST 1 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index d85103c28d..ce9bdedbf0 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -449,17 +449,6 @@ static inline void set_pc(CPULoongArchState *env, uint= 64_t value) #define HW_FLAGS_EUEN_SXE 0x08 #define HW_FLAGS_VA32 0x20 =20 -static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; - *flags |=3D is_va32(env) * HW_FLAGS_VA32; -} - void loongarch_cpu_list(void); =20 #define cpu_list loongarch_cpu_list diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index da13111fd8..21c37e2267 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -596,22 +596,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr = physaddr, vaddr addr, #define TB_FLAGS_TRACE 16 #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) =20 -static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; - if (env->sr & SR_S) { - *flags |=3D TB_FLAGS_MSR_S; - *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; - *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; - } - if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { - *flags |=3D TB_FLAGS_TRACE; - } -} - void dump_mmu(CPUM68KState *env); =20 #endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 8f8b4f55d4..bdbbf2751b 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -404,14 +404,6 @@ void mb_tcg_init(void); /* Ensure there is no overlap between the two masks. */ QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); =20 -static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); - *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); -} - #if !defined(CONFIG_USER_ONLY) bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 49915af09d..6d9f95be18 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1344,15 +1344,6 @@ void itc_reconfigure(struct MIPSITUState *tag); /* helper.c */ target_ulong exception_resume_pc(CPUMIPSState *env); =20 -static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->active_tc.PC; - *cs_base =3D 0; - *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | - MIPS_HFLAG_HWRENA_ULR); -} - /** * mips_cpu_create_with_clock: * @typename: a MIPS CPU type. diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index c1d4fc6542..890d91d901 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -295,16 +295,4 @@ FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS =3D=3D 0. */ FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */ FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 =3D=3D 0. */ =20 -static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - unsigned crs =3D FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS); - - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->ctrl[CR_STATUS] & CR_STATUS_U) - | (crs ? 0 : R_TBFLAGS_CRS0_MASK) - | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK); -} - #endif /* NIOS2_CPU_H */ diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index d57f820743..bfa3d6fba6 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -366,16 +366,6 @@ static inline void cpu_set_gpr(CPUOpenRISCState *env, = int i, uint32_t val) env->shadow_gpr[0][i] =3D val; } =20 -static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) - | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) - | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); -} - static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) { return (env->sr diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index faba987dc0..46eeb78c33 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2511,19 +2511,6 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xe= r); */ #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) =20 -#ifdef CONFIG_DEBUG_TCG -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); -#else -static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->nip; - *cs_base =3D 0; - *flags =3D env->hflags; -} -#endif - G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception); G_NORETURN void raise_exception_ra(CPUPPCState *env, uint32_t exception, uintptr_t raddr); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9b0590c7d9..58ed6700de 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -627,9 +627,6 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, ta= rget_ulong vtype) return cpu->cfg.vlen >> (sew + 3 - lmul); } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - void riscv_cpu_update_mask(CPURISCVState *env); =20 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 3f5b501acf..33290e2c47 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -142,15 +142,6 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, = int rte); #define RX_CPU_IRQ 0 #define RX_CPU_FIR 1 =20 -static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); - *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); -} - static inline uint32_t rx_cpu_pack_psw(CPURXState *env) { uint32_t psw =3D 0; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 5c646cafaa..eeb10d10bd 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -348,28 +348,6 @@ extern const VMStateDescription vmstate_s390_cpu; #define MMU_HOME_IDX 2 #define MMU_REAL_IDX 3 =20 -static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - if (env->psw.addr & 1) { - /* - * Instructions must be at even addresses. - * This needs to be checked before address translation. - */ - env->int_pgm_ilen =3D 2; /* see s390_cpu_tlb_fill() */ - tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); - } - *pc =3D env->psw.addr; - *cs_base =3D env->ex_value; - *flags =3D (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; - if (env->cregs[0] & CR0_AFP) { - *flags |=3D FLAG_MASK_AFP; - } - if (env->cregs[0] & CR0_VECTOR) { - *flags |=3D FLAG_MASK_VECTOR; - } -} - /* PER bits from control register 9 */ #define PER_CR9_EVENT_BRANCH 0x80000000 #define PER_CR9_EVENT_IFETCH 0x40000000 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 218ba24333..818810769f 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -357,19 +357,4 @@ static inline void cpu_write_sr(CPUSH4State *env, targ= et_ulong sr) env->sr =3D sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); } =20 -static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - /* For a gUSA region, notice the end of the region. */ - *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; - *flags =3D env->flags - | (env->fpscr & TB_FLAG_FPSCR_MASK) - | (env->sr & TB_FLAG_SR_MASK) - | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ -#ifdef CONFIG_USER_ONLY - *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #endif /* SH4_CPU_H */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index bd24cd578c..33338f8846 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -733,41 +733,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_HYPER (1 << 7) #define TB_FLAG_ASI_SHIFT 24 =20 -static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - uint32_t flags; - *pc =3D env->pc; - *cs_base =3D env->npc; - flags =3D cpu_mmu_index(env, false); -#ifndef CONFIG_USER_ONLY - if (cpu_supervisor_mode(env)) { - flags |=3D TB_FLAG_SUPER; - } -#endif -#ifdef TARGET_SPARC64 -#ifndef CONFIG_USER_ONLY - if (cpu_hypervisor_mode(env)) { - flags |=3D TB_FLAG_HYPER; - } -#endif - if (env->pstate & PS_AM) { - flags |=3D TB_FLAG_AM_ENABLED; - } - if ((env->def.features & CPU_FEATURE_FLOAT) - && (env->pstate & PS_PEF) - && (env->fprs & FPRS_FEF)) { - flags |=3D TB_FLAG_FPU_ENABLED; - } - flags |=3D env->asi << TB_FLAG_ASI_SHIFT; -#else - if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) { - flags |=3D TB_FLAG_FPU_ENABLED; - } -#endif - *pflags =3D flags; -} - static inline bool tb_fpu_enabled(int tb_flags) { #if defined(CONFIG_USER_ONLY) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 9454b0adcd..43604f00ca 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -378,18 +378,6 @@ FIELD(TB_FLAGS, PRIV, 0, 2) void cpu_state_reset(CPUTriCoreState *s); void tricore_tcg_init(void); =20 -static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t new_flags =3D 0; - *pc =3D env->PC; - *cs_base =3D 0; - - new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, - extract32(env->PSW, 10, 2)); - *flags =3D new_flags; -} - #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU #define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 89d6b690af..0c51d2b0ec 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -721,74 +721,6 @@ static inline uint32_t xtensa_replicate_windowstart(CP= UXtensaState *env) =20 #include "exec/cpu-all.h" =20 -static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D 0; - *flags |=3D xtensa_get_ring(env); - if (env->sregs[PS] & PS_EXCM) { - *flags |=3D XTENSA_TBFLAG_EXCM; - } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { - target_ulong lend_dist =3D - env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); - - /* - * 0 in the csbase_lend field means that there may not be a loopba= ck - * for any instruction that starts inside this page. Any other val= ue - * means that an instruction that ends at this offset from the page - * start may loop back and will need loopback code to be generated. - * - * lend_dist is 0 when LEND points to the start of the page, but - * no instruction that starts inside this page may end at offset 0, - * so it's still correct. - * - * When an instruction ends at a page boundary it may only start in - * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE - * for the TB that contains this instruction. - */ - if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { - target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; - - *cs_base =3D lend_dist; - if (lbeg_off < 256) { - *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; - } - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && - (env->sregs[LITBASE] & 1)) { - *flags |=3D XTENSA_TBFLAG_LITBASE; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { - if (xtensa_get_cintlevel(env) < env->config->debug_level) { - *flags |=3D XTENSA_TBFLAG_DEBUG; - } - if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { - *flags |=3D XTENSA_TBFLAG_ICOUNT; - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { - *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && - (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { - uint32_t windowstart =3D xtensa_replicate_windowstart(env) >> - (env->sregs[WINDOW_BASE] + 1); - uint32_t w =3D ctz32(windowstart | 0x8); - - *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; - *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, - PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; - } else { - *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; - } - if (env->yield_needed) { - *flags |=3D XTENSA_TBFLAG_YIELD; - } -} - XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk); =20 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 2559ce38ee..5e468d4605 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -34,6 +34,17 @@ int cpu_mmu_index(CPUAlphaState *env, bool ifetch) return ret; } =20 +void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *pflags =3D env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void alpha_cpu_set_pc(CPUState *cs, vaddr value) { AlphaCPU *cpu =3D ALPHA_CPU(cs); diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 38263d07dd..351e127fea 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -31,6 +31,24 @@ int cpu_mmu_index(CPUAVRState *env, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } =20 +void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags =3D 0; + + *pc =3D env->pc_w * 2; + *cs_base =3D 0; + + if (env->fullacc) { + flags |=3D TB_FLAGS_FULL_ACCESS; + } + if (env->skip) { + flags |=3D TB_FLAGS_SKIP; + } + + *pflags =3D flags; +} + static void avr_cpu_set_pc(CPUState *cs, vaddr value) { AVRCPU *cpu =3D AVR_CPU(cs); diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 553742a068..8880e94a8e 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -32,6 +32,16 @@ int cpu_mmu_index(CPUCRISState *env, bool ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } =20 +void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D env->dslot | + (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG + | X_FLAG | PFIX_FLAG)); +} + static void cris_cpu_set_pc(CPUState *cs, vaddr value) { CRISCPU *cpu =3D CRIS_CPU(cs); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index bf7c901705..68b6e1a31f 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -35,6 +35,18 @@ int cpu_mmu_index(CPUHexagonState *env, bool ifetch) #endif } =20 +void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t hex_flags =3D 0; + *pc =3D env->gpr[HEX_REG_PC]; + *cs_base =3D 0; + if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); + } + *flags =3D hex_flags; +} + static void hexagon_v67_cpu_init(Object *obj) { } static void hexagon_v68_cpu_init(Object *obj) { } static void hexagon_v69_cpu_init(Object *obj) { } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 22f031758e..0103e0429b 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -40,6 +40,53 @@ int cpu_mmu_index(CPUHPPAState *env, bool ifetch) #endif } =20 +void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags =3D env->psw_n * PSW_N; + + /* + * TB lookup assumes that PC contains the complete virtual address. + * If we leave space+offset separate, we'll get ITLB misses to an + * incomplete virtual address. This also means that we must separate + * out current cpu privilege from the low bits of IAOQ_F. + */ +#ifdef CONFIG_USER_ONLY + *pc =3D env->iaoq_f & -4; + *cs_base =3D env->iaoq_b & -4; + flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#else + /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ + flags |=3D env->psw & (PSW_W | PSW_C | PSW_D); + flags |=3D (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; + + *pc =3D (env->psw & PSW_C + ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) + : env->iaoq_f & -4); + *cs_base =3D env->iasq_f; + + /* + * Insert a difference between IAOQ_B and IAOQ_F within the otherwise = zero + * low 32-bits of CS_BASE. This will succeed for all direct branches, + * which is the primary case we care about -- using goto_tb within a p= age. + * Failure is indicated by a zero difference. + */ + if (env->iasq_f =3D=3D env->iasq_b) { + target_sreg diff =3D env->iaoq_b - env->iaoq_f; + if (TARGET_REGISTER_BITS =3D=3D 32 || diff =3D=3D (int32_t)diff) { + *cs_base |=3D (uint32_t)diff; + } + } + if ((env->sr[4] =3D=3D env->sr[5]) + & (env->sr[4] =3D=3D env->sr[6]) + & (env->sr[4] =3D=3D env->sr[7])) { + flags |=3D TB_FLAG_SR_SAME; + } +#endif + + *pflags =3D flags; +} + static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { HPPACPU *cpu =3D HPPA_CPU(cs); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3327ecf6db..7baf74fb9a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -52,6 +52,15 @@ int cpu_mmu_index(CPUX86State *env, bool ifetch) ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; } =20 +void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *cs_base =3D env->segs[R_CS].base; + *pc =3D *cs_base + env->eip; + *flags =3D env->hflags | + (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); +} + static void x86_cpu_realizefn(DeviceState *dev, Error **errp); =20 /* Helpers for building CPUID[2] descriptors: */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index c6c2760e46..cc53a7e51a 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -32,6 +32,17 @@ int cpu_mmu_index(CPULoongArchState *env, bool ifetch) #endif } =20 +void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; + *flags |=3D is_va32(env) * HW_FLAGS_VA32; +} + const char * const regnames[32] =3D { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 74da87f07e..9c664cb9a8 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -29,6 +29,22 @@ int cpu_mmu_index(CPUM68KState *env, bool ifetch) return (env->sr & SR_S) =3D=3D 0 ? 1 : 0; } =20 +void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; + if (env->sr & SR_S) { + *flags |=3D TB_FLAGS_MSR_S; + *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; + *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; + } + if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { + *flags |=3D TB_FLAGS_TRACE; + } +} + static void m68k_cpu_set_pc(CPUState *cs, vaddr value) { M68kCPU *cpu =3D M68K_CPU(cs); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f8891de41e..4c270e941f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -47,6 +47,13 @@ int cpu_mmu_index(CPUMBState *env, bool ifetch) return MMU_KERNEL_IDX; } =20 +void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); + *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); +} =20 static const struct { const char *name; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 1b5994e9a7..fe93acf28f 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -49,6 +49,15 @@ int cpu_mmu_index(CPUMIPSState *env, bool ifetch) return hflags_mmu_index(env->hflags); } =20 +void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->active_tc.PC; + *cs_base =3D 0; + *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | + MIPS_HFLAG_HWRENA_ULR); +} + const char regnames[32][3] =3D { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 887a9bf786..868d75b165 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -32,6 +32,18 @@ int cpu_mmu_index(CPUNios2State *env, bool ifetch) MMU_SUPERVISOR_IDX; } =20 +void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + unsigned crs =3D FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS); + + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D (env->ctrl[CR_STATUS] & CR_STATUS_U) + | (crs ? 0 : R_TBFLAGS_CRS0_MASK) + | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK); +} + static void nios2_cpu_set_pc(CPUState *cs, vaddr value) { Nios2CPU *cpu =3D NIOS2_CPU(cs); diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 5938d66da3..36d97d249d 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -37,6 +37,16 @@ int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) return ret; } =20 +void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); +} + static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index 53f1d5c370..046732857b 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -36,6 +36,17 @@ int cpu_mmu_index(CPUPPCState *env, bool ifetch) #endif } =20 +/* debug version defined in helper_hregs */ +#ifndef CONFIG_DEBUG_TCG +void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->nip; + *cs_base =3D 0; + *flags =3D env->hflags; +} +#endif + target_ulong cpu_read_xer(const CPUPPCState *env) { if (is_isa300(env)) { diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 1ce1da0a6b..688a70b707 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -31,6 +31,15 @@ int cpu_mmu_index(CPURXState *env, bool ifetch) return 0; } =20 +void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); + *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); +} + static void rx_cpu_set_pc(CPUState *cs, vaddr value) { RXCPU *cpu =3D RX_CPU(cs); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index aa574807f1..51c707ea12 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -72,6 +72,30 @@ int cpu_mmu_index(CPUS390XState *env, bool ifetch) #endif } =20 +void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + if (env->psw.addr & 1) { + /* + * Instructions must be at even addresses. + * This needs to be checked before address translation. + */ + env->int_pgm_ilen =3D 2; /* see s390_cpu_tlb_fill() */ +#ifdef CONFIG_TCG + tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); +#endif + } + *pc =3D env->psw.addr; + *cs_base =3D env->ex_value; + *flags =3D (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; + if (env->cregs[0] & CR0_AFP) { + *flags |=3D FLAG_MASK_AFP; + } + if (env->cregs[0] & CR0_VECTOR) { + *flags |=3D FLAG_MASK_VECTOR; + } +} + #ifndef CONFIG_USER_ONLY static bool is_early_exception_psw(uint64_t mask, uint64_t addr) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 6bffe52c04..ea7f13612e 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -41,6 +41,21 @@ int cpu_mmu_index(CPUSH4State *env, bool ifetch) } } =20 +void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + /* For a gUSA region, notice the end of the region. */ + *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; + *flags =3D env->flags + | (env->fpscr & TB_FLAG_FPSCR_MASK) + | (env->sr & TB_FLAG_SR_MASK) + | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ +#ifdef CONFIG_USER_ONLY + *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void superh_cpu_set_pc(CPUState *cs, vaddr value) { SuperHCPU *cpu =3D SUPERH_CPU(cs); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 256ba2be88..a6af3fd9ee 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -57,6 +57,41 @@ int cpu_mmu_index(CPUSPARCState *env, bool ifetch) #endif } =20 +void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags; + *pc =3D env->pc; + *cs_base =3D env->npc; + flags =3D cpu_mmu_index(env, false); +#ifndef CONFIG_USER_ONLY + if (cpu_supervisor_mode(env)) { + flags |=3D TB_FLAG_SUPER; + } +#endif +#ifdef TARGET_SPARC64 +#ifndef CONFIG_USER_ONLY + if (cpu_hypervisor_mode(env)) { + flags |=3D TB_FLAG_HYPER; + } +#endif + if (env->pstate & PS_AM) { + flags |=3D TB_FLAG_AM_ENABLED; + } + if ((env->def.features & CPU_FEATURE_FLOAT) + && (env->pstate & PS_PEF) + && (env->fprs & FPRS_FEF)) { + flags |=3D TB_FLAG_FPU_ENABLED; + } + flags |=3D env->asi << TB_FLAG_ASI_SHIFT; +#else + if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) { + flags |=3D TB_FLAG_FPU_ENABLED; + } +#endif + *pflags =3D flags; +} + static void sparc_cpu_reset_hold(Object *obj) { CPUState *s =3D CPU(obj); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index a81f37e3e4..f8bf10569a 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -29,6 +29,18 @@ int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) return 0; } =20 +void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t new_flags =3D 0; + *pc =3D env->PC; + *cs_base =3D 0; + + new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, + extract32(env->PSW, 10, 2)); + *flags =3D new_flags; +} + static inline void set_feature(CPUTriCoreState *env, int feature) { env->features |=3D 1ULL << feature; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 769b3c9305..2c76ba86cd 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -44,6 +44,74 @@ int cpu_mmu_index(CPUXtensaState *env, bool ifetch) return xtensa_get_cring(env); } =20 +void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D 0; + *flags |=3D xtensa_get_ring(env); + if (env->sregs[PS] & PS_EXCM) { + *flags |=3D XTENSA_TBFLAG_EXCM; + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { + target_ulong lend_dist =3D + env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); + + /* + * 0 in the csbase_lend field means that there may not be a loopba= ck + * for any instruction that starts inside this page. Any other val= ue + * means that an instruction that ends at this offset from the page + * start may loop back and will need loopback code to be generated. + * + * lend_dist is 0 when LEND points to the start of the page, but + * no instruction that starts inside this page may end at offset 0, + * so it's still correct. + * + * When an instruction ends at a page boundary it may only start in + * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE + * for the TB that contains this instruction. + */ + if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { + target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; + + *cs_base =3D lend_dist; + if (lbeg_off < 256) { + *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; + } + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && + (env->sregs[LITBASE] & 1)) { + *flags |=3D XTENSA_TBFLAG_LITBASE; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { + if (xtensa_get_cintlevel(env) < env->config->debug_level) { + *flags |=3D XTENSA_TBFLAG_DEBUG; + } + if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { + *flags |=3D XTENSA_TBFLAG_ICOUNT; + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { + *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && + (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { + uint32_t windowstart =3D xtensa_replicate_windowstart(env) >> + (env->sregs[WINDOW_BASE] + 1); + uint32_t w =3D ctz32(windowstart | 0x8); + + *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; + *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, + PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; + } else { + *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; + } + if (env->yield_needed) { + *flags |=3D XTENSA_TBFLAG_YIELD; + } +} + static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) { XtensaCPU *cpu =3D XTENSA_CPU(cs); --=20 2.43.0