From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675297; cv=none; d=zohomail.com; s=zohoarc; b=i4vyQIR7R+jG/GxLUzvlGqIMKtlzQTYHzwF3EF5gDn9iozgEGOaLkxh8vBUZSiD1a9/SrRdZ3GmWDLbRJBxChFgQzI4g/dUHUdw78k0afyV1KbXE/9Ymro0ZIl2FpZNT8setYBlPfWe6kYDCeUOJu1y0fHdw5Q8D8dr9PfRYDso= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675297; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=0b7t76vK6gdZs+kbUmPzuyVEzX6X7fA1qtYiQNVWzGM=; b=aJ8Z+JR679eSpAFe5UeIFW8e4BF6rjCyO0AvABEfkWkWwmyKfrezY1eV9IuGvxQe0iJC1scaTsz0Jed4c8j2MedT/wj8825iLEKj9rf/Wk0lHM6UpzmWeH+1YSA1dwjxSN5AR2fUOWpvvGY8SfazhOtQ08w+v8wDaMRn7vLU0R0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705675297193246.9404096622427; Fri, 19 Jan 2024 06:41:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQq2q-0005oz-0x; Fri, 19 Jan 2024 09:40:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2h-0005mw-1h for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:24 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2b-0003I9-G7 for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=0b7t76vK6gdZs+kbUmPzuyVEzX6X7fA1qtYiQNVWzGM=; b=SFvA/LGkI8kYxFpzqP7C68XlSw Lph4Kcj4sZM9dUcsigWPQKcQflhLEAdk2htW9sC6uCrpIkQJ2gmVqHsXUiQwda8LyjLAeZhHBwy+2 apK8TzWmn4EO6m4t5IUalW1n4IOK+qOv55pkJwrnCA6BpThN7sjgQlvXvGKsiwu/HpHY=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 01/34] target: [PAGE_VARY] Use PAGE_VARY for all softmmu targets Date: Fri, 19 Jan 2024 15:39:51 +0100 Message-ID: <20240119144024.14289-2-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675298823100003 Content-Type: text/plain; charset="utf-8" Allows for future commits to use TargetPageBits to access page bits and mask, thus making TARGET_PAGE_* independent of softmmu target. In the future, this will also be important fo allowing heterogeneous CPUs on the same board. Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/cpu-param.h | 6 ++++++ target/avr/cpu-param.h | 6 ++++++ target/cris/cpu-param.h | 7 +++++++ target/hppa/cpu-param.h | 6 ++++++ target/i386/cpu-param.h | 6 ++++++ target/loongarch/cpu-param.h | 5 +++++ target/m68k/cpu-param.h | 6 ++++++ target/microblaze/cpu-param.h | 6 ++++-- target/nios2/cpu-param.h | 5 ++++- target/openrisc/cpu-param.h | 8 +++++++- target/ppc/cpu-param.h | 6 ++++++ target/riscv/cpu-param.h | 7 +++++++ target/rx/cpu-param.h | 8 +++++++- target/s390x/cpu-param.h | 8 +++++++- target/sh4/cpu-param.h | 4 +++- target/sparc/cpu-param.h | 17 +++++++++++++++-- target/tricore/cpu-param.h | 8 +++++++- target/xtensa/cpu-param.h | 8 +++++--- 18 files changed, 114 insertions(+), 13 deletions(-) diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index 68c46f7998..dc9da45bdf 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -9,7 +9,13 @@ #define ALPHA_CPU_PARAM_H =20 #define TARGET_LONG_BITS 64 + +#ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 13 +#else +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 13 +#endif =20 /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ #define TARGET_PHYS_ADDR_SPACE_BITS 44 diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 9a92bc74fc..87142069fe 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -28,7 +28,13 @@ * should be implemented as a device and not memory * 2. SRAM starts at the address 0x0100 */ +#ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 8 +#else +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 8 +#endif + #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 =20 diff --git a/target/cris/cpu-param.h b/target/cris/cpu-param.h index b31b742c0d..9c66ca9e66 100644 --- a/target/cris/cpu-param.h +++ b/target/cris/cpu-param.h @@ -9,7 +9,14 @@ #define CRIS_CPU_PARAM_H =20 #define TARGET_LONG_BITS 32 + +#ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 13 +#else +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 13 +#endif + #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index c2791ae5f2..781dbc17d3 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -28,6 +28,12 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 64 # define TARGET_PHYS_ADDR_SPACE_BITS 32 #endif + +#ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 +#else +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 12 +#endif =20 #endif diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index 911b4cd51b..d09d0eb2ed 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -22,6 +22,12 @@ # define TARGET_PHYS_ADDR_SPACE_BITS 36 # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif + +#ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 +#else +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 12 +#endif =20 #endif diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index 1265dc7cb5..f537c53ec4 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -12,6 +12,11 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 48 #define TARGET_VIRT_ADDR_SPACE_BITS 48 =20 +#ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 14 +#else +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 14 +#endif =20 #endif diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 39dcbcece8..92706969c7 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -14,7 +14,13 @@ * and m68k linux uses 4k pages * use the smallest one */ +#ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 +#else +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 12 +#endif + #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 9770b0eb52..51987d330d 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -20,13 +20,15 @@ #define TARGET_LONG_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 +/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ +#define TARGET_PAGE_BITS 12 #else #define TARGET_LONG_BITS 64 #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 12 #endif =20 -/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ -#define TARGET_PAGE_BITS 12 =20 #endif diff --git a/target/nios2/cpu-param.h b/target/nios2/cpu-param.h index 767bba4b7b..40af6aef68 100644 --- a/target/nios2/cpu-param.h +++ b/target/nios2/cpu-param.h @@ -9,12 +9,15 @@ #define NIOS2_CPU_PARAM_H =20 #define TARGET_LONG_BITS 32 -#define TARGET_PAGE_BITS 12 + #define TARGET_PHYS_ADDR_SPACE_BITS 32 #ifdef CONFIG_USER_ONLY # define TARGET_VIRT_ADDR_SPACE_BITS 31 +# define TARGET_PAGE_BITS 12 #else # define TARGET_VIRT_ADDR_SPACE_BITS 32 +# define TARGET_PAGE_BITS_VARY +# define TARGET_PAGE_BITS_MIN 12 #endif =20 #endif diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index 3f08207485..10c52edf76 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -9,8 +9,14 @@ #define OPENRISC_CPU_PARAM_H =20 #define TARGET_LONG_BITS 32 -#define TARGET_PAGE_BITS 13 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#ifdef CONFIG_USER_ONLY +#define TARGET_PAGE_BITS 13 +#else +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 13 +#endif + #endif diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index 0a0416e0a8..597dd39a6b 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -31,6 +31,12 @@ # define TARGET_PHYS_ADDR_SPACE_BITS 36 # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif + +#ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 +#else +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 12 +#endif =20 #endif diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index b2a9396dec..80ba169e2b 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -17,7 +17,14 @@ # define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ #endif + +#ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ +#else +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 12 /* 4 KiB Pages */ +#endif + /* * The current MMU Modes are: * - U mode 0b000 diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index 521d669bdf..f05a28456a 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -20,9 +20,15 @@ #define RX_CPU_PARAM_H =20 #define TARGET_LONG_BITS 32 -#define TARGET_PAGE_BITS 12 =20 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#ifdef CONFIG_USER_ONLY +#define TARGET_PAGE_BITS 12 +#else +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 12 +#endif + #endif diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index 84ca08626b..23d4345812 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -9,8 +9,14 @@ #define S390_CPU_PARAM_H =20 #define TARGET_LONG_BITS 64 -#define TARGET_PAGE_BITS 12 #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 =20 +#ifdef CONFIG_USER_ONLY +#define TARGET_PAGE_BITS 12 +#else +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 12 +#endif + #endif diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index a7cdb7edb6..03354f1342 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -9,12 +9,14 @@ #define SH4_CPU_PARAM_H =20 #define TARGET_LONG_BITS 32 -#define TARGET_PAGE_BITS 12 /* 4k */ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #ifdef CONFIG_USER_ONLY # define TARGET_VIRT_ADDR_SPACE_BITS 31 +# define TARGET_PAGE_BITS 12 /* 4k */ #else # define TARGET_VIRT_ADDR_SPACE_BITS 32 +# define TARGET_PAGE_BITS_VARY +# define TARGET_PAGE_BITS_MIN 12 /* 4k */ #endif =20 #endif diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index cb11980404..19b53ebea6 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -9,7 +9,6 @@ =20 #ifdef TARGET_SPARC64 # define TARGET_LONG_BITS 64 -# define TARGET_PAGE_BITS 13 /* 8k */ # define TARGET_PHYS_ADDR_SPACE_BITS 41 # ifdef TARGET_ABI32 # define TARGET_VIRT_ADDR_SPACE_BITS 32 @@ -18,9 +17,23 @@ # endif #else # define TARGET_LONG_BITS 32 -# define TARGET_PAGE_BITS 12 /* 4k */ # define TARGET_PHYS_ADDR_SPACE_BITS 36 # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 +#ifdef CONFIG_USER_ONLY +# ifdef TARGET_SPARC64 +# define TARGET_PAGE_BITS 13 /* 8k */ +# else +# define TARGET_PAGE_BITS 12 /* 4k */ +# endif +#else +# define TARGET_PAGE_BITS_VARY +# ifdef TARGET_SPARC64 +# define TARGET_PAGE_BITS_MIN 13 /* 8k */ +# else +# define TARGET_PAGE_BITS_MIN 12 /* 4k */ +# endif +#endif + #endif diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index e29d551dd6..6eff65ac54 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -9,8 +9,14 @@ #define TRICORE_CPU_PARAM_H =20 #define TARGET_LONG_BITS 32 -#define TARGET_PAGE_BITS 14 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#ifdef CONFIG_USER_ONLY +# define TARGET_PAGE_BITS 14 +#else +# define TARGET_PAGE_BITS_VARY +# define TARGET_PAGE_BITS_MIN 14 +#endif + #endif diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index b1da0555de..1c18855626 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -9,12 +9,14 @@ #define XTENSA_CPU_PARAM_H =20 #define TARGET_LONG_BITS 32 -#define TARGET_PAGE_BITS 12 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #ifdef CONFIG_USER_ONLY -#define TARGET_VIRT_ADDR_SPACE_BITS 30 +# define TARGET_VIRT_ADDR_SPACE_BITS 30 +# define TARGET_PAGE_BITS 12 #else -#define TARGET_VIRT_ADDR_SPACE_BITS 32 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +# define TARGET_PAGE_BITS_VARY +# define TARGET_PAGE_BITS_MIN 12 #endif =20 #endif --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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(zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675415284100003 Content-Type: text/plain; charset="utf-8" TARGET_PAGE_BITS_MIN is now defined as target_page.bits_min when PAGE_VARY is used, similar to other TARGET_PAGE_* macros. We still pick whatever minimum the target specifies, however in a heterogeneous context we would want the maximum of all target_page.bits_min. This also makes TLB_* macros target independent, and the static assert checking for TLB_* flag overlap is moved to a runtime assert in tlb_init(). [NOTE: I'm not happy with adding the TARGET_PAGE_BITS_MIN_SPECIFIC macro, maybe we can remove it and use MachineClass->minimum_page_bits instead? Other ideas?] Signed-off-by: Anton Johansson --- include/exec/cpu-all.h | 10 +++++----- include/exec/cpu-defs.h | 4 ++-- include/exec/page-vary.h | 1 + target/alpha/cpu-param.h | 2 +- target/arm/cpu-param.h | 2 +- target/avr/cpu-param.h | 2 +- target/cris/cpu-param.h | 2 +- target/hppa/cpu-param.h | 2 +- target/i386/cpu-param.h | 2 +- target/loongarch/cpu-param.h | 2 +- target/m68k/cpu-param.h | 2 +- target/microblaze/cpu-param.h | 2 +- target/mips/cpu-param.h | 2 +- target/nios2/cpu-param.h | 2 +- target/openrisc/cpu-param.h | 2 +- target/ppc/cpu-param.h | 2 +- target/riscv/cpu-param.h | 2 +- target/rx/cpu-param.h | 2 +- target/s390x/cpu-param.h | 2 +- target/sh4/cpu-param.h | 2 +- target/sparc/cpu-param.h | 4 ++-- target/tricore/cpu-param.h | 2 +- target/xtensa/cpu-param.h | 2 +- accel/tcg/cputlb.c | 3 +++ page-vary-common.c | 1 + page-vary-target.c | 4 ++-- target/arm/tcg/translate.c | 4 ++-- 27 files changed, 37 insertions(+), 32 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 5340907cfd..a1e4dee6a2 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -155,12 +155,15 @@ static inline void stl_phys_notdirty(AddressSpace *as= , hwaddr addr, uint32_t val # include "exec/page-vary.h" extern const TargetPageBits target_page; #ifdef CONFIG_DEBUG_TCG +#define TARGET_PAGE_BITS_MIN ({ assert(target_page.decided); \ + target_page.bits_min; }) #define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bit= s; }) #define TARGET_PAGE_MASK ({ assert(target_page.decided); \ (target_long)target_page.mask; }) #else -#define TARGET_PAGE_BITS target_page.bits -#define TARGET_PAGE_MASK ((target_long)target_page.mask) +#define TARGET_PAGE_BITS_MIN target_page.bits_min +#define TARGET_PAGE_BITS target_page.bits +#define TARGET_PAGE_MASK ((target_long)target_page.mask) #endif #define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) #else @@ -380,9 +383,6 @@ CPUArchState *cpu_copy(CPUArchState *env); =20 #define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT) =20 -/* The two sets of flags must not overlap. */ -QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); - /** * tlb_hit_page: return true if page aligned @addr is a hit against the * TLB entry @tlb_addr diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 3915438b83..e8ccbe4bef 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -44,8 +44,8 @@ #endif #ifndef TARGET_PAGE_BITS # ifdef TARGET_PAGE_BITS_VARY -# ifndef TARGET_PAGE_BITS_MIN -# error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h +# ifndef TARGET_PAGE_BITS_MIN_SPECIFIC +# error TARGET_PAGE_BITS_MIN_SPECIFIC must be defined in cpu-param.h # endif # else # error TARGET_PAGE_BITS must be defined in cpu-param.h diff --git a/include/exec/page-vary.h b/include/exec/page-vary.h index 54ddde308a..add1282a7c 100644 --- a/include/exec/page-vary.h +++ b/include/exec/page-vary.h @@ -22,6 +22,7 @@ =20 typedef struct { bool decided; + int bits_min; int bits; uint64_t mask; } TargetPageBits; diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index dc9da45bdf..7001b130d6 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -14,7 +14,7 @@ #define TARGET_PAGE_BITS 13 #else #define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 13 +#define TARGET_PAGE_BITS_MIN_SPECIFIC 13 #endif =20 /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index f9b462a98f..442feb5380 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -29,7 +29,7 @@ * have to support 1K tiny pages. */ # define TARGET_PAGE_BITS_VARY -# define TARGET_PAGE_BITS_MIN 10 +# define TARGET_PAGE_BITS_MIN_SPECIFIC 10 =20 #endif =20 diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 87142069fe..e9b011a50d 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -32,7 +32,7 @@ #define TARGET_PAGE_BITS 8 #else #define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 8 +#define TARGET_PAGE_BITS_MIN_SPECIFIC 8 #endif =20 #define TARGET_PHYS_ADDR_SPACE_BITS 24 diff --git a/target/cris/cpu-param.h b/target/cris/cpu-param.h index 9c66ca9e66..2c939a2beb 100644 --- a/target/cris/cpu-param.h +++ b/target/cris/cpu-param.h @@ -14,7 +14,7 @@ #define TARGET_PAGE_BITS 13 #else #define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 13 +#define TARGET_PAGE_BITS_MIN_SPECIFIC 13 #endif =20 #define TARGET_PHYS_ADDR_SPACE_BITS 32 diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 781dbc17d3..5e413b7b76 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -33,7 +33,7 @@ #define TARGET_PAGE_BITS 12 #else #define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 12 +#define TARGET_PAGE_BITS_MIN_SPECIFIC 12 #endif =20 #endif diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index d09d0eb2ed..a497e842d8 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -27,7 +27,7 @@ #define TARGET_PAGE_BITS 12 #else #define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 12 +#define TARGET_PAGE_BITS_MIN_SPECIFIC 12 #endif =20 #endif diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index f537c53ec4..a447a03a76 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -16,7 +16,7 @@ #define TARGET_PAGE_BITS 14 #else #define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 14 +#define TARGET_PAGE_BITS_MIN_SPECIFIC 14 #endif =20 #endif diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 92706969c7..650a1f94c7 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -18,7 +18,7 @@ #define TARGET_PAGE_BITS 12 #else #define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 12 +#define TARGET_PAGE_BITS_MIN_SPECIFIC 12 #endif =20 #define TARGET_PHYS_ADDR_SPACE_BITS 32 diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 51987d330d..4bfd825999 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -27,7 +27,7 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 #define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 12 +#define TARGET_PAGE_BITS_MIN_SPECIFIC 12 #endif =20 =20 diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 594c91a156..1f4fb03b66 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -27,7 +27,7 @@ #define TARGET_PAGE_BITS 12 #else #define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 12 +#define TARGET_PAGE_BITS_MIN_SPECIFIC 12 #endif =20 #endif diff --git a/target/nios2/cpu-param.h b/target/nios2/cpu-param.h index 40af6aef68..759c89abea 100644 --- a/target/nios2/cpu-param.h +++ b/target/nios2/cpu-param.h @@ -17,7 +17,7 @@ #else # define TARGET_VIRT_ADDR_SPACE_BITS 32 # define TARGET_PAGE_BITS_VARY -# define TARGET_PAGE_BITS_MIN 12 +# define TARGET_PAGE_BITS_MIN_SPECIFIC 12 #endif =20 #endif diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index 10c52edf76..b20dbd7c8b 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -16,7 +16,7 @@ #define TARGET_PAGE_BITS 13 #else #define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 13 +#define TARGET_PAGE_BITS_MIN_SPECIFIC 13 #endif =20 #endif diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index 597dd39a6b..c712131b5d 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -36,7 +36,7 @@ #define TARGET_PAGE_BITS 12 #else #define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 12 +#define TARGET_PAGE_BITS_MIN_SPECIFIC 12 #endif =20 #endif diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index 80ba169e2b..889d2b14fe 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -22,7 +22,7 @@ #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ #else #define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 12 /* 4 KiB Pages */ +#define TARGET_PAGE_BITS_MIN_SPECIFIC 12 /* 4 KiB Pages */ #endif =20 /* diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index f05a28456a..5b5fb658e6 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -28,7 +28,7 @@ #define TARGET_PAGE_BITS 12 #else #define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 12 +#define TARGET_PAGE_BITS_MIN_SPECIFIC 12 #endif =20 #endif diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index 23d4345812..b8a9cf96b4 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -16,7 +16,7 @@ #define TARGET_PAGE_BITS 12 #else #define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 12 +#define TARGET_PAGE_BITS_MIN_SPECIFIC 12 #endif =20 #endif diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index 03354f1342..42c747c333 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -16,7 +16,7 @@ #else # define TARGET_VIRT_ADDR_SPACE_BITS 32 # define TARGET_PAGE_BITS_VARY -# define TARGET_PAGE_BITS_MIN 12 /* 4k */ +# define TARGET_PAGE_BITS_MIN_SPECIFIC 12 /* 4k */ #endif =20 #endif diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index 19b53ebea6..538a8db77a 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -30,9 +30,9 @@ #else # define TARGET_PAGE_BITS_VARY # ifdef TARGET_SPARC64 -# define TARGET_PAGE_BITS_MIN 13 /* 8k */ +# define TARGET_PAGE_BITS_MIN_SPECIFIC 13 /* 8k */ # else -# define TARGET_PAGE_BITS_MIN 12 /* 4k */ +# define TARGET_PAGE_BITS_MIN_SPECIFIC 12 /* 4k */ # endif #endif =20 diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index 6eff65ac54..bddfb57530 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -16,7 +16,7 @@ # define TARGET_PAGE_BITS 14 #else # define TARGET_PAGE_BITS_VARY -# define TARGET_PAGE_BITS_MIN 14 +# define TARGET_PAGE_BITS_MIN_SPECIFIC 14 #endif =20 #endif diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index 1c18855626..9689581e3b 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -16,7 +16,7 @@ #else # define TARGET_VIRT_ADDR_SPACE_BITS 32 # define TARGET_PAGE_BITS_VARY -# define TARGET_PAGE_BITS_MIN 12 +# define TARGET_PAGE_BITS_MIN_SPECIFIC 12 #endif =20 #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b8c5e345b8..449c86301e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -278,6 +278,9 @@ void tlb_init(CPUState *cpu) int64_t now =3D get_clock_realtime(); int i; =20 + /* The two sets of flags must not overlap. */ + assert((TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK) =3D=3D 0); + qemu_spin_init(&cpu->neg.tlb.c.lock); =20 /* All tlbs are initialized flushed. */ diff --git a/page-vary-common.c b/page-vary-common.c index ab77672dd4..ecd4e30c94 100644 --- a/page-vary-common.c +++ b/page-vary-common.c @@ -48,6 +48,7 @@ void finalize_target_page_bits_common(int min) if (target_page.bits =3D=3D 0) { target_page.bits =3D min; } + target_page.bits_min =3D min; target_page.mask =3D -1ull << target_page.bits; target_page.decided =3D true; } diff --git a/page-vary-target.c b/page-vary-target.c index 343b4adb95..87dae60d5e 100644 --- a/page-vary-target.c +++ b/page-vary-target.c @@ -26,7 +26,7 @@ bool set_preferred_target_page_bits(int bits) { #ifdef TARGET_PAGE_BITS_VARY - assert(bits >=3D TARGET_PAGE_BITS_MIN); + assert(bits >=3D TARGET_PAGE_BITS_MIN_SPECIFIC); return set_preferred_target_page_bits_common(bits); #else return true; @@ -36,6 +36,6 @@ bool set_preferred_target_page_bits(int bits) void finalize_target_page_bits(void) { #ifdef TARGET_PAGE_BITS_VARY - finalize_target_page_bits_common(TARGET_PAGE_BITS_MIN); + finalize_target_page_bits_common(TARGET_PAGE_BITS_MIN_SPECIFIC); #endif } diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 48927fbb8c..bdcb8a6555 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -902,8 +902,8 @@ MemOp pow2_align(unsigned i) static const MemOp mop_align[] =3D { 0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16, /* - * FIXME: TARGET_PAGE_BITS_MIN affects TLB_FLAGS_MASK such - * that 256-bit alignment (MO_ALIGN_32) cannot be supported: + * FIXME: TARGET_PAGE_BITS_MIN_SPECIFIC affects TLB_FLAGS_MASK + * such that 256-bit alignment (MO_ALIGN_32) cannot be supported: * see get_alignment_bits(). Enforce only 128-bit alignment for no= w. */ MO_ALIGN_16 --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675366; cv=none; d=zohomail.com; s=zohoarc; b=ElCrP6mH9N8NI+fSg8fWefVCFGTV3mTLYYC/k2qnT+LDgC21cOOJI0MHUKa7csc93sq4jtlx3tVptrH59FaCNBhPKkEkZhkf27loNTZKiH6ADklOP0+XvSJmHbPnTO5ztvFgem/aapbpXg4dqq3QMNgc7SkNuclNdtA8VjlcRrY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675366; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=0CWT5ojr77Q9zixDwJBU6wGjiRCwORiOck1FGfPbW1Y=; b=JLJthzQxPyZ2AsguVPmz8LzDWCPeGug8pJx3YpiVOkQzxRkTL73rFLFe8v+4MoSwM6KfoWUJwgaMgBIpfsutGuLlG73AnsDrhYvX/T3+vxFmJMJNY5NGM5PRt+Ay8zymRQGl3qVZI9LKC2TugmrR2H0ndrwOXP03SI3UuP0z9X4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17056753664021010.7312417926325; Fri, 19 Jan 2024 06:42:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQq33-0005xL-V0; Fri, 19 Jan 2024 09:40:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2h-0005mz-34 for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:24 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2b-0003Sj-GP for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=0CWT5ojr77Q9zixDwJBU6wGjiRCwORiOck1FGfPbW1Y=; b=OVlUSVoxOxK3Z0TL40W0u8xHZD qvEFTrnRYfJSEC1AiNr97BQypr9QRJaDsW7Fy4CMwkTgWT2ed5G4nLtbqSUZBKl7/sxxKb3GakMkt qjiiTnCVi94JFutnz6LYFK6s3YjZuRxmE4MrFyvEgthUn1cEkBTnbEhQQ11JSwWvrq4Y=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 03/34] exec: [PAGE_VARY] Move TARGET_PAGE_BITS_VARY to common header Date: Fri, 19 Jan 2024 15:39:53 +0100 Message-ID: <20240119144024.14289-4-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675367128100009 Content-Type: text/plain; charset="utf-8" We need to be able access the variable TARGET_PAGE_* macros in a target-independent manner. Signed-off-by: Anton Johansson --- include/exec/cpu-all.h | 29 ++++++++++------------------- include/exec/cpu-common.h | 25 +++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 19 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index a1e4dee6a2..83165b1ce4 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -149,30 +149,21 @@ static inline void stl_phys_notdirty(AddressSpace *as= , hwaddr addr, uint32_t val #include "exec/memory_ldst_phys.h.inc" #endif =20 -/* page related stuff */ - -#ifdef TARGET_PAGE_BITS_VARY -# include "exec/page-vary.h" -extern const TargetPageBits target_page; -#ifdef CONFIG_DEBUG_TCG -#define TARGET_PAGE_BITS_MIN ({ assert(target_page.decided); \ - target_page.bits_min; }) -#define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bit= s; }) -#define TARGET_PAGE_MASK ({ assert(target_page.decided); \ - (target_long)target_page.mask; }) -#else -#define TARGET_PAGE_BITS_MIN target_page.bits_min -#define TARGET_PAGE_BITS target_page.bits -#define TARGET_PAGE_MASK ((target_long)target_page.mask) -#endif -#define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) -#else +/* Non-variable page size macros */ +#ifndef TARGET_PAGE_BITS_VARY #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) #define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS) +#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) #endif =20 -#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) +/* + * Check that softmmu targets are using variable page sizes, we need this + * for the TARGET_PAGE_* macros to be target independent. + */ +#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_PAGE_BITS_VARY) +# error Need to use TARGET_PAGE_BITS_VARY on system mode +#endif =20 /* same as PROT_xxx */ #define PAGE_READ 0x0001 diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 605b160a7e..df53252d51 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -26,6 +26,31 @@ typedef uint64_t vaddr; #define VADDR_PRIX PRIX64 #define VADDR_MAX UINT64_MAX =20 +/** + * Variable page size macros + * + * TARGET_PAGE_BITS_VARY is assumed for softmmu targets so + * these macros are target independent. This is checked in + * cpu-all.h. + */ +#ifndef CONFIG_USER_ONLY +# include "exec/page-vary.h" +extern const TargetPageBits target_page; +#ifdef CONFIG_DEBUG_TCG +#define TARGET_PAGE_BITS_MIN ({ assert(target_page.decided); \ + target_page.bits_min; }) +#define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bit= s; }) +#define TARGET_PAGE_MASK ({ assert(target_page.decided); \ + (int)target_page.mask; }) +#else +#define TARGET_PAGE_BITS_MIN target_page.bits_min +#define TARGET_PAGE_BITS target_page.bits +#define TARGET_PAGE_MASK ((int)target_page.mask) +#endif +#define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) +#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) +#endif + void cpu_exec_init_all(void); void cpu_exec_step_atomic(CPUState *cpu); =20 --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705675537684869.6180210008234; Fri, 19 Jan 2024 06:45:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQq2y-0005t8-HV; Fri, 19 Jan 2024 09:40:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2f-0005mU-1I for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:22 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2b-0003Sq-K0 for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=bGElSCUlpgiXi9G6rlQ4CqjB/wCRk8+IhyTwx+6S/MQ=; b=grwOX/lE+ffToN3IjaUdqQm2iG R8c3tBQ5vC5ty0ptbVtUhuaJz36DfZSEg4rxKXM/7OLHBgOXp00zG/+7t9OTJ8t8V1h0UcB7DbYw+ ab0y3tDw+2S5o7pRn+mZGfMxNZH7ccDETNAe9PelZ60yfO1vq+lRxdZ8/P05Z8PHMKE8=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 04/34] exec: [PAGE_VARY] Unpoison TARGET_PAGE_* macros for system mode Date: Fri, 19 Jan 2024 15:39:54 +0100 Message-ID: <20240119144024.14289-5-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675537929100005 Content-Type: text/plain; charset="utf-8" TARGET_PAGE_* are now target-independent for softmmu targets, and can safely be accessed common code. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- include/exec/poison.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/exec/poison.h b/include/exec/poison.h index 1ea5633eb3..6d87954a91 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -46,10 +46,12 @@ #pragma GCC poison TARGET_FMT_ld #pragma GCC poison TARGET_FMT_lu =20 +#ifdef CONFIG_USER_ONLY #pragma GCC poison TARGET_PAGE_SIZE #pragma GCC poison TARGET_PAGE_MASK #pragma GCC poison TARGET_PAGE_BITS #pragma GCC poison TARGET_PAGE_ALIGN +#endif =20 #pragma GCC poison CPU_INTERRUPT_HARD #pragma GCC poison CPU_INTERRUPT_EXITTB --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675264; cv=none; d=zohomail.com; s=zohoarc; b=SZ+LUPxRww5NwE/MqdSuzUT1K7Y5dV8+uF0GGi8HqI69V75GJAfBFJnXekzuT8vf4ixAWrCplMrP5uh8M7Fwzz1u/t8hs3OwvC0Pe8/KmG/LK02rIviy94n7Y3tLrwDui/ehGcLtT1Wa2IsoRPwiQicq9iedmjT+qghqiXGXAXA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675264; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=HGHmcwrFsDedpDfs3+LaapRdnSkQbjFoJJJVWFRxpII=; b=aG+U83vRNR6ACAYTrh2hv9YftKkBrEBP1pUXHFoveaCdqjklXW3d0St4ILzUCGUP/Lr6ZMOoOuOP9jgW2Wp8w3MzzGyyFH70/SbODVzgf6pqdAbum5RUsLIFdandjzJiR1pAdjK7fdWZgYcIJc7rA5YHbCcDvbiKLF1z08guRwg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705675263891286.988032201136; Fri, 19 Jan 2024 06:41:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQq2e-0005mN-VU; Fri, 19 Jan 2024 09:40:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2d-0005m3-Nn for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:19 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2b-0003TG-Dr for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=HGHmcwrFsDedpDfs3+LaapRdnSkQbjFoJJJVWFRxpII=; b=a9ZpVltxm+1/D5ON2xjzmtkekB EMaTOu+5+RvJ+5bgNesO0WP54KIIzxLh6VdwdDK+0p0CAuFEDsM5gUcBeO0JaX6S2EqZdv9t5iXom Eg2fsWf+3L8fgKTQ0tCIMYRYtBMRjLQ6VodYUXKxnL+oKScTzoQfbv6JOAq/K7xSJDgI=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 05/34] target/tricore: [VADDR] Use target_ulong for EA Date: Fri, 19 Jan 2024 15:39:55 +0100 Message-ID: <20240119144024.14289-6-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675264666100001 Content-Type: text/plain; charset="utf-8" Prepares target for typedef'ing abi_ptr to vaddr. Fixes sign extension bug that would result from abi_ptr being unsigned in the future. Necessary to make memory access function signatures target agnostic. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- target/tricore/op_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 89be1ed648..f57bb39d1f 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -2395,7 +2395,7 @@ static bool cdc_zero(target_ulong *psw) return count =3D=3D 0; } =20 -static void save_context_upper(CPUTriCoreState *env, int ea) +static void save_context_upper(CPUTriCoreState *env, target_ulong ea) { cpu_stl_data(env, ea, env->PCXI); cpu_stl_data(env, ea+4, psw_read(env)); @@ -2415,7 +2415,7 @@ static void save_context_upper(CPUTriCoreState *env, = int ea) cpu_stl_data(env, ea+60, env->gpr_d[15]); } =20 -static void save_context_lower(CPUTriCoreState *env, int ea) +static void save_context_lower(CPUTriCoreState *env, target_ulong ea) { cpu_stl_data(env, ea, env->PCXI); cpu_stl_data(env, ea+4, env->gpr_a[11]); @@ -2435,7 +2435,7 @@ static void save_context_lower(CPUTriCoreState *env, = int ea) cpu_stl_data(env, ea+60, env->gpr_d[7]); } =20 -static void restore_context_upper(CPUTriCoreState *env, int ea, +static void restore_context_upper(CPUTriCoreState *env, target_ulong ea, target_ulong *new_PCXI, target_ulong *ne= w_PSW) { *new_PCXI =3D cpu_ldl_data(env, ea); @@ -2456,7 +2456,7 @@ static void restore_context_upper(CPUTriCoreState *en= v, int ea, env->gpr_d[15] =3D cpu_ldl_data(env, ea+60); } =20 -static void restore_context_lower(CPUTriCoreState *env, int ea, +static void restore_context_lower(CPUTriCoreState *env, target_ulong ea, target_ulong *ra, target_ulong *pcxi) { *pcxi =3D cpu_ldl_data(env, ea); --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675394; cv=none; d=zohomail.com; s=zohoarc; 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Fri, 19 Jan 2024 06:43:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQq2v-0005qA-TL; Fri, 19 Jan 2024 09:40:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2e-0005mQ-P3 for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:20 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2b-0003TL-Gq for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=qXOq/h6phsa/tEESVpy5xNTXbPzc//D/ihwH2veRNU8=; b=EWahrOkuQ1I7Hi3RtRzClONnGs hFDhsMo4OCCj9XR8NNDfTG+RiTFtaFnwtvocWFUv1LMWxpNcmDeHnhwIVl3T56jBYV2hSZKhLxeEF aOlVTHILN0E2PhwVB0saFt/Y7pNekvmq6CpaVWm+BK8Vg5+quAUPjnf+y9gjJ5grcHtE=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 06/34] exec: [VADDR] Move vaddr defines to separate file Date: Fri, 19 Jan 2024 15:39:56 +0100 Message-ID: <20240119144024.14289-7-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675395127100001 Content-Type: text/plain; charset="utf-8" Needed to work around circular includes. vaddr is currently defined in cpu-common.h and needed by hw/core/cpu.h, but cpu-common.h also need cpu.h to know the size of the CPUState. [Maybe we can instead move parts of cpu-common.h w. hw/core/cpu.h to sort out the circular inclusion.] Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- include/exec/cpu-common.h | 12 ------------ include/exec/vaddr.h | 18 ++++++++++++++++++ 2 files changed, 18 insertions(+), 12 deletions(-) create mode 100644 include/exec/vaddr.h diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index df53252d51..c071f1a003 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -14,18 +14,6 @@ #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another= */ #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ =20 -/** - * vaddr: - * Type wide enough to contain any #target_ulong virtual address. - */ -typedef uint64_t vaddr; -#define VADDR_PRId PRId64 -#define VADDR_PRIu PRIu64 -#define VADDR_PRIo PRIo64 -#define VADDR_PRIx PRIx64 -#define VADDR_PRIX PRIX64 -#define VADDR_MAX UINT64_MAX - /** * Variable page size macros * diff --git a/include/exec/vaddr.h b/include/exec/vaddr.h new file mode 100644 index 0000000000..db48bb16bc --- /dev/null +++ b/include/exec/vaddr.h @@ -0,0 +1,18 @@ +/* Define vaddr if it exists. */ + +#ifndef VADDR_H +#define VADDR_H + +/** + * vaddr: + * Type wide enough to contain any #target_ulong virtual address. + */ +typedef uint64_t vaddr; +#define VADDR_PRId PRId64 +#define VADDR_PRIu PRIu64 +#define VADDR_PRIo PRIo64 +#define VADDR_PRIx PRIx64 +#define VADDR_PRIX PRIX64 +#define VADDR_MAX UINT64_MAX + +#endif --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675404; cv=none; d=zohomail.com; s=zohoarc; b=lPddD0hPsJC7KtVsFig7RCyVJfGxuRTByGCOm6EAZoJUqhyQ7czqfohftCRw2/6mk92+S7LPIAsvBZRURyN1DLkcjvB+cU10S2qxFmPJPAPQpABEgyE7IajmrYrhQm2xCvwcRx9YvNmDA01kttOsXgZ2mjDy8vA6ufr06J/Calc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675404; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Fri, 19 Jan 2024 09:40:19 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2b-0003WE-GG for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=hxBMwD1GCaiuF899/iFCMKGKTUOtgix0iEaqjEpTw1E=; b=Eb97r8ZhNvzpzZQSvs7DsXTwPH HhCfnrYpAWZAvddYDNth0wLzHHSNdaJEPIF0Y5kgQU7h7eUms7oi+3xWmfjcBQQcYJR9As1NGLsHT Af++NltcGRR/AR7laH1aJt+YEVAw8YKeqX2kjINj8smZSIWHa5WEeCt2UcJ5Hf4gkubw=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 07/34] hw/core: [VADDR] Include vaddr.h from cpu.h Date: Fri, 19 Jan 2024 15:39:57 +0100 Message-ID: <20240119144024.14289-8-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675405167100005 Content-Type: text/plain; charset="utf-8" cpu-common.h is only needed for vaddr Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index f25d53ee90..57d100c203 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -22,8 +22,8 @@ =20 #include "hw/qdev-core.h" #include "disas/dis-asm.h" -#include "exec/cpu-common.h" #include "exec/hwaddr.h" +#include "exec/vaddr.h" #include "exec/memattrs.h" #include "exec/tlb-common.h" #include "qapi/qapi-types-run-state.h" --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=G5Bw0OiXVj933CF1Eo5sz9jzaJ/fZkwsa8JFV6dXuEY=; b=NvncDpb4+/gZSTAzZ2oUZUy32U W+74mn0SqDIQfOqRAYFjWnQW1ETFpCGbzmAjVGEFYD4EP6aee+e5P1qrbOiRF7fheCo+HAk+NvXw4 HiULYd8cbnwAV2PL9k+QioD1+Xpx/2KKAKDpabgh/4dc/XW6SYa+qxBz3x0J6bMwZduo=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 08/34] target: [VADDR] Use vaddr in gen_intermediate_code Date: Fri, 19 Jan 2024 15:39:58 +0100 Message-ID: <20240119144024.14289-9-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675405197100006 Content-Type: text/plain; charset="utf-8" Makes gen_intermediate_code() signature target agnostic so the function can be called from accel/tcg/translate-all.c without target specifics. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- include/exec/translator.h | 2 +- target/alpha/translate.c | 2 +- target/arm/tcg/translate.c | 2 +- target/avr/translate.c | 2 +- target/cris/translate.c | 2 +- target/hexagon/translate.c | 2 +- target/hppa/translate.c | 2 +- target/i386/tcg/translate.c | 2 +- target/loongarch/translate.c | 2 +- target/m68k/translate.c | 2 +- target/microblaze/translate.c | 2 +- target/mips/tcg/translate.c | 2 +- target/nios2/translate.c | 2 +- target/openrisc/translate.c | 2 +- target/ppc/translate.c | 2 +- target/riscv/translate.c | 2 +- target/rx/translate.c | 2 +- target/s390x/tcg/translate.c | 2 +- target/sh4/translate.c | 2 +- target/sparc/translate.c | 2 +- target/tricore/translate.c | 2 +- target/xtensa/translate.c | 2 +- 22 files changed, 22 insertions(+), 22 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index 4e17c4f401..2ab8f58bea 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -33,7 +33,7 @@ * the target-specific DisasContext, and then invoke translator_loop. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_i= nsns, - target_ulong pc, void *host_pc); + vaddr pc, void *host_pc); =20 /** * DisasJumpType: diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 32333081d8..134eb7225b 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2971,7 +2971,7 @@ static const TranslatorOps alpha_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_i= nsns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cpu, tb, max_insns, pc, host_pc, &alpha_tr_ops, &dc.ba= se); diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index bdcb8a6555..0877cb1ce5 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -9682,7 +9682,7 @@ static const TranslatorOps thumb_translator_ops =3D { =20 /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_i= nsns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc =3D { }; const TranslatorOps *ops =3D &arm_translator_ops; diff --git a/target/avr/translate.c b/target/avr/translate.c index cdffa04519..e5dd057799 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2805,7 +2805,7 @@ static const TranslatorOps avr_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc =3D { }; translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base); diff --git a/target/cris/translate.c b/target/cris/translate.c index b3974ba0bb..ee1402a9a3 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3172,7 +3172,7 @@ static const TranslatorOps cris_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cs, tb, max_insns, pc, host_pc, &cris_tr_ops, &dc.base= ); diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 663b7bbc3a..2ef6a89622 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -1154,7 +1154,7 @@ static const TranslatorOps hexagon_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; =20 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 902cd642ae..f22ec3aeb3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4273,7 +4273,7 @@ static const TranslatorOps hppa_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.bas= e); diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index c6894d66b1..c97d1e3da8 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -7084,7 +7084,7 @@ static const TranslatorOps i386_tr_ops =3D { =20 /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_i= nsns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; =20 diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index a75fed1d98..d80a9a3d86 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -326,7 +326,7 @@ static const TranslatorOps loongarch_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; =20 diff --git a/target/m68k/translate.c b/target/m68k/translate.c index d22df2a8dc..3408385fa1 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6105,7 +6105,7 @@ static const TranslatorOps m68k_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_i= nsns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cpu, tb, max_insns, pc, host_pc, &m68k_tr_ops, &dc.bas= e); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 49bfb4a0ea..2e628647d1 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1792,7 +1792,7 @@ static const TranslatorOps mb_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_i= nsns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base); diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index adbdcb1472..2cc4945793 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15555,7 +15555,7 @@ static const TranslatorOps mips_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; =20 diff --git a/target/nios2/translate.c b/target/nios2/translate.c index e806623594..3078372b36 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -1036,7 +1036,7 @@ static const TranslatorOps nios2_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cs, tb, max_insns, pc, host_pc, &nios2_tr_ops, &dc.bas= e); diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index ecff4412b7..d4cbc5eaea 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1658,7 +1658,7 @@ static const TranslatorOps openrisc_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 329da4d518..049f636927 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7518,7 +7518,7 @@ static const TranslatorOps ppc_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f0be79bb16..6341e4aab0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1286,7 +1286,7 @@ static const TranslatorOps riscv_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; =20 diff --git a/target/rx/translate.c b/target/rx/translate.c index f8860830ae..dd3b396946 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2271,7 +2271,7 @@ static const TranslatorOps rx_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; =20 diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 4bae1509f5..f35999ffc0 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6528,7 +6528,7 @@ static const TranslatorOps s390x_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; =20 diff --git a/target/sh4/translate.c b/target/sh4/translate.c index cbd8dfc02f..a48aef2cbe 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2300,7 +2300,7 @@ static const TranslatorOps sh4_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index f92ff80ac8..28cd3510e1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5709,7 +5709,7 @@ static const TranslatorOps sparc_tr_ops =3D { }; =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc =3D {}; =20 diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 1b625629bb..b26aa8098f 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8448,7 +8448,7 @@ static const TranslatorOps tricore_tr_ops =3D { =20 =20 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; translator_loop(cs, tb, max_insns, pc, host_pc, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 54bee7ddba..47f321a720 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1256,7 +1256,7 @@ static const TranslatorOps xtensa_translator_ops =3D { }; =20 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_i= nsns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc =3D {}; translator_loop(cpu, tb, max_insns, pc, host_pc, --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675331; cv=none; d=zohomail.com; s=zohoarc; b=AY9ho5tbVCdTBFSxPXSDRxQM/9Rjc5tK+w/wiH+eLU+aue4PbvqZLIyszz5HB9bxucBQJkFw7WOTrfTlUruY+CG5hl+/K4b5M2Y4Rcsz7IOzsVe7HcOYCbS34LS2i5JB89o1tmoe31ysrxWhVLLIljda6kvGWQEicxf84P3cZyw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675331; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Fri, 19 Jan 2024 09:40:24 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2b-0003j9-JD for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=9odshd6cnNtmtj3iaUrnIF7sAejUiH24FOWHPx/ofJo=; b=Wy6l8KJNaoPKIFhEk5ApVnJOin +57vDmqhFGgpDCPIWJkBkaq22/eAHTB8umjjXUNk48rcBix0eVoazSajl3AVffKFAP6GUlzoNlIAf x+iPsngwdEzhaU5ootA63jCVTZhtUWNph+1D2hHRoVx50MLJ1ChgKc+YyHklxk1ehHl8=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 09/34] exec: [VADDR] Use vaddr in DisasContextBase for virtual addresses Date: Fri, 19 Jan 2024 15:39:59 +0100 Message-ID: <20240119144024.14289-10-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675332986100003 Content-Type: text/plain; charset="utf-8" Updates target/ QEMU_LOG macros to use VADDR_PRIx for printing updated DisasContextBase fields. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- include/exec/translator.h | 6 +++--- target/mips/tcg/translate.h | 3 ++- target/hexagon/translate.c | 3 ++- target/m68k/translate.c | 2 +- target/mips/tcg/translate.c | 12 ++++++------ 5 files changed, 14 insertions(+), 12 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index 2ab8f58bea..c4b46ec8aa 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -77,8 +77,8 @@ typedef enum DisasJumpType { */ typedef struct DisasContextBase { TranslationBlock *tb; - target_ulong pc_first; - target_ulong pc_next; + vaddr pc_first; + vaddr pc_next; DisasJumpType is_jmp; int num_insns; int max_insns; @@ -231,7 +231,7 @@ void translator_fake_ldb(uint8_t insn8, abi_ptr pc); * Translators can use this to enforce the rule that only single-insn * translation blocks are allowed to cross page boundaries. */ -static inline bool is_same_page(const DisasContextBase *db, target_ulong a= ddr) +static inline bool is_same_page(const DisasContextBase *db, vaddr addr) { return ((addr ^ db->pc_first) & TARGET_PAGE_MASK) =3D=3D 0; } diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index cffcfeab8c..93a78b8121 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -202,7 +202,8 @@ extern TCGv bcond; do { = \ if (MIPS_DEBUG_DISAS) { = \ qemu_log_mask(CPU_LOG_TB_IN_ASM, = \ - TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\= n", \ + "%016" VADDR_PRIx = \ + ": %08x Invalid %s %03x %03x %03x\n", = \ ctx->base.pc_next, ctx->opcode, op, = \ ctx->opcode >> 26, ctx->opcode & 0x3F, = \ ((ctx->opcode >> 16) & 0x1F)); = \ diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 2ef6a89622..7988e54f7d 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -234,7 +234,8 @@ static int read_packet_words(CPUHexagonState *env, Disa= sContext *ctx, g_assert(ctx->base.num_insns =3D=3D 1); } =20 - HEX_DEBUG_LOG("decode_packet: pc =3D 0x%x\n", ctx->base.pc_next); + HEX_DEBUG_LOG("decode_packet: pc =3D 0x%" VADDR_PRIx "\n", + ctx->base.pc_next); HEX_DEBUG_LOG(" words =3D { "); for (int i =3D 0; i < nwords; i++) { HEX_DEBUG_LOG("0x%x, ", words[i]); diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 3408385fa1..a51fdef32a 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1474,7 +1474,7 @@ DISAS_INSN(undef) * for the 680x0 series, as well as those that are implemented * but actually illegal for CPU32 or pre-68020. */ - qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n", + qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %" VADDR_PRIx "\= n", insn, s->base.pc_next); gen_exception(s, s->base.pc_next, EXCP_ILLEGAL); } diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 2cc4945793..c5a7378dee 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -4585,8 +4585,8 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS - LOG_DISAS("Branch in delay / forbidden slot at PC 0x" - TARGET_FMT_lx "\n", ctx->base.pc_next); + LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" + VADDR_PRIx "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); goto out; @@ -9061,8 +9061,8 @@ static void gen_compute_branch1_r6(DisasContext *ctx,= uint32_t op, =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS - LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx - "\n", ctx->base.pc_next); + LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" + VADDR_PRIx "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); return; @@ -11275,8 +11275,8 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS - LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx - "\n", ctx->base.pc_next); + LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" + VADDR_PRIx "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); return; --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=rW6sRB4eCsSZkO9YFs9s1AVEkogjjwAKpHsPA+2vclM=; b=iK8SAis8/+IYqPJxpDdvBJI1bb UNqK2qDWS6MmAlhNJTzUsTuv4Jh6guvS9FKoUwgwtXu5e3FVbmiibHj9SjU55dK0DGBExjZkv6eb3 kQkOPpwH/wNgxTl+Wb6mmJNg9nrD1iDs98e4gkAw8ifRaL2Gl5CXjUeIP5op+YZCe1is=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 10/34] exec: [VADDR] typedef abi_ptr to vaddr Date: Fri, 19 Jan 2024 15:40:00 +0100 Message-ID: <20240119144024.14289-11-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675316960100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- include/exec/cpu_ldst.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 6061e33ac9..eb8f3f0595 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -121,8 +121,8 @@ static inline bool guest_range_valid_untagged(abi_ulong= start, abi_ulong len) h2g_nocheck(x); \ }) #else -typedef target_ulong abi_ptr; -#define TARGET_ABI_FMT_ptr TARGET_FMT_lx +typedef vaddr abi_ptr; +#define TARGET_ABI_FMT_ptr VADDR_PRIx #endif =20 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr); --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675337; cv=none; d=zohomail.com; s=zohoarc; b=cAhilTgYm3KYGGha7sk4A1vfX9rhy7IaVttZQts+mDRGoTOHlxGamKw2E1FPGG5CV4eHzy5EGQPwtpSWz3JmbFs9cTDQkvBHQrVQJPCyXjNLsVul/y2z1uELJeiL8HBGMPfSpRxHxhdDx6U3o860RgN4UH3smD9Uchy3x7Miylo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675337; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Fri, 19 Jan 2024 09:40:31 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2h-0003qe-Lm for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=uMQY05glCUgc2SOZtvjUFn8m9dY4dxvnJGKBXXX0x6U=; b=XooMNysNb5XXAXMg7Ll/o5+b0l NNyEV181Re71FV0s4VKK+vQk0p4oXkVFltsnMsH/2p2N369Z+dB+7kgG5PHjBdCUbY8NwSrCgfszA U0JX6d7CTxhkub+jie5jrz/z0FGR5ZWM+7sZD0du0LRMwUS70G/gnkTyvdQElml5ENdM=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 11/34] [IGNORE] Squash of header code shuffling Date: Fri, 19 Jan 2024 15:40:01 +0100 Message-ID: <20240119144024.14289-12-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675339008100004 Content-Type: text/plain; charset="utf-8" This commit squashes header changes that are likely to change during rebase. Code is moved from common to specific headers, or vice versa to ensure that no target-specific code is pulled by accel/tcg via headers. Signed-off-by: Anton Johansson --- accel/tcg/tb-hash.h | 4 +- hw/s390x/s390-virtio-hcall.h | 2 + include/exec/cpu-all.h | 1 + include/exec/cpu-common.h | 2 + include/exec/cpu_ldst-target.h | 52 +++++ include/exec/cpu_ldst.h | 60 ++---- include/exec/exec-all.h | 347 +------------------------------ include/exec/exec-common.h | 367 +++++++++++++++++++++++++++++++++ include/exec/memory-internal.h | 2 +- include/exec/ram_addr.h | 3 +- include/qemu/plugin-memory.h | 1 - accel/tcg/cpu-exec.c | 1 + plugins/core.c | 1 + target/arm/cpu.c | 1 + target/sparc/gdbstub.c | 3 + 15 files changed, 459 insertions(+), 388 deletions(-) create mode 100644 include/exec/cpu_ldst-target.h create mode 100644 include/exec/exec-common.h diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h index a0c61f25cd..2569810365 100644 --- a/accel/tcg/tb-hash.h +++ b/accel/tcg/tb-hash.h @@ -20,8 +20,8 @@ #ifndef EXEC_TB_HASH_H #define EXEC_TB_HASH_H =20 -#include "exec/cpu-defs.h" -#include "exec/exec-all.h" +#include "exec/exec-common.h" +#include "exec/translation-block.h" #include "qemu/xxhash.h" #include "tb-jmp-cache.h" =20 diff --git a/hw/s390x/s390-virtio-hcall.h b/hw/s390x/s390-virtio-hcall.h index 9800c4b351..0e48dbf71f 100644 --- a/hw/s390x/s390-virtio-hcall.h +++ b/hw/s390x/s390-virtio-hcall.h @@ -12,6 +12,8 @@ #ifndef HW_S390_VIRTIO_HCALL_H #define HW_S390_VIRTIO_HCALL_H =20 +#include "qemu/osdep.h" +#include "cpu.h" #include "standard-headers/asm-s390/virtio-ccw.h" =20 /* The only thing that we need from the old kvm_virtio.h file */ diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 83165b1ce4..483e762f05 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -20,6 +20,7 @@ #define CPU_ALL_H =20 #include "exec/cpu-common.h" +#include "exec/cpu-defs.h" #include "exec/memory.h" #include "exec/tswap.h" #include "qemu/thread.h" diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index c071f1a003..2eb6589764 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -3,6 +3,8 @@ =20 /* CPU interfaces that are target independent. */ =20 +#include "qemu/osdep.h" +#include "hw/core/cpu.h" #ifndef CONFIG_USER_ONLY #include "exec/hwaddr.h" #endif diff --git a/include/exec/cpu_ldst-target.h b/include/exec/cpu_ldst-target.h new file mode 100644 index 0000000000..4fdec4a3ff --- /dev/null +++ b/include/exec/cpu_ldst-target.h @@ -0,0 +1,52 @@ +#ifndef CPU_LDST_SPECIFIC_H +#define CPU_LDST_SPECIFIC_H + +#include "cpu-param.h" + +#if TARGET_BIG_ENDIAN +# define cpu_lduw_data cpu_lduw_be_data +# define cpu_ldsw_data cpu_ldsw_be_data +# define cpu_ldl_data cpu_ldl_be_data +# define cpu_ldq_data cpu_ldq_be_data +# define cpu_lduw_data_ra cpu_lduw_be_data_ra +# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra +# define cpu_ldl_data_ra cpu_ldl_be_data_ra +# define cpu_ldq_data_ra cpu_ldq_be_data_ra +# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra +# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra +# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra +# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra +# define cpu_stw_data cpu_stw_be_data +# define cpu_stl_data cpu_stl_be_data +# define cpu_stq_data cpu_stq_be_data +# define cpu_stw_data_ra cpu_stw_be_data_ra +# define cpu_stl_data_ra cpu_stl_be_data_ra +# define cpu_stq_data_ra cpu_stq_be_data_ra +# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra +# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra +# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra +#else +# define cpu_lduw_data cpu_lduw_le_data +# define cpu_ldsw_data cpu_ldsw_le_data +# define cpu_ldl_data cpu_ldl_le_data +# define cpu_ldq_data cpu_ldq_le_data +# define cpu_lduw_data_ra cpu_lduw_le_data_ra +# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra +# define cpu_ldl_data_ra cpu_ldl_le_data_ra +# define cpu_ldq_data_ra cpu_ldq_le_data_ra +# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra +# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra +# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra +# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra +# define cpu_stw_data cpu_stw_le_data +# define cpu_stl_data cpu_stl_le_data +# define cpu_stq_data cpu_stq_le_data +# define cpu_stw_data_ra cpu_stw_le_data_ra +# define cpu_stl_data_ra cpu_stl_le_data_ra +# define cpu_stq_data_ra cpu_stq_le_data_ra +# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra +# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra +# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra +#endif + +#endif diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index eb8f3f0595..24fe322d72 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -64,7 +64,21 @@ =20 #include "exec/memopidx.h" #include "qemu/int128.h" +#if defined(CONFIG_USER_ONLY) #include "cpu.h" +#include "exec/cpu-all.h" +#include "exec/user/abitypes.h" +#include "exec/user/guest-base.h" +#else +#include "qemu/typedefs.h" +#include "exec/cpu-common.h" +#include "exec/tlb-common.h" +#include "tcg/tcg.h" +#endif + +#ifdef NEED_CPU_H +#include "cpu_ldst-target.h" +#endif =20 #if defined(CONFIG_USER_ONLY) /* sparc32plus has 64bit long but 32bit space address @@ -378,52 +392,6 @@ static inline CPUTLBEntry *tlb_entry(CPUState *cpu, ui= ntptr_t mmu_idx, =20 #endif /* defined(CONFIG_USER_ONLY) */ =20 -#if TARGET_BIG_ENDIAN -# define cpu_lduw_data cpu_lduw_be_data -# define cpu_ldsw_data cpu_ldsw_be_data -# define cpu_ldl_data cpu_ldl_be_data -# define cpu_ldq_data cpu_ldq_be_data -# define cpu_lduw_data_ra cpu_lduw_be_data_ra -# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra -# define cpu_ldl_data_ra cpu_ldl_be_data_ra -# define cpu_ldq_data_ra cpu_ldq_be_data_ra -# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra -# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra -# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra -# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra -# define cpu_stw_data cpu_stw_be_data -# define cpu_stl_data cpu_stl_be_data -# define cpu_stq_data cpu_stq_be_data -# define cpu_stw_data_ra cpu_stw_be_data_ra -# define cpu_stl_data_ra cpu_stl_be_data_ra -# define cpu_stq_data_ra cpu_stq_be_data_ra -# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra -# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra -# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra -#else -# define cpu_lduw_data cpu_lduw_le_data -# define cpu_ldsw_data cpu_ldsw_le_data -# define cpu_ldl_data cpu_ldl_le_data -# define cpu_ldq_data cpu_ldq_le_data -# define cpu_lduw_data_ra cpu_lduw_le_data_ra -# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra -# define cpu_ldl_data_ra cpu_ldl_le_data_ra -# define cpu_ldq_data_ra cpu_ldq_le_data_ra -# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra -# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra -# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra -# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra -# define cpu_stw_data cpu_stw_le_data -# define cpu_stl_data cpu_stl_le_data -# define cpu_stq_data cpu_stq_le_data -# define cpu_stw_data_ra cpu_stw_le_data_ra -# define cpu_stl_data_ra cpu_stl_le_data_ra -# define cpu_stq_data_ra cpu_stq_le_data_ra -# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra -# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra -# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra -#endif - uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra); uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr, diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index ee90ef122b..8410521893 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -20,352 +20,25 @@ #ifndef EXEC_ALL_H #define EXEC_ALL_H =20 +#if defined(CONFIG_USER_ONLY) #include "cpu.h" +#endif +#include "exec/exec-common.h" #if defined(CONFIG_USER_ONLY) #include "exec/cpu_ldst.h" #endif #include "exec/translation-block.h" #include "qemu/clang-tsa.h" - -/** - * cpu_loop_exit_requested: - * @cpu: The CPU state to be tested - * - * Indicate if somebody asked for a return of the CPU to the main loop - * (e.g., via cpu_exit() or cpu_interrupt()). - * - * This is helpful for architectures that support interruptible - * instructions. After writing back all state to registers/memory, this - * call can be used to check if it makes sense to return to the main loop - * or to continue executing the interruptible instruction. - */ -static inline bool cpu_loop_exit_requested(CPUState *cpu) -{ - return (int32_t)qatomic_read(&cpu->neg.icount_decr.u32) < 0; -} - -#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) -/* cputlb.c */ -/** - * tlb_init - initialize a CPU's TLB - * @cpu: CPU whose TLB should be initialized - */ -void tlb_init(CPUState *cpu); -/** - * tlb_destroy - destroy a CPU's TLB - * @cpu: CPU whose TLB should be destroyed - */ -void tlb_destroy(CPUState *cpu); -/** - * tlb_flush_page: - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * - * Flush one page from the TLB of the specified CPU, for all - * MMU indexes. - */ -void tlb_flush_page(CPUState *cpu, vaddr addr); -/** - * tlb_flush_page_all_cpus: - * @cpu: src CPU of the flush - * @addr: virtual address of page to be flushed - * - * Flush one page from the TLB of the specified CPU, for all - * MMU indexes. - */ -void tlb_flush_page_all_cpus(CPUState *src, vaddr addr); -/** - * tlb_flush_page_all_cpus_synced: - * @cpu: src CPU of the flush - * @addr: virtual address of page to be flushed - * - * Flush one page from the TLB of the specified CPU, for all MMU - * indexes like tlb_flush_page_all_cpus except the source vCPUs work - * is scheduled as safe work meaning all flushes will be complete once - * the source vCPUs safe work is complete. This will depend on when - * the guests translation ends the TB. - */ -void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); -/** - * tlb_flush: - * @cpu: CPU whose TLB should be flushed - * - * Flush the entire TLB for the specified CPU. Most CPU architectures - * allow the implementation to drop entries from the TLB at any time - * so this is generally safe. If more selective flushing is required - * use one of the other functions for efficiency. - */ -void tlb_flush(CPUState *cpu); -/** - * tlb_flush_all_cpus: - * @cpu: src CPU of the flush - */ -void tlb_flush_all_cpus(CPUState *src_cpu); -/** - * tlb_flush_all_cpus_synced: - * @cpu: src CPU of the flush - * - * Like tlb_flush_all_cpus except this except the source vCPUs work is - * scheduled as safe work meaning all flushes will be complete once - * the source vCPUs safe work is complete. This will depend on when - * the guests translation ends the TB. - */ -void tlb_flush_all_cpus_synced(CPUState *src_cpu); -/** - * tlb_flush_page_by_mmuidx: - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of MMU indexes to flush - * - * Flush one page from the TLB of the specified CPU, for the specified - * MMU indexes. - */ -void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap); -/** - * tlb_flush_page_by_mmuidx_all_cpus: - * @cpu: Originating CPU of the flush - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of MMU indexes to flush - * - * Flush one page from the TLB of all CPUs, for the specified - * MMU indexes. - */ -void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr, - uint16_t idxmap); -/** - * tlb_flush_page_by_mmuidx_all_cpus_synced: - * @cpu: Originating CPU of the flush - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of MMU indexes to flush - * - * Flush one page from the TLB of all CPUs, for the specified MMU - * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source - * vCPUs work is scheduled as safe work meaning all flushes will be - * complete once the source vCPUs safe work is complete. This will - * depend on when the guests translation ends the TB. - */ -void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, - uint16_t idxmap); -/** - * tlb_flush_by_mmuidx: - * @cpu: CPU whose TLB should be flushed - * @wait: If true ensure synchronisation by exiting the cpu_loop - * @idxmap: bitmap of MMU indexes to flush - * - * Flush all entries from the TLB of the specified CPU, for the specified - * MMU indexes. - */ -void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); -/** - * tlb_flush_by_mmuidx_all_cpus: - * @cpu: Originating CPU of the flush - * @idxmap: bitmap of MMU indexes to flush - * - * Flush all entries from all TLBs of all CPUs, for the specified - * MMU indexes. - */ -void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap); -/** - * tlb_flush_by_mmuidx_all_cpus_synced: - * @cpu: Originating CPU of the flush - * @idxmap: bitmap of MMU indexes to flush - * - * Flush all entries from all TLBs of all CPUs, for the specified - * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source - * vCPUs work is scheduled as safe work meaning all flushes will be - * complete once the source vCPUs safe work is complete. This will - * depend on when the guests translation ends the TB. - */ -void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); - -/** - * tlb_flush_page_bits_by_mmuidx - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of mmu indexes to flush - * @bits: number of significant bits in address - * - * Similar to tlb_flush_page_mask, but with a bitmap of indexes. - */ -void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bits); - -/* Similarly, with broadcast and syncing. */ -void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bits= ); -void tlb_flush_page_bits_by_mmuidx_all_cpus_synced - (CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits); - -/** - * tlb_flush_range_by_mmuidx - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of the start of the range to be flushed - * @len: length of range to be flushed - * @idxmap: bitmap of mmu indexes to flush - * @bits: number of significant bits in address - * - * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), - * comparing only the low @bits worth of each virtual page. - */ -void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, - unsigned bits); - -/* Similarly, with broadcast and syncing. */ -void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, - unsigned bits); -void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - vaddr len, - uint16_t idxmap, - unsigned bits); - -/** - * tlb_set_page_full: - * @cpu: CPU context - * @mmu_idx: mmu index of the tlb to modify - * @addr: virtual address of the entry to add - * @full: the details of the tlb entry - * - * Add an entry to @cpu tlb index @mmu_idx. All of the fields of - * @full must be filled, except for xlat_section, and constitute - * the complete description of the translated page. - * - * This is generally called by the target tlb_fill function after - * having performed a successful page table walk to find the physical - * address and attributes for the translation. - * - * At most one entry for a given virtual address is permitted. Only a - * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only - * used by tlb_flush_page. - */ -void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, - CPUTLBEntryFull *full); - -/** - * tlb_set_page_with_attrs: - * @cpu: CPU to add this TLB entry for - * @addr: virtual address of page to add entry for - * @paddr: physical address of the page - * @attrs: memory transaction attributes - * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) - * @mmu_idx: MMU index to insert TLB entry for - * @size: size of the page in bytes - * - * Add an entry to this CPU's TLB (a mapping from virtual address - * @addr to physical address @paddr) with the specified memory - * transaction attributes. This is generally called by the target CPU - * specific code after it has been called through the tlb_fill() - * entry point and performed a successful page table walk to find - * the physical address and attributes for the virtual address - * which provoked the TLB miss. - * - * At most one entry for a given virtual address is permitted. Only a - * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only - * used by tlb_flush_page. - */ -void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, - hwaddr paddr, MemTxAttrs attrs, - int prot, int mmu_idx, vaddr size); -/* tlb_set_page: +/* + * All the code in this header is target independent. * - * This function is equivalent to calling tlb_set_page_with_attrs() - * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided - * as a convenience for CPUs which don't use memory transaction attributes. + * We only have this cpu.h include here since a lot of + * compilation units rely on getting cpu.h from exec-all.h. */ -void tlb_set_page(CPUState *cpu, vaddr addr, - hwaddr paddr, int prot, - int mmu_idx, vaddr size); -#else -static inline void tlb_init(CPUState *cpu) -{ -} -static inline void tlb_destroy(CPUState *cpu) -{ -} -static inline void tlb_flush_page(CPUState *cpu, vaddr addr) -{ -} -static inline void tlb_flush_page_all_cpus(CPUState *src, vaddr addr) -{ -} -static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr add= r) -{ -} -static inline void tlb_flush(CPUState *cpu) -{ -} -static inline void tlb_flush_all_cpus(CPUState *src_cpu) -{ -} -static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) -{ -} -static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, - vaddr addr, uint16_t idxmap) -{ -} - -static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) -{ -} -static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, - vaddr addr, - uint16_t idxmap) -{ -} -static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - uint16_t idxma= p) -{ -} -static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t id= xmap) -{ -} - -static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, - uint16_t idxmap) -{ -} -static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, - vaddr addr, - uint16_t idxmap, - unsigned bits) -{ -} -static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, - vaddr addr, - uint16_t idxmap, - unsigned bits) -{ -} -static inline void -tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bi= ts) -{ -} -static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, - unsigned bits) -{ -} -static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, - vaddr addr, - vaddr len, - uint16_t idxmap, - unsigned bits) -{ -} -static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - vaddr len, - uint16_t idxm= ap, - unsigned bits) -{ -} +#if defined(NEED_CPU_H) +#include "cpu.h" #endif + /** * probe_access: * @env: CPUArchState diff --git a/include/exec/exec-common.h b/include/exec/exec-common.h new file mode 100644 index 0000000000..82c7216c39 --- /dev/null +++ b/include/exec/exec-common.h @@ -0,0 +1,367 @@ +/* + * target-independent internal execution defines for qemu + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef EXEC_COMMON_H +#define EXEC_COMMON_H + +#include "qemu/osdep.h" +#include "hw/core/cpu.h" + +/** + * cpu_loop_exit_requested: + * @cpu: The CPU state to be tested + * + * Indicate if somebody asked for a return of the CPU to the main loop + * (e.g., via cpu_exit() or cpu_interrupt()). + * + * This is helpful for architectures that support interruptible + * instructions. After writing back all state to registers/memory, this + * call can be used to check if it makes sense to return to the main loop + * or to continue executing the interruptible instruction. + */ +static inline bool cpu_loop_exit_requested(CPUState *cpu) +{ + return (int32_t)qatomic_read(&cpu->neg.icount_decr.u32) < 0; +} + +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) +/* cputlb.c */ +/** + * tlb_init - initialize a CPU's TLB + * @cpu: CPU whose TLB should be initialized + */ +void tlb_init(CPUState *cpu); +/** + * tlb_destroy - destroy a CPU's TLB + * @cpu: CPU whose TLB should be destroyed + */ +void tlb_destroy(CPUState *cpu); +/** + * tlb_flush_page: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * + * Flush one page from the TLB of the specified CPU, for all + * MMU indexes. + */ +void tlb_flush_page(CPUState *cpu, vaddr addr); +/** + * tlb_flush_page_all_cpus: + * @cpu: src CPU of the flush + * @addr: virtual address of page to be flushed + * + * Flush one page from the TLB of the specified CPU, for all + * MMU indexes. + */ +void tlb_flush_page_all_cpus(CPUState *src, vaddr addr); +/** + * tlb_flush_page_all_cpus_synced: + * @cpu: src CPU of the flush + * @addr: virtual address of page to be flushed + * + * Flush one page from the TLB of the specified CPU, for all MMU + * indexes like tlb_flush_page_all_cpus except the source vCPUs work + * is scheduled as safe work meaning all flushes will be complete once + * the source vCPUs safe work is complete. This will depend on when + * the guests translation ends the TB. + */ +void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); +/** + * tlb_flush: + * @cpu: CPU whose TLB should be flushed + * + * Flush the entire TLB for the specified CPU. Most CPU architectures + * allow the implementation to drop entries from the TLB at any time + * so this is generally safe. If more selective flushing is required + * use one of the other functions for efficiency. + */ +void tlb_flush(CPUState *cpu); +/** + * tlb_flush_all_cpus: + * @cpu: src CPU of the flush + */ +void tlb_flush_all_cpus(CPUState *src_cpu); +/** + * tlb_flush_all_cpus_synced: + * @cpu: src CPU of the flush + * + * Like tlb_flush_all_cpus except this except the source vCPUs work is + * scheduled as safe work meaning all flushes will be complete once + * the source vCPUs safe work is complete. This will depend on when + * the guests translation ends the TB. + */ +void tlb_flush_all_cpus_synced(CPUState *src_cpu); +/** + * tlb_flush_page_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush one page from the TLB of the specified CPU, for the specified + * MMU indexes. + */ +void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, + uint16_t idxmap); +/** + * tlb_flush_page_by_mmuidx_all_cpus: + * @cpu: Originating CPU of the flush + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush one page from the TLB of all CPUs, for the specified + * MMU indexes. + */ +void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr, + uint16_t idxmap); +/** + * tlb_flush_page_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush one page from the TLB of all CPUs, for the specified MMU + * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source + * vCPUs work is scheduled as safe work meaning all flushes will be + * complete once the source vCPUs safe work is complete. This will + * depend on when the guests translation ends the TB. + */ +void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, + uint16_t idxmap); +/** + * tlb_flush_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @wait: If true ensure synchronisation by exiting the cpu_loop + * @idxmap: bitmap of MMU indexes to flush + * + * Flush all entries from the TLB of the specified CPU, for the specified + * MMU indexes. + */ +void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); +/** + * tlb_flush_by_mmuidx_all_cpus: + * @cpu: Originating CPU of the flush + * @idxmap: bitmap of MMU indexes to flush + * + * Flush all entries from all TLBs of all CPUs, for the specified + * MMU indexes. + */ +void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap); +/** + * tlb_flush_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @idxmap: bitmap of MMU indexes to flush + * + * Flush all entries from all TLBs of all CPUs, for the specified + * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source + * vCPUs work is scheduled as safe work meaning all flushes will be + * complete once the source vCPUs safe work is complete. This will + * depend on when the guests translation ends the TB. + */ +void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); + +/** + * tlb_flush_page_bits_by_mmuidx + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of mmu indexes to flush + * @bits: number of significant bits in address + * + * Similar to tlb_flush_page_mask, but with a bitmap of indexes. + */ +void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, + uint16_t idxmap, unsigned bits); + +/* Similarly, with broadcast and syncing. */ +void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr, + uint16_t idxmap, unsigned bits= ); +void tlb_flush_page_bits_by_mmuidx_all_cpus_synced + (CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits); + +/** + * tlb_flush_range_by_mmuidx + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of the start of the range to be flushed + * @len: length of range to be flushed + * @idxmap: bitmap of mmu indexes to flush + * @bits: number of significant bits in address + * + * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), + * comparing only the low @bits worth of each virtual page. + */ +void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, + unsigned bits); + +/* Similarly, with broadcast and syncing. */ +void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, + unsigned bits); +void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + vaddr len, + uint16_t idxmap, + unsigned bits); + +/** + * tlb_set_page_full: + * @cpu: CPU context + * @mmu_idx: mmu index of the tlb to modify + * @addr: virtual address of the entry to add + * @full: the details of the tlb entry + * + * Add an entry to @cpu tlb index @mmu_idx. All of the fields of + * @full must be filled, except for xlat_section, and constitute + * the complete description of the translated page. + * + * This is generally called by the target tlb_fill function after + * having performed a successful page table walk to find the physical + * address and attributes for the translation. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only + * used by tlb_flush_page. + */ +void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, + CPUTLBEntryFull *full); + +/** + * tlb_set_page_with_attrs: + * @cpu: CPU to add this TLB entry for + * @addr: virtual address of page to add entry for + * @paddr: physical address of the page + * @attrs: memory transaction attributes + * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) + * @mmu_idx: MMU index to insert TLB entry for + * @size: size of the page in bytes + * + * Add an entry to this CPU's TLB (a mapping from virtual address + * @addr to physical address @paddr) with the specified memory + * transaction attributes. This is generally called by the target CPU + * specific code after it has been called through the tlb_fill() + * entry point and performed a successful page table walk to find + * the physical address and attributes for the virtual address + * which provoked the TLB miss. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only + * used by tlb_flush_page. + */ +void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, + hwaddr paddr, MemTxAttrs attrs, + int prot, int mmu_idx, vaddr size); +/** + * tlb_set_page: + * + * This function is equivalent to calling tlb_set_page_with_attrs() + * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided + * as a convenience for CPUs which don't use memory transaction attributes. + */ +void tlb_set_page(CPUState *cpu, vaddr addr, + hwaddr paddr, int prot, + int mmu_idx, vaddr size); +#else +static inline void tlb_init(CPUState *cpu) +{ +} +static inline void tlb_destroy(CPUState *cpu) +{ +} +static inline void tlb_flush_page(CPUState *cpu, vaddr addr) +{ +} +static inline void tlb_flush_page_all_cpus(CPUState *src, vaddr addr) +{ +} +static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr add= r) +{ +} +static inline void tlb_flush(CPUState *cpu) +{ +} +static inline void tlb_flush_all_cpus(CPUState *src_cpu) +{ +} +static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) +{ +} +static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, + vaddr addr, uint16_t idxmap) +{ +} + +static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) +{ +} +static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, + vaddr addr, + uint16_t idxmap) +{ +} +static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + uint16_t idxma= p) +{ +} +static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t id= xmap) +{ +} + +static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, + uint16_t idxmap) +{ +} +static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, + vaddr addr, + uint16_t idxmap, + unsigned bits) +{ +} +static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, + vaddr addr, + uint16_t idxmap, + unsigned bits) +{ +} +static inline void +tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, + uint16_t idxmap, unsigned bi= ts) +{ +} +static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, + unsigned bits) +{ +} +static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, + vaddr addr, + vaddr len, + uint16_t idxmap, + unsigned bits) +{ +} +static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + vaddr len, + uint16_t idxm= ap, + unsigned bits) +{ +} +#endif + +#endif /* EXEC_COMMON_H */ diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h index 100c1237ac..ef9816d0c1 100644 --- a/include/exec/memory-internal.h +++ b/include/exec/memory-internal.h @@ -20,7 +20,7 @@ #ifndef MEMORY_INTERNAL_H #define MEMORY_INTERNAL_H =20 -#include "cpu.h" +#include "exec/memory.h" =20 #ifndef CONFIG_USER_ONLY static inline AddressSpaceDispatch *flatview_to_dispatch(FlatView *fv) diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index 9f2e3893f5..765290a2f4 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -20,11 +20,12 @@ #define RAM_ADDR_H =20 #ifndef CONFIG_USER_ONLY -#include "cpu.h" #include "sysemu/xen.h" #include "sysemu/tcg.h" #include "exec/ramlist.h" #include "exec/ramblock.h" +#include "exec/memory.h" +#include "qemu/bitmap.h" =20 extern uint64_t total_dirty_pages; =20 diff --git a/include/qemu/plugin-memory.h b/include/qemu/plugin-memory.h index 71c1123308..6065ec7aaf 100644 --- a/include/qemu/plugin-memory.h +++ b/include/qemu/plugin-memory.h @@ -9,7 +9,6 @@ #ifndef PLUGIN_MEMORY_H #define PLUGIN_MEMORY_H =20 -#include "exec/cpu-defs.h" #include "exec/hwaddr.h" =20 struct qemu_plugin_hwaddr { diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index fd0fc08f76..88de0eb000 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -34,6 +34,7 @@ #include "hw/i386/apic.h" #endif #include "sysemu/cpus.h" +#include "cpu.h" #include "exec/cpu-all.h" #include "sysemu/cpu-timers.h" #include "exec/replay-core.h" diff --git a/plugins/core.c b/plugins/core.c index 3c4e26c7ed..987b5300c7 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -24,6 +24,7 @@ #include "exec/cpu-common.h" =20 #include "exec/exec-all.h" +#include "exec/cpu-defs.h" #include "exec/tb-flush.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 831295d7cd..374ef523da 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -32,6 +32,7 @@ #endif /* CONFIG_TCG */ #include "internals.h" #include "exec/exec-all.h" +#include "exec/cpu-all.h" #include "hw/qdev-properties.h" #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index a1c8fdc4d5..b3eb8d035f 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -20,6 +20,9 @@ #include "qemu/osdep.h" #include "cpu.h" #include "gdbstub/helpers.h" +#if defined(TARGET_ABI32) && defined(CONFIG_USER_ONLY) +#include "exec/user/abitypes.h" +#endif =20 #ifdef TARGET_ABI32 #define gdb_get_rega(buf, val) gdb_get_reg32(buf, val) --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675585; cv=none; d=zohomail.com; s=zohoarc; b=TiwjjOKk/xGiquH+NbI7mLH9KKWM8uBnrbvKSYHH94GNMw6rwBhYXU0yMHn8cDr5vGJUDa1/+RBrX86c4g/zUk9JzXqgScpFd6CD0ncYe0O4pRTWetmeELGiCXOE7QO8ISmBlciqzM/DXHRCWDf8oe/rqwxtx4swgxrkNA3JU1o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675585; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=RJp3FDw6CrSCzKk75aUjlDvdhLiCJ8PHaUBmcDm9HLw=; b=IECoWkP5dpKoz2nKHfzPjiFu9etMQGAtVtGTijAgyAmgdDHZEtY/ZD5XCz/1avnI+gI0Jxec9ke+eGWdMlMoxl+VKzTNQfCRwk6JpgryR8unHr/bJp919buZj4aBt5x31rHaBeUKS/nkpj9dnLvnwU0J/JRuMjBw+wGKCZ2sEa4= ARC-Authentication-Results: i=1; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=RJp3FDw6CrSCzKk75aUjlDvdhLiCJ8PHaUBmcDm9HLw=; b=WLkoLfZAgtmqctR5iZtWLTMUde jbOOfVaqcf0VJgQgbUCqMGWoHiL8e7bqwUyzpuEgPMXqAiPePT03Hq3pekaenn9Epunp/1bCQekoQ M7vuBp2mFEOY5lNULsOBWwPwt90QOzbOGFo41mNkCbCtVVD86bme9xEhPVxGyFmw+ikQ=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 12/34] target: Uninline cpu_mmu_index() Date: Fri, 19 Jan 2024 15:40:02 +0100 Message-ID: <20240119144024.14289-13-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675586513100003 Content-Type: text/plain; charset="utf-8" Uninlines the target-defined cpu_mmu_index() function by moving its definition to target/*/cpu.c. This allows for compiling memory access functions in accel/tcg/cputlb.c without having to know target specifics. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- include/exec/cpu-common.h | 10 ++++++++++ target/alpha/cpu.h | 9 --------- target/arm/cpu.h | 13 ------------- target/avr/cpu.h | 6 ------ target/cris/cpu.h | 4 ---- target/hexagon/cpu.h | 9 --------- target/hppa/cpu.h | 12 ------------ target/i386/cpu.h | 7 ------- target/loongarch/cpu.h | 12 ------------ target/m68k/cpu.h | 4 ---- target/microblaze/cpu.h | 15 --------------- target/mips/cpu.h | 14 +------------- target/nios2/cpu.h | 6 ------ target/openrisc/cpu.h | 12 ------------ target/ppc/cpu.h | 8 -------- target/riscv/cpu.h | 2 -- target/rx/cpu.h | 5 ----- target/s390x/cpu.h | 31 ------------------------------- target/sh4/cpu.h | 10 ---------- target/sparc/cpu.h | 28 ---------------------------- target/tricore/cpu.h | 5 ----- target/xtensa/cpu.h | 5 ----- target/alpha/cpu.c | 8 ++++++++ target/arm/cpu.c | 5 +++++ target/avr/cpu.c | 5 +++++ target/cris/cpu.c | 4 ++++ target/hexagon/cpu.c | 9 +++++++++ target/hppa/cpu.c | 12 ++++++++++++ target/i386/cpu.c | 7 +++++++ target/loongarch/cpu.c | 12 ++++++++++++ target/m68k/cpu.c | 5 +++++ target/microblaze/cpu.c | 16 ++++++++++++++++ target/mips/cpu.c | 14 ++++++++++++++ target/nios2/cpu.c | 6 ++++++ target/openrisc/cpu.c | 12 ++++++++++++ target/ppc/cpu.c | 9 +++++++++ target/riscv/cpu_helper.c | 2 +- target/rx/cpu.c | 5 +++++ target/s390x/cpu.c | 31 +++++++++++++++++++++++++++++++ target/sh4/cpu.c | 13 +++++++++++++ target/sparc/cpu.c | 28 ++++++++++++++++++++++++++++ target/tricore/cpu.c | 5 +++++ target/xtensa/cpu.c | 4 ++++ 43 files changed, 222 insertions(+), 217 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 2eb6589764..12952c481c 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -60,6 +60,16 @@ void cpu_list_lock(void); void cpu_list_unlock(void); unsigned int cpu_list_generation_id_get(void); =20 +/** + * cpu_mmu_index: + * @env: The cpu environment + * @ifetch: True for code access, false for data access. + * + * Return the core mmu index for the current translation regime. + * This function is used by generic TCG code paths. + */ +int cpu_mmu_index(CPUArchState *env, bool ifetch); + void tcg_flush_softmmu_tlb(CPUState *cs); void tcg_flush_jmp_cache(CPUState *cs); =20 diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e2a467ec17..e93186d50e 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -380,15 +380,6 @@ enum { =20 #define TB_FLAG_UNALIGN (1u << 1) =20 -static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) -{ - int ret =3D env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_= IDX; - if (env->flags & ENV_FLAG_PAL_MODE) { - ret =3D MMU_KERNEL_IDX; - } - return ret; -} - enum { IR_V0 =3D 0, IR_T0 =3D 1, diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 51963b6545..3dfca8f3ae 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3167,19 +3167,6 @@ FIELD(TBFLAG_A64, NAA, 30, 1) #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHIC= H) =20 -/** - * cpu_mmu_index: - * @env: The cpu environment - * @ifetch: True for code access, false for data access. - * - * Return the core mmu index for the current translation regime. - * This function is used by generic TCG code paths. - */ -static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) -{ - return EX_TBFLAG_ANY(env->hflags, MMUIDX); -} - /** * sve_vq * @env: the cpu context diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 4ce22d8e4f..581ba54aae 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -172,12 +172,6 @@ static inline void set_avr_feature(CPUAVRState *env, i= nt feature) } =20 #define cpu_list avr_cpu_list -#define cpu_mmu_index avr_cpu_mmu_index - -static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) -{ - return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; -} =20 void avr_cpu_tcg_init(void); =20 diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 676b8e93ca..9587a2a229 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -248,10 +248,6 @@ enum { =20 /* MMU modes definitions */ #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) -{ - return !!(env->pregs[PR_CCS] & U_FLAG); -} =20 /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 10cd1efd57..562b5c7095 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -165,15 +165,6 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonStat= e *env, vaddr *pc, *flags =3D hex_flags; } =20 -static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else -#error System mode not supported on Hexagon yet -#endif -} - typedef HexagonCPU ArchCPU; =20 void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7557f884b5..3da91d41d4 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -237,18 +237,6 @@ struct ArchCPU { =20 #include "exec/cpu-all.h" =20 -static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else - if (env->psw & (ifetch ? PSW_C : PSW_D)) { - return PRIV_TO_MMU_IDX(env->iaoq_f & 3); - } - return MMU_PHYS_IDX; /* mmu disabled */ -#endif -} - void hppa_translate_init(void); =20 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e1b41c29f0..7de2bad701 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2259,13 +2259,6 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define MMU_NESTED_IDX 3 #define MMU_PHYS_IDX 4 =20 -static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) -{ - return (env->hflags & HF_CPL_MASK) =3D=3D 3 ? MMU_USER_IDX : - (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) - ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; -} - static inline int cpu_mmu_index_kernel(CPUX86State *env) { return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 3b5ec51928..d85103c28d 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -415,18 +415,6 @@ struct LoongArchCPUClass { #define MMU_IDX_USER MMU_PLV_USER #define MMU_IDX_DA 4 =20 -static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_IDX_USER; -#else - if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { - return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); - } - return MMU_IDX_DA; -#endif -} - static inline bool is_la64(CPULoongArchState *env) { return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) =3D=3D CPUCFG1_ARCH_L= A64; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 20afb0c94d..da13111fd8 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -572,10 +572,6 @@ enum { /* MMU modes definitions */ #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) -{ - return (env->sr & SR_S) =3D=3D 0 ? 1 : 0; -} =20 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e43c49d4af..8f8b4f55d4 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -423,21 +423,6 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr ph= ysaddr, vaddr addr, MemTxResult response, uintptr_t retaddr); #endif =20 -static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) -{ - MicroBlazeCPU *cpu =3D env_archcpu(env); - - /* Are we in nommu mode?. */ - if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { - return MMU_NOMMU_IDX; - } - - if (env->msr & MSR_UM) { - return MMU_USER_IDX; - } - return MMU_KERNEL_IDX; -} - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_mb_cpu; #endif diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 67f8e8b988..49915af09d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1233,19 +1233,7 @@ uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *= env); */ #define MMU_USER_IDX 2 =20 -static inline int hflags_mmu_index(uint32_t hflags) -{ - if (hflags & MIPS_HFLAG_ERL) { - return 3; /* ERL */ - } else { - return hflags & MIPS_HFLAG_KSU; - } -} - -static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) -{ - return hflags_mmu_index(env->hflags); -} +int hflags_mmu_index(uint32_t hflags); =20 #include "exec/cpu-all.h" =20 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 70b6377a4f..c1d4fc6542 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -279,12 +279,6 @@ void do_nios2_semihosting(CPUNios2State *env); #define MMU_SUPERVISOR_IDX 0 #define MMU_USER_IDX 1 =20 -static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) -{ - return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : - MMU_SUPERVISOR_IDX; -} - #ifndef CONFIG_USER_ONLY hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 334997e9a1..d57f820743 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -376,18 +376,6 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCSta= te *env, vaddr *pc, | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); } =20 -static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) -{ - int ret =3D MMU_NOMMU_IDX; /* mmu is disabled */ - - if (env->sr & (ifetch ? SR_IME : SR_DME)) { - /* The mmu is enabled; test supervisor state. */ - ret =3D env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; - } - - return ret; -} - static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) { return (env->sr diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f5027616fa..faba987dc0 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1483,14 +1483,6 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint= 32_t val); =20 /* MMU modes definitions */ #define MMU_USER_IDX 0 -static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else - return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) &= 7; -#endif -} =20 /* Compatibility modes */ #if defined(TARGET_PPC64) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ef9cf21c0c..9b0590c7d9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -434,7 +434,6 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t reta= ddr); @@ -446,7 +445,6 @@ void riscv_cpu_list(void); void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); =20 #define cpu_list riscv_cpu_list -#define cpu_mmu_index riscv_cpu_mmu_index =20 #ifndef CONFIG_USER_ONLY void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, diff --git a/target/rx/cpu.h b/target/rx/cpu.h index f66754eb8a..3f5b501acf 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -151,11 +151,6 @@ static inline void cpu_get_tb_cpu_state(CPURXState *en= v, vaddr *pc, *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); } =20 -static inline int cpu_mmu_index(CPURXState *env, bool ifetch) -{ - return 0; -} - static inline uint32_t rx_cpu_pack_psw(CPURXState *env) { uint32_t psw =3D 0; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 7bea7075e1..5c646cafaa 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -348,37 +348,6 @@ extern const VMStateDescription vmstate_s390_cpu; #define MMU_HOME_IDX 2 #define MMU_REAL_IDX 3 =20 -static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else - if (!(env->psw.mask & PSW_MASK_DAT)) { - return MMU_REAL_IDX; - } - - if (ifetch) { - if ((env->psw.mask & PSW_MASK_ASC) =3D=3D PSW_ASC_HOME) { - return MMU_HOME_IDX; - } - return MMU_PRIMARY_IDX; - } - - switch (env->psw.mask & PSW_MASK_ASC) { - case PSW_ASC_PRIMARY: - return MMU_PRIMARY_IDX; - case PSW_ASC_SECONDARY: - return MMU_SECONDARY_IDX; - case PSW_ASC_HOME: - return MMU_HOME_IDX; - case PSW_ASC_ACCREG: - /* Fallthrough: access register mode is not yet supported */ - default: - abort(); - } -#endif -} - static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index f75a235973..218ba24333 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -260,16 +260,6 @@ void cpu_load_tlb(CPUSH4State * env); =20 /* MMU modes definitions */ #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch) -{ - /* The instruction in a RTE delay slot is fetched in privileged - mode, but executed in user mode. */ - if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { - return 0; - } else { - return (env->sr & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; - } -} =20 #include "exec/cpu-all.h" =20 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index b3a98f1d74..bd24cd578c 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -692,34 +692,6 @@ static inline int cpu_supervisor_mode(CPUSPARCState *e= nv1) } #endif =20 -static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) -{ -#if defined(CONFIG_USER_ONLY) - return MMU_USER_IDX; -#elif !defined(TARGET_SPARC64) - if ((env->mmuregs[0] & MMU_E) =3D=3D 0) { /* MMU disabled */ - return MMU_PHYS_IDX; - } else { - return env->psrs; - } -#else - /* IMMU or DMMU disabled. */ - if (ifetch - ? (env->lsu & IMMU_E) =3D=3D 0 || (env->pstate & PS_RED) !=3D 0 - : (env->lsu & DMMU_E) =3D=3D 0) { - return MMU_PHYS_IDX; - } else if (cpu_hypervisor_mode(env)) { - return MMU_PHYS_IDX; - } else if (env->tl > 0) { - return MMU_NUCLEUS_IDX; - } else if (cpu_supervisor_mode(env)) { - return MMU_KERNEL_IDX; - } else { - return MMU_USER_IDX; - } -#endif -} - static inline int cpu_interrupts_enabled(CPUSPARCState *env1) { #if !defined (TARGET_SPARC64) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 217937bbf6..9454b0adcd 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -371,11 +371,6 @@ void tricore_cpu_list(void); =20 #define cpu_list tricore_cpu_list =20 -static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) -{ - return 0; -} - #include "exec/cpu-all.h" =20 FIELD(TB_FLAGS, PRIV, 0, 2) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index c6bbef1e5d..89d6b690af 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -700,11 +700,6 @@ static inline uint32_t xtensa_replicate_windowstart(CP= UXtensaState *env) /* MMU modes definitions */ #define MMU_USER_IDX 3 =20 -static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) -{ - return xtensa_get_cring(env); -} - #define XTENSA_TBFLAG_RING_MASK 0x3 #define XTENSA_TBFLAG_EXCM 0x4 #define XTENSA_TBFLAG_LITBASE 0x8 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 51b7d8d1bf..2559ce38ee 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -25,6 +25,14 @@ #include "cpu.h" #include "exec/exec-all.h" =20 +int cpu_mmu_index(CPUAlphaState *env, bool ifetch) +{ + int ret =3D env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_= IDX; + if (env->flags & ENV_FLAG_PAL_MODE) { + ret =3D MMU_KERNEL_IDX; + } + return ret; +} =20 static void alpha_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 374ef523da..6f640b0e78 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -49,6 +49,11 @@ #include "fpu/softfloat.h" #include "cpregs.h" =20 +int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + return EX_TBFLAG_ANY(env->hflags, MMUIDX); +} + static void arm_cpu_set_pc(CPUState *cs, vaddr value) { ARMCPU *cpu =3D ARM_CPU(cs); diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 14d8b9d1f0..38263d07dd 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -26,6 +26,11 @@ #include "disas/dis-asm.h" #include "tcg/debug-assert.h" =20 +int cpu_mmu_index(CPUAVRState *env, bool ifetch) +{ + return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; +} + static void avr_cpu_set_pc(CPUState *cs, vaddr value) { AVRCPU *cpu =3D AVR_CPU(cs); diff --git a/target/cris/cpu.c b/target/cris/cpu.c index be4a44c218..553742a068 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -27,6 +27,10 @@ #include "cpu.h" #include "mmu.h" =20 +int cpu_mmu_index(CPUCRISState *env, bool ifetch) +{ + return !!(env->pregs[PR_CCS] & U_FLAG); +} =20 static void cris_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 1adc11b713..bf7c901705 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -26,6 +26,15 @@ #include "tcg/tcg.h" #include "exec/gdbstub.h" =20 +int cpu_mmu_index(CPUHexagonState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else +#error System mode not supported on Hexagon yet +#endif +} + static void hexagon_v67_cpu_init(Object *obj) { } static void hexagon_v68_cpu_init(Object *obj) { } static void hexagon_v69_cpu_init(Object *obj) { } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 1644297bf8..22f031758e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -28,6 +28,18 @@ #include "fpu/softfloat.h" #include "tcg/tcg.h" =20 +int cpu_mmu_index(CPUHPPAState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + if (env->psw & (ifetch ? PSW_C : PSW_D)) { + return PRIV_TO_MMU_IDX(env->iaoq_f & 3); + } + return MMU_PHYS_IDX; /* mmu disabled */ +#endif +} + static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { HPPACPU *cpu =3D HPPA_CPU(cs); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 66ab092628..3327ecf6db 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -45,6 +45,13 @@ #include "disas/capstone.h" #include "cpu-internal.h" =20 +int cpu_mmu_index(CPUX86State *env, bool ifetch) +{ + return (env->hflags & HF_CPL_MASK) =3D=3D 3 ? MMU_USER_IDX : + (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) + ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; +} + static void x86_cpu_realizefn(DeviceState *dev, Error **errp); =20 /* Helpers for building CPUID[2] descriptors: */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index e70773c22e..c6c2760e46 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -20,6 +20,18 @@ #include "sysemu/reset.h" #include "tcg/tcg.h" =20 +int cpu_mmu_index(CPULoongArchState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_IDX_USER; +#else + if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { + return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); + } + return MMU_IDX_DA; +#endif +} + const char * const regnames[32] =3D { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 538d9473c2..74da87f07e 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -24,6 +24,11 @@ #include "migration/vmstate.h" #include "fpu/softfloat.h" =20 +int cpu_mmu_index(CPUM68KState *env, bool ifetch) +{ + return (env->sr & SR_S) =3D=3D 0 ? 1 : 0; +} + static void m68k_cpu_set_pc(CPUState *cs, vaddr value) { M68kCPU *cpu =3D M68K_CPU(cs); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bbb3335cad..f8891de41e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -32,6 +32,22 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" =20 +int cpu_mmu_index(CPUMBState *env, bool ifetch) +{ + MicroBlazeCPU *cpu =3D env_archcpu(env); + + /* Are we in nommu mode?. */ + if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { + return MMU_NOMMU_IDX; + } + + if (env->msr & MSR_UM) { + return MMU_USER_IDX; + } + return MMU_KERNEL_IDX; +} + + static const struct { const char *name; uint8_t version_id; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a0023edd43..1b5994e9a7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -35,6 +35,20 @@ #include "semihosting/semihost.h" #include "fpu_helper.h" =20 +int hflags_mmu_index(uint32_t hflags) +{ + if (hflags & MIPS_HFLAG_ERL) { + return 3; /* ERL */ + } else { + return hflags & MIPS_HFLAG_KSU; + } +} + +int cpu_mmu_index(CPUMIPSState *env, bool ifetch) +{ + return hflags_mmu_index(env->hflags); +} + const char regnames[32][3] =3D { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 15e499f828..887a9bf786 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -26,6 +26,12 @@ #include "gdbstub/helpers.h" #include "hw/qdev-properties.h" =20 +int cpu_mmu_index(CPUNios2State *env, bool ifetch) +{ + return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : + MMU_SUPERVISOR_IDX; +} + static void nios2_cpu_set_pc(CPUState *cs, vaddr value) { Nios2CPU *cpu =3D NIOS2_CPU(cs); diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index f5a3d5273b..5938d66da3 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -25,6 +25,18 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" =20 +int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) +{ + int ret =3D MMU_NOMMU_IDX; /* mmu is disabled */ + + if (env->sr & (ifetch ? SR_IME : SR_DME)) { + /* The mmu is enabled; test supervisor state. */ + ret =3D env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; + } + + return ret; +} + static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index e3ad8e0c27..53f1d5c370 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -27,6 +27,15 @@ #include "helper_regs.h" #include "sysemu/tcg.h" =20 +int cpu_mmu_index(CPUPPCState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) &= 7; +#endif +} + target_ulong cpu_read_xer(const CPUPPCState *env) { if (is_isa300(env)) { diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3a02079290..537a56ed27 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -33,7 +33,7 @@ #include "debug.h" #include "tcg/oversized-guest.h" =20 -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) +int cpu_mmu_index(CPURISCVState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return 0; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 4d0d3a0c8c..1ce1da0a6b 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -26,6 +26,11 @@ #include "fpu/softfloat.h" #include "tcg/debug-assert.h" =20 +int cpu_mmu_index(CPURXState *env, bool ifetch) +{ + return 0; +} + static void rx_cpu_set_pc(CPUState *cs, vaddr value) { RXCPU *cpu =3D RX_CPU(cs); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 4f7599d72c..aa574807f1 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -41,6 +41,37 @@ #define CR0_RESET 0xE0UL #define CR14_RESET 0xC2000000UL; =20 +int cpu_mmu_index(CPUS390XState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + if (!(env->psw.mask & PSW_MASK_DAT)) { + return MMU_REAL_IDX; + } + + if (ifetch) { + if ((env->psw.mask & PSW_MASK_ASC) =3D=3D PSW_ASC_HOME) { + return MMU_HOME_IDX; + } + return MMU_PRIMARY_IDX; + } + + switch (env->psw.mask & PSW_MASK_ASC) { + case PSW_ASC_PRIMARY: + return MMU_PRIMARY_IDX; + case PSW_ASC_SECONDARY: + return MMU_SECONDARY_IDX; + case PSW_ASC_HOME: + return MMU_HOME_IDX; + case PSW_ASC_ACCREG: + /* Fallthrough: access register mode is not yet supported */ + default: + abort(); + } +#endif +} + #ifndef CONFIG_USER_ONLY static bool is_early_exception_psw(uint64_t mask, uint64_t addr) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 788e41fea6..6bffe52c04 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -28,6 +28,19 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" =20 +int cpu_mmu_index(CPUSH4State *env, bool ifetch) +{ + /* + * The instruction in a RTE delay slot is fetched in privileged + * mode, but executed in user mode. + */ + if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { + return 0; + } else { + return (env->sr & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; + } +} + static void superh_cpu_set_pc(CPUState *cs, vaddr value) { SuperHCPU *cpu =3D SUPERH_CPU(cs); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 8ba96ae225..256ba2be88 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -29,6 +29,34 @@ =20 //#define DEBUG_FEATURES =20 +int cpu_mmu_index(CPUSPARCState *env, bool ifetch) +{ +#if defined(CONFIG_USER_ONLY) + return MMU_USER_IDX; +#elif !defined(TARGET_SPARC64) + if ((env->mmuregs[0] & MMU_E) =3D=3D 0) { /* MMU disabled */ + return MMU_PHYS_IDX; + } else { + return env->psrs; + } +#else + /* IMMU or DMMU disabled. */ + if (ifetch + ? (env->lsu & IMMU_E) =3D=3D 0 || (env->pstate & PS_RED) !=3D 0 + : (env->lsu & DMMU_E) =3D=3D 0) { + return MMU_PHYS_IDX; + } else if (cpu_hypervisor_mode(env)) { + return MMU_PHYS_IDX; + } else if (env->tl > 0) { + return MMU_NUCLEUS_IDX; + } else if (cpu_supervisor_mode(env)) { + return MMU_KERNEL_IDX; + } else { + return MMU_USER_IDX; + } +#endif +} + static void sparc_cpu_reset_hold(Object *obj) { CPUState *s =3D CPU(obj); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index d1477622e6..a81f37e3e4 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -24,6 +24,11 @@ #include "qemu/error-report.h" #include "tcg/debug-assert.h" =20 +int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) +{ + return 0; +} + static inline void set_feature(CPUTriCoreState *env, int feature) { env->features |=3D 1ULL << feature; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index ea1dae7390..769b3c9305 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -39,6 +39,10 @@ #include "exec/memory.h" #endif =20 +int cpu_mmu_index(CPUXtensaState *env, bool ifetch) +{ + return xtensa_get_cring(env); +} =20 static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) { --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675332; cv=none; d=zohomail.com; s=zohoarc; b=gMla57OpqvpFZe8ykmeiZ7wyG+EndB/hxMaXH9DEvR3CoM4fXL0zHtSj7LyxvVNX/Iq5/T+G39//x2Zdkl0WUKUeoX086K7W87Fy66F+oPWqYEKyZ3vtJ159mZZ4gwzdTt738YYehYUP8uUIY5haz1DUmqNM9fYAfUlKP9LrRWc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675332; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=8VbSSJ+elwAUh/3IBh5c6unmBtljyQ3plo6LsH7WdK4=; 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Fri, 19 Jan 2024 09:40:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=8VbSSJ+elwAUh/3IBh5c6unmBtljyQ3plo6LsH7WdK4=; b=FITrlALjFaKVMHTJ9yP75JbGb1 do4NHneJlsothXci4kF3y4HhYLcb8lgMYQMCEqerOYJsvFmFSCdWSgYVQf8MPho6y8fvfoaSL8oPg xAUm+1FrABt1w0SDwHw6NzO4UKUxrJpzZ0Ex2EX3yNHmlUnPwuOiHNTDLxxECrUxleYA=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 13/34] target: Uninline cpu_get_tb_cpu_state() Date: Fri, 19 Jan 2024 15:40:03 +0100 Message-ID: <20240119144024.14289-14-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675333034100005 Content-Type: text/plain; charset="utf-8" Required to compile accel/tcg/translate-all.c once for softmmu targets. The function gets quite big for some targets so uninlining makes sense. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- include/exec/cpu-common.h | 4 +++ target/alpha/cpu.h | 11 ------- target/arm/cpu.h | 3 -- target/avr/cpu.h | 18 ----------- target/cris/cpu.h | 10 ------ target/hexagon/cpu.h | 12 ------- target/hppa/cpu.h | 43 ------------------------- target/i386/cpu.h | 9 ------ target/loongarch/cpu.h | 11 ------- target/m68k/cpu.h | 16 --------- target/microblaze/cpu.h | 8 ----- target/mips/cpu.h | 9 ------ target/nios2/cpu.h | 12 ------- target/openrisc/cpu.h | 10 ------ target/ppc/cpu.h | 13 -------- target/riscv/cpu.h | 3 -- target/rx/cpu.h | 9 ------ target/s390x/cpu.h | 22 ------------- target/sh4/cpu.h | 15 --------- target/sparc/cpu.h | 35 -------------------- target/tricore/cpu.h | 12 ------- target/xtensa/cpu.h | 68 --------------------------------------- target/alpha/cpu.c | 11 +++++++ target/avr/cpu.c | 18 +++++++++++ target/cris/cpu.c | 10 ++++++ target/hexagon/cpu.c | 12 +++++++ target/hppa/cpu.c | 47 +++++++++++++++++++++++++++ target/i386/cpu.c | 9 ++++++ target/loongarch/cpu.c | 11 +++++++ target/m68k/cpu.c | 16 +++++++++ target/microblaze/cpu.c | 7 ++++ target/mips/cpu.c | 9 ++++++ target/nios2/cpu.c | 12 +++++++ target/openrisc/cpu.c | 10 ++++++ target/ppc/cpu.c | 11 +++++++ target/rx/cpu.c | 9 ++++++ target/s390x/cpu.c | 24 ++++++++++++++ target/sh4/cpu.c | 15 +++++++++ target/sparc/cpu.c | 35 ++++++++++++++++++++ target/tricore/cpu.c | 12 +++++++ target/xtensa/cpu.c | 68 +++++++++++++++++++++++++++++++++++++++ 41 files changed, 350 insertions(+), 349 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 12952c481c..b5dae4a9d6 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -70,6 +70,10 @@ unsigned int cpu_list_generation_id_get(void); */ int cpu_mmu_index(CPUArchState *env, bool ifetch); =20 +void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags); + + void tcg_flush_softmmu_tlb(CPUState *cs); void tcg_flush_jmp_cache(CPUState *cs); =20 diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e93186d50e..09937b32a2 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -452,17 +452,6 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, MemTxResult response, uintptr_t retad= dr); #endif =20 -static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *pflags =3D env->flags & ENV_FLAG_TB_MASK; -#ifdef CONFIG_USER_ONLY - *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #ifdef CONFIG_USER_ONLY /* Copied from linux ieee_swcr_to_fpcr. */ static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3dfca8f3ae..9732c836b2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3212,9 +3212,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *en= v) } #endif =20 -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); - enum { QEMU_PSCI_CONDUIT_DISABLED =3D 0, QEMU_PSCI_CONDUIT_SMC =3D 1, diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 581ba54aae..e454f3ac3c 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -183,24 +183,6 @@ enum { TB_FLAGS_SKIP =3D 2, }; =20 -static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - uint32_t flags =3D 0; - - *pc =3D env->pc_w * 2; - *cs_base =3D 0; - - if (env->fullacc) { - flags |=3D TB_FLAGS_FULL_ACCESS; - } - if (env->skip) { - flags |=3D TB_FLAGS_SKIP; - } - - *pflags =3D flags; -} - static inline int cpu_interrupts_enabled(CPUAVRState *env) { return env->sregI !=3D 0; diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 9587a2a229..1312a719b7 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -261,16 +261,6 @@ enum { =20 #include "exec/cpu-all.h" =20 -static inline void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D env->dslot | - (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG - | X_FLAG | PFIX_FLAG)); -} - #define cpu_list cris_cpu_list void cris_cpu_list(void); =20 diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 562b5c7095..8e0b7704ef 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -153,18 +153,6 @@ struct ArchCPU { =20 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) =20 -static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t hex_flags =3D 0; - *pc =3D env->gpr[HEX_REG_PC]; - *cs_base =3D 0; - if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { - hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); - } - *flags =3D hex_flags; -} - typedef HexagonCPU ArchCPU; =20 void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 3da91d41d4..088692db90 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -267,49 +267,6 @@ static inline target_ulong hppa_form_gva(CPUHPPAState = *env, uint64_t spc, #define TB_FLAG_PRIV_SHIFT 8 #define TB_FLAG_UNALIGN 0x400 =20 -static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - uint32_t flags =3D env->psw_n * PSW_N; - - /* TB lookup assumes that PC contains the complete virtual address. - If we leave space+offset separate, we'll get ITLB misses to an - incomplete virtual address. This also means that we must separate - out current cpu privilege from the low bits of IAOQ_F. */ -#ifdef CONFIG_USER_ONLY - *pc =3D env->iaoq_f & -4; - *cs_base =3D env->iaoq_b & -4; - flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#else - /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ - flags |=3D env->psw & (PSW_W | PSW_C | PSW_D); - flags |=3D (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - - *pc =3D (env->psw & PSW_C - ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) - : env->iaoq_f & -4); - *cs_base =3D env->iasq_f; - - /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise = zero - low 32-bits of CS_BASE. This will succeed for all direct branches, - which is the primary case we care about -- using goto_tb within a p= age. - Failure is indicated by a zero difference. */ - if (env->iasq_f =3D=3D env->iasq_b) { - target_sreg diff =3D env->iaoq_b - env->iaoq_f; - if (TARGET_REGISTER_BITS =3D=3D 32 || diff =3D=3D (int32_t)diff) { - *cs_base |=3D (uint32_t)diff; - } - } - if ((env->sr[4] =3D=3D env->sr[5]) - & (env->sr[4] =3D=3D env->sr[6]) - & (env->sr[4] =3D=3D env->sr[7])) { - flags |=3D TB_FLAG_SR_SAME; - } -#endif - - *pflags =3D flags; -} - target_ureg cpu_hppa_get_psw(CPUHPPAState *env); void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg); void cpu_hppa_loaded_fr0(CPUHPPAState *env); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7de2bad701..5e938fdac3 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2278,15 +2278,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *= env) #include "hw/i386/apic.h" #endif =20 -static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *cs_base =3D env->segs[R_CS].base; - *pc =3D *cs_base + env->eip; - *flags =3D env->hflags | - (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); -} - void do_cpu_init(X86CPU *cpu); =20 #define MCE_INJECT_BROADCAST 1 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index d85103c28d..ce9bdedbf0 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -449,17 +449,6 @@ static inline void set_pc(CPULoongArchState *env, uint= 64_t value) #define HW_FLAGS_EUEN_SXE 0x08 #define HW_FLAGS_VA32 0x20 =20 -static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; - *flags |=3D is_va32(env) * HW_FLAGS_VA32; -} - void loongarch_cpu_list(void); =20 #define cpu_list loongarch_cpu_list diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index da13111fd8..21c37e2267 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -596,22 +596,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr = physaddr, vaddr addr, #define TB_FLAGS_TRACE 16 #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) =20 -static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; - if (env->sr & SR_S) { - *flags |=3D TB_FLAGS_MSR_S; - *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; - *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; - } - if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { - *flags |=3D TB_FLAGS_TRACE; - } -} - void dump_mmu(CPUM68KState *env); =20 #endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 8f8b4f55d4..bdbbf2751b 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -404,14 +404,6 @@ void mb_tcg_init(void); /* Ensure there is no overlap between the two masks. */ QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); =20 -static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); - *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); -} - #if !defined(CONFIG_USER_ONLY) bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 49915af09d..6d9f95be18 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1344,15 +1344,6 @@ void itc_reconfigure(struct MIPSITUState *tag); /* helper.c */ target_ulong exception_resume_pc(CPUMIPSState *env); =20 -static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->active_tc.PC; - *cs_base =3D 0; - *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | - MIPS_HFLAG_HWRENA_ULR); -} - /** * mips_cpu_create_with_clock: * @typename: a MIPS CPU type. diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index c1d4fc6542..890d91d901 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -295,16 +295,4 @@ FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS =3D=3D 0. */ FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */ FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 =3D=3D 0. */ =20 -static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - unsigned crs =3D FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS); - - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->ctrl[CR_STATUS] & CR_STATUS_U) - | (crs ? 0 : R_TBFLAGS_CRS0_MASK) - | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK); -} - #endif /* NIOS2_CPU_H */ diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index d57f820743..bfa3d6fba6 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -366,16 +366,6 @@ static inline void cpu_set_gpr(CPUOpenRISCState *env, = int i, uint32_t val) env->shadow_gpr[0][i] =3D val; } =20 -static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) - | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) - | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); -} - static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) { return (env->sr diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index faba987dc0..46eeb78c33 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2511,19 +2511,6 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xe= r); */ #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) =20 -#ifdef CONFIG_DEBUG_TCG -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); -#else -static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->nip; - *cs_base =3D 0; - *flags =3D env->hflags; -} -#endif - G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception); G_NORETURN void raise_exception_ra(CPUPPCState *env, uint32_t exception, uintptr_t raddr); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9b0590c7d9..58ed6700de 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -627,9 +627,6 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, ta= rget_ulong vtype) return cpu->cfg.vlen >> (sew + 3 - lmul); } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - void riscv_cpu_update_mask(CPURISCVState *env); =20 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 3f5b501acf..33290e2c47 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -142,15 +142,6 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, = int rte); #define RX_CPU_IRQ 0 #define RX_CPU_FIR 1 =20 -static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); - *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); -} - static inline uint32_t rx_cpu_pack_psw(CPURXState *env) { uint32_t psw =3D 0; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 5c646cafaa..eeb10d10bd 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -348,28 +348,6 @@ extern const VMStateDescription vmstate_s390_cpu; #define MMU_HOME_IDX 2 #define MMU_REAL_IDX 3 =20 -static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - if (env->psw.addr & 1) { - /* - * Instructions must be at even addresses. - * This needs to be checked before address translation. - */ - env->int_pgm_ilen =3D 2; /* see s390_cpu_tlb_fill() */ - tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); - } - *pc =3D env->psw.addr; - *cs_base =3D env->ex_value; - *flags =3D (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; - if (env->cregs[0] & CR0_AFP) { - *flags |=3D FLAG_MASK_AFP; - } - if (env->cregs[0] & CR0_VECTOR) { - *flags |=3D FLAG_MASK_VECTOR; - } -} - /* PER bits from control register 9 */ #define PER_CR9_EVENT_BRANCH 0x80000000 #define PER_CR9_EVENT_IFETCH 0x40000000 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 218ba24333..818810769f 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -357,19 +357,4 @@ static inline void cpu_write_sr(CPUSH4State *env, targ= et_ulong sr) env->sr =3D sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); } =20 -static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - /* For a gUSA region, notice the end of the region. */ - *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; - *flags =3D env->flags - | (env->fpscr & TB_FLAG_FPSCR_MASK) - | (env->sr & TB_FLAG_SR_MASK) - | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ -#ifdef CONFIG_USER_ONLY - *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #endif /* SH4_CPU_H */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index bd24cd578c..33338f8846 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -733,41 +733,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_HYPER (1 << 7) #define TB_FLAG_ASI_SHIFT 24 =20 -static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - uint32_t flags; - *pc =3D env->pc; - *cs_base =3D env->npc; - flags =3D cpu_mmu_index(env, false); -#ifndef CONFIG_USER_ONLY - if (cpu_supervisor_mode(env)) { - flags |=3D TB_FLAG_SUPER; - } -#endif -#ifdef TARGET_SPARC64 -#ifndef CONFIG_USER_ONLY - if (cpu_hypervisor_mode(env)) { - flags |=3D TB_FLAG_HYPER; - } -#endif - if (env->pstate & PS_AM) { - flags |=3D TB_FLAG_AM_ENABLED; - } - if ((env->def.features & CPU_FEATURE_FLOAT) - && (env->pstate & PS_PEF) - && (env->fprs & FPRS_FEF)) { - flags |=3D TB_FLAG_FPU_ENABLED; - } - flags |=3D env->asi << TB_FLAG_ASI_SHIFT; -#else - if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) { - flags |=3D TB_FLAG_FPU_ENABLED; - } -#endif - *pflags =3D flags; -} - static inline bool tb_fpu_enabled(int tb_flags) { #if defined(CONFIG_USER_ONLY) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 9454b0adcd..43604f00ca 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -378,18 +378,6 @@ FIELD(TB_FLAGS, PRIV, 0, 2) void cpu_state_reset(CPUTriCoreState *s); void tricore_tcg_init(void); =20 -static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t new_flags =3D 0; - *pc =3D env->PC; - *cs_base =3D 0; - - new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, - extract32(env->PSW, 10, 2)); - *flags =3D new_flags; -} - #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU #define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 89d6b690af..0c51d2b0ec 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -721,74 +721,6 @@ static inline uint32_t xtensa_replicate_windowstart(CP= UXtensaState *env) =20 #include "exec/cpu-all.h" =20 -static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D 0; - *flags |=3D xtensa_get_ring(env); - if (env->sregs[PS] & PS_EXCM) { - *flags |=3D XTENSA_TBFLAG_EXCM; - } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { - target_ulong lend_dist =3D - env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); - - /* - * 0 in the csbase_lend field means that there may not be a loopba= ck - * for any instruction that starts inside this page. Any other val= ue - * means that an instruction that ends at this offset from the page - * start may loop back and will need loopback code to be generated. - * - * lend_dist is 0 when LEND points to the start of the page, but - * no instruction that starts inside this page may end at offset 0, - * so it's still correct. - * - * When an instruction ends at a page boundary it may only start in - * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE - * for the TB that contains this instruction. - */ - if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { - target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; - - *cs_base =3D lend_dist; - if (lbeg_off < 256) { - *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; - } - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && - (env->sregs[LITBASE] & 1)) { - *flags |=3D XTENSA_TBFLAG_LITBASE; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { - if (xtensa_get_cintlevel(env) < env->config->debug_level) { - *flags |=3D XTENSA_TBFLAG_DEBUG; - } - if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { - *flags |=3D XTENSA_TBFLAG_ICOUNT; - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { - *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && - (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { - uint32_t windowstart =3D xtensa_replicate_windowstart(env) >> - (env->sregs[WINDOW_BASE] + 1); - uint32_t w =3D ctz32(windowstart | 0x8); - - *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; - *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, - PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; - } else { - *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; - } - if (env->yield_needed) { - *flags |=3D XTENSA_TBFLAG_YIELD; - } -} - XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk); =20 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 2559ce38ee..5e468d4605 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -34,6 +34,17 @@ int cpu_mmu_index(CPUAlphaState *env, bool ifetch) return ret; } =20 +void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *pflags =3D env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void alpha_cpu_set_pc(CPUState *cs, vaddr value) { AlphaCPU *cpu =3D ALPHA_CPU(cs); diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 38263d07dd..351e127fea 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -31,6 +31,24 @@ int cpu_mmu_index(CPUAVRState *env, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } =20 +void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags =3D 0; + + *pc =3D env->pc_w * 2; + *cs_base =3D 0; + + if (env->fullacc) { + flags |=3D TB_FLAGS_FULL_ACCESS; + } + if (env->skip) { + flags |=3D TB_FLAGS_SKIP; + } + + *pflags =3D flags; +} + static void avr_cpu_set_pc(CPUState *cs, vaddr value) { AVRCPU *cpu =3D AVR_CPU(cs); diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 553742a068..8880e94a8e 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -32,6 +32,16 @@ int cpu_mmu_index(CPUCRISState *env, bool ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } =20 +void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D env->dslot | + (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG + | X_FLAG | PFIX_FLAG)); +} + static void cris_cpu_set_pc(CPUState *cs, vaddr value) { CRISCPU *cpu =3D CRIS_CPU(cs); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index bf7c901705..68b6e1a31f 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -35,6 +35,18 @@ int cpu_mmu_index(CPUHexagonState *env, bool ifetch) #endif } =20 +void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t hex_flags =3D 0; + *pc =3D env->gpr[HEX_REG_PC]; + *cs_base =3D 0; + if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); + } + *flags =3D hex_flags; +} + static void hexagon_v67_cpu_init(Object *obj) { } static void hexagon_v68_cpu_init(Object *obj) { } static void hexagon_v69_cpu_init(Object *obj) { } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 22f031758e..0103e0429b 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -40,6 +40,53 @@ int cpu_mmu_index(CPUHPPAState *env, bool ifetch) #endif } =20 +void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags =3D env->psw_n * PSW_N; + + /* + * TB lookup assumes that PC contains the complete virtual address. + * If we leave space+offset separate, we'll get ITLB misses to an + * incomplete virtual address. This also means that we must separate + * out current cpu privilege from the low bits of IAOQ_F. + */ +#ifdef CONFIG_USER_ONLY + *pc =3D env->iaoq_f & -4; + *cs_base =3D env->iaoq_b & -4; + flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#else + /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ + flags |=3D env->psw & (PSW_W | PSW_C | PSW_D); + flags |=3D (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; + + *pc =3D (env->psw & PSW_C + ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) + : env->iaoq_f & -4); + *cs_base =3D env->iasq_f; + + /* + * Insert a difference between IAOQ_B and IAOQ_F within the otherwise = zero + * low 32-bits of CS_BASE. This will succeed for all direct branches, + * which is the primary case we care about -- using goto_tb within a p= age. + * Failure is indicated by a zero difference. + */ + if (env->iasq_f =3D=3D env->iasq_b) { + target_sreg diff =3D env->iaoq_b - env->iaoq_f; + if (TARGET_REGISTER_BITS =3D=3D 32 || diff =3D=3D (int32_t)diff) { + *cs_base |=3D (uint32_t)diff; + } + } + if ((env->sr[4] =3D=3D env->sr[5]) + & (env->sr[4] =3D=3D env->sr[6]) + & (env->sr[4] =3D=3D env->sr[7])) { + flags |=3D TB_FLAG_SR_SAME; + } +#endif + + *pflags =3D flags; +} + static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { HPPACPU *cpu =3D HPPA_CPU(cs); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3327ecf6db..7baf74fb9a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -52,6 +52,15 @@ int cpu_mmu_index(CPUX86State *env, bool ifetch) ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; } =20 +void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *cs_base =3D env->segs[R_CS].base; + *pc =3D *cs_base + env->eip; + *flags =3D env->hflags | + (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); +} + static void x86_cpu_realizefn(DeviceState *dev, Error **errp); =20 /* Helpers for building CPUID[2] descriptors: */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index c6c2760e46..cc53a7e51a 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -32,6 +32,17 @@ int cpu_mmu_index(CPULoongArchState *env, bool ifetch) #endif } =20 +void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; + *flags |=3D is_va32(env) * HW_FLAGS_VA32; +} + const char * const regnames[32] =3D { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 74da87f07e..9c664cb9a8 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -29,6 +29,22 @@ int cpu_mmu_index(CPUM68KState *env, bool ifetch) return (env->sr & SR_S) =3D=3D 0 ? 1 : 0; } =20 +void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; + if (env->sr & SR_S) { + *flags |=3D TB_FLAGS_MSR_S; + *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; + *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; + } + if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { + *flags |=3D TB_FLAGS_TRACE; + } +} + static void m68k_cpu_set_pc(CPUState *cs, vaddr value) { M68kCPU *cpu =3D M68K_CPU(cs); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f8891de41e..4c270e941f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -47,6 +47,13 @@ int cpu_mmu_index(CPUMBState *env, bool ifetch) return MMU_KERNEL_IDX; } =20 +void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); + *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); +} =20 static const struct { const char *name; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 1b5994e9a7..fe93acf28f 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -49,6 +49,15 @@ int cpu_mmu_index(CPUMIPSState *env, bool ifetch) return hflags_mmu_index(env->hflags); } =20 +void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->active_tc.PC; + *cs_base =3D 0; + *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | + MIPS_HFLAG_HWRENA_ULR); +} + const char regnames[32][3] =3D { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 887a9bf786..868d75b165 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -32,6 +32,18 @@ int cpu_mmu_index(CPUNios2State *env, bool ifetch) MMU_SUPERVISOR_IDX; } =20 +void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + unsigned crs =3D FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS); + + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D (env->ctrl[CR_STATUS] & CR_STATUS_U) + | (crs ? 0 : R_TBFLAGS_CRS0_MASK) + | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK); +} + static void nios2_cpu_set_pc(CPUState *cs, vaddr value) { Nios2CPU *cpu =3D NIOS2_CPU(cs); diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 5938d66da3..36d97d249d 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -37,6 +37,16 @@ int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) return ret; } =20 +void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); +} + static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index 53f1d5c370..046732857b 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -36,6 +36,17 @@ int cpu_mmu_index(CPUPPCState *env, bool ifetch) #endif } =20 +/* debug version defined in helper_hregs */ +#ifndef CONFIG_DEBUG_TCG +void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->nip; + *cs_base =3D 0; + *flags =3D env->hflags; +} +#endif + target_ulong cpu_read_xer(const CPUPPCState *env) { if (is_isa300(env)) { diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 1ce1da0a6b..688a70b707 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -31,6 +31,15 @@ int cpu_mmu_index(CPURXState *env, bool ifetch) return 0; } =20 +void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); + *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); +} + static void rx_cpu_set_pc(CPUState *cs, vaddr value) { RXCPU *cpu =3D RX_CPU(cs); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index aa574807f1..51c707ea12 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -72,6 +72,30 @@ int cpu_mmu_index(CPUS390XState *env, bool ifetch) #endif } =20 +void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + if (env->psw.addr & 1) { + /* + * Instructions must be at even addresses. + * This needs to be checked before address translation. + */ + env->int_pgm_ilen =3D 2; /* see s390_cpu_tlb_fill() */ +#ifdef CONFIG_TCG + tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); +#endif + } + *pc =3D env->psw.addr; + *cs_base =3D env->ex_value; + *flags =3D (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; + if (env->cregs[0] & CR0_AFP) { + *flags |=3D FLAG_MASK_AFP; + } + if (env->cregs[0] & CR0_VECTOR) { + *flags |=3D FLAG_MASK_VECTOR; + } +} + #ifndef CONFIG_USER_ONLY static bool is_early_exception_psw(uint64_t mask, uint64_t addr) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 6bffe52c04..ea7f13612e 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -41,6 +41,21 @@ int cpu_mmu_index(CPUSH4State *env, bool ifetch) } } =20 +void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + /* For a gUSA region, notice the end of the region. */ + *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; + *flags =3D env->flags + | (env->fpscr & TB_FLAG_FPSCR_MASK) + | (env->sr & TB_FLAG_SR_MASK) + | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ +#ifdef CONFIG_USER_ONLY + *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void superh_cpu_set_pc(CPUState *cs, vaddr value) { SuperHCPU *cpu =3D SUPERH_CPU(cs); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 256ba2be88..a6af3fd9ee 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -57,6 +57,41 @@ int cpu_mmu_index(CPUSPARCState *env, bool ifetch) #endif } =20 +void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags; + *pc =3D env->pc; + *cs_base =3D env->npc; + flags =3D cpu_mmu_index(env, false); +#ifndef CONFIG_USER_ONLY + if (cpu_supervisor_mode(env)) { + flags |=3D TB_FLAG_SUPER; + } +#endif +#ifdef TARGET_SPARC64 +#ifndef CONFIG_USER_ONLY + if (cpu_hypervisor_mode(env)) { + flags |=3D TB_FLAG_HYPER; + } +#endif + if (env->pstate & PS_AM) { + flags |=3D TB_FLAG_AM_ENABLED; + } + if ((env->def.features & CPU_FEATURE_FLOAT) + && (env->pstate & PS_PEF) + && (env->fprs & FPRS_FEF)) { + flags |=3D TB_FLAG_FPU_ENABLED; + } + flags |=3D env->asi << TB_FLAG_ASI_SHIFT; +#else + if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) { + flags |=3D TB_FLAG_FPU_ENABLED; + } +#endif + *pflags =3D flags; +} + static void sparc_cpu_reset_hold(Object *obj) { CPUState *s =3D CPU(obj); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index a81f37e3e4..f8bf10569a 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -29,6 +29,18 @@ int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) return 0; } =20 +void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t new_flags =3D 0; + *pc =3D env->PC; + *cs_base =3D 0; + + new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, + extract32(env->PSW, 10, 2)); + *flags =3D new_flags; +} + static inline void set_feature(CPUTriCoreState *env, int feature) { env->features |=3D 1ULL << feature; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 769b3c9305..2c76ba86cd 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -44,6 +44,74 @@ int cpu_mmu_index(CPUXtensaState *env, bool ifetch) return xtensa_get_cring(env); } =20 +void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D 0; + *flags |=3D xtensa_get_ring(env); + if (env->sregs[PS] & PS_EXCM) { + *flags |=3D XTENSA_TBFLAG_EXCM; + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { + target_ulong lend_dist =3D + env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); + + /* + * 0 in the csbase_lend field means that there may not be a loopba= ck + * for any instruction that starts inside this page. Any other val= ue + * means that an instruction that ends at this offset from the page + * start may loop back and will need loopback code to be generated. + * + * lend_dist is 0 when LEND points to the start of the page, but + * no instruction that starts inside this page may end at offset 0, + * so it's still correct. + * + * When an instruction ends at a page boundary it may only start in + * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE + * for the TB that contains this instruction. + */ + if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { + target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; + + *cs_base =3D lend_dist; + if (lbeg_off < 256) { + *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; + } + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && + (env->sregs[LITBASE] & 1)) { + *flags |=3D XTENSA_TBFLAG_LITBASE; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { + if (xtensa_get_cintlevel(env) < env->config->debug_level) { + *flags |=3D XTENSA_TBFLAG_DEBUG; + } + if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { + *flags |=3D XTENSA_TBFLAG_ICOUNT; + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { + *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && + (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { + uint32_t windowstart =3D xtensa_replicate_windowstart(env) >> + (env->sregs[WINDOW_BASE] + 1); + uint32_t w =3D ctz32(windowstart | 0x8); + + *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; + *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, + PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; + } else { + *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; + } + if (env->yield_needed) { + *flags |=3D XTENSA_TBFLAG_YIELD; + } +} + static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) { XtensaCPU *cpu =3D XTENSA_CPU(cs); --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=0BDn6bG9vf0A3hTWpVATIe+zc3eDiyN2r2gdXqUqrRY=; b=LP4LQt0qCBoEwceF+2YXu85Oib gKYIv1KXSFYBl7IF5ID2wCT62qT8hVzMmOoGExbAVH19vzHsnnAqsaN7T8Qd1PsgWxtMgELfTRM51 I4UP4TtAkPghN1IsvcFPL0H8zXIQtvVBOpNaLNFfej4RlW/kJ2Z3Sk0b2/RYCDA0GOjs=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 14/34] exec: [CPUTLB] Move PAGE_* macros to common header Date: Fri, 19 Jan 2024 15:40:04 +0100 Message-ID: <20240119144024.14289-15-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675519785100003 Content-Type: text/plain; charset="utf-8" These don't vary across targets and are used in soon-to-be common code (cputlb.c). Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- include/exec/cpu-all.h | 24 ------------------------ include/exec/cpu-common.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 24 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 483e762f05..219544bad8 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -166,34 +166,10 @@ static inline void stl_phys_notdirty(AddressSpace *as= , hwaddr addr, uint32_t val # error Need to use TARGET_PAGE_BITS_VARY on system mode #endif =20 -/* same as PROT_xxx */ -#define PAGE_READ 0x0001 -#define PAGE_WRITE 0x0002 -#define PAGE_EXEC 0x0004 -#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) -#define PAGE_VALID 0x0008 -/* - * Original state of the write flag (used when tracking self-modifying cod= e) - */ -#define PAGE_WRITE_ORG 0x0010 -/* - * Invalidate the TLB entry immediately, helpful for s390x - * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs= () - */ -#define PAGE_WRITE_INV 0x0020 -/* For use with page_set_flags: page is being replaced; target_data cleare= d. */ -#define PAGE_RESET 0x0040 -/* For linux-user, indicates that the page is MAP_ANON. */ -#define PAGE_ANON 0x0080 - #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ #define PAGE_RESERVED 0x0100 #endif -/* Target-specific bits that will be used via page_get_flags(). */ -#define PAGE_TARGET_1 0x0200 -#define PAGE_TARGET_2 0x0400 - /* * For linux-user, indicates that the page is mapped with the same semanti= cs * in both guest and host. diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index b5dae4a9d6..63bc0ad150 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -234,4 +234,34 @@ G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, ui= ntptr_t pc); G_NORETURN void cpu_loop_exit(CPUState *cpu); G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); =20 +/* same as PROT_xxx */ +#define PAGE_READ 0x0001 +#define PAGE_WRITE 0x0002 +#define PAGE_EXEC 0x0004 +#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) +#define PAGE_VALID 0x0008 +/* + * Original state of the write flag (used when tracking self-modifying cod= e) + */ +#define PAGE_WRITE_ORG 0x0010 +/* + * Invalidate the TLB entry immediately, helpful for s390x + * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs= () + */ +#define PAGE_WRITE_INV 0x0020 +/* For use with page_set_flags: page is being replaced; target_data cleare= d. */ +#define PAGE_RESET 0x0040 +/* For linux-user, indicates that the page is MAP_ANON. */ +#define PAGE_ANON 0x0080 + +/* Target-specific bits that will be used via page_get_flags(). */ +#define PAGE_TARGET_1 0x0200 +#define PAGE_TARGET_2 0x0400 + +/* + * For linux-user, indicates that the page is mapped with the same semanti= cs + * in both guest and host. + */ +#define PAGE_PASSTHROUGH 0x0800 + #endif /* CPU_COMMON_H */ --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675290; cv=none; d=zohomail.com; s=zohoarc; b=moULbrYQI603tQw5rPZFpGoCUe1NGtjOGZAXCSf1XM2BL1l2f9P0ErelI3uxmVFYawl7G+TpQKuVRxstVgtkFSCtULMQsLtQot8mwKcST4fZxqhaCmy5H6MllD7ztQvDU0zwfbCHdIpzG7OU7g0+AvyheJQ4tMGpnXNBgN7GMcw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675290; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=VbhZY2Okth22bd+NRvxa9PZqSda0T+iKQ/d0QwiWpEU=; b=TeyefJ+x4/0lpgabdBRN36jcNu2mahTC79CjS+sEaG3Gp1Dp8NiORwwkm9k/MiapvXJ2Rwcp4EfWkYpHKJCbQd1TrkA+NjpxMLVcutQ6LI/8Im4w+kbNlv2FbW3FC/jC0klzB9ZFncgQuNO/ateEH1LaCjxvcvE1bjW0Zh5Skl4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170567529033620.525773448683708; Fri, 19 Jan 2024 06:41:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQq35-0005xS-2h; Fri, 19 Jan 2024 09:40:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2q-0005ps-72 for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:34 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2l-0003t7-CX for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=VbhZY2Okth22bd+NRvxa9PZqSda0T+iKQ/d0QwiWpEU=; b=JNGjbhuBAvMMZbtiw28DGVstgl Oy/NXXJBeyx5BmTb1rGywq5JRdm4unkIJzt1+Xl2sUtvUVSFV7HGBoOcrnX5umVlZ41nbn/8fkRPx sf0jdPE2ByiCaQLlk+9n0q3ELmvz8TBJC1kL/gxiLdctDq9+xJpa5h2JaoMb0fRZ/6f8=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 15/34] exec: [CPUTLB] Move TLB_*/tlb_*() to common header Date: Fri, 19 Jan 2024 15:40:05 +0100 Message-ID: <20240119144024.14289-16-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675290786100003 Content-Type: text/plain; charset="utf-8" TLB_* macros and tlb_*() functions are target independent, move to cpu-comm= on.h. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- include/exec/cpu-all.h | 81 -------------------------------------- include/exec/cpu-common.h | 83 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+), 81 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 219544bad8..968fbd4d16 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -295,87 +295,6 @@ CPUArchState *cpu_copy(CPUArchState *env); | CPU_INTERRUPT_TGT_EXT_3 \ | CPU_INTERRUPT_TGT_EXT_4) =20 -#ifdef CONFIG_USER_ONLY - -/* - * Allow some level of source compatibility with softmmu. We do not - * support any of the more exotic features, so only invalid pages may - * be signaled by probe_access_flags(). - */ -#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) -#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) -#define TLB_WATCHPOINT 0 - -#else - -/* - * Flags stored in the low bits of the TLB virtual address. - * These are defined so that fast path ram access is all zeros. - * The flags all must be between TARGET_PAGE_BITS and - * maximum address alignment bit. - * - * Use TARGET_PAGE_BITS_MIN so that these bits are constant - * when TARGET_PAGE_BITS_VARY is in effect. - * - * The count, if not the placement of these bits is known - * to tcg/tcg-op-ldst.c, check_max_alignment(). - */ -/* Zero if TLB entry is valid. */ -#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) -/* Set if TLB entry references a clean RAM page. The iotlb entry will - contain the page physical address. */ -#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) -/* Set if TLB entry is an IO callback. */ -#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) -/* Set if TLB entry writes ignored. */ -#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4)) -/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ -#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) - -/* - * Use this mask to check interception with an alignment mask - * in a TCG backend. - */ -#define TLB_FLAGS_MASK \ - (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ - | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) - -/* - * Flags stored in CPUTLBEntryFull.slow_flags[x]. - * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x]. - */ -/* Set if TLB entry requires byte swap. */ -#define TLB_BSWAP (1 << 0) -/* Set if TLB entry contains a watchpoint. */ -#define TLB_WATCHPOINT (1 << 1) - -#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT) - -/** - * tlb_hit_page: return true if page aligned @addr is a hit against the - * TLB entry @tlb_addr - * - * @addr: virtual address to test (must be page aligned) - * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) - */ -static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr) -{ - return addr =3D=3D (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); -} - -/** - * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr - * - * @addr: virtual address to test (need not be page aligned) - * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) - */ -static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) -{ - return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); -} - -#endif /* !CONFIG_USER_ONLY */ - /* accel/tcg/cpu-exec.c */ int cpu_exec(CPUState *cpu); =20 diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 63bc0ad150..d3c8b2cf55 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -41,6 +41,89 @@ extern const TargetPageBits target_page; #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) #endif =20 +#ifdef CONFIG_USER_ONLY + +/* + * Allow some level of source compatibility with softmmu. We do not + * support any of the more exotic features, so only invalid pages may + * be signaled by probe_access_flags(). + */ +#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) +#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) +#define TLB_WATCHPOINT 0 + +#else + +/* + * Flags stored in the low bits of the TLB virtual address. + * These are defined so that fast path ram access is all zeros. + * The flags all must be between TARGET_PAGE_BITS and + * maximum address alignment bit. + * + * Use TARGET_PAGE_BITS_MIN so that these bits are constant + * when TARGET_PAGE_BITS_VARY is in effect. + * + * The count, if not the placement of these bits is known + * to tcg/tcg-op-ldst.c, check_max_alignment(). + */ +/* Zero if TLB entry is valid. */ +#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) +/* + * Set if TLB entry references a clean RAM page. The iotlb entry will + * contain the page physical address. + */ +#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) +/* Set if TLB entry is an IO callback. */ +#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) +/* Set if TLB entry writes ignored. */ +#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4)) +/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ +#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) + +/* + * Use this mask to check interception with an alignment mask + * in a TCG backend. + */ +#define TLB_FLAGS_MASK \ + (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ + | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) + +/* + * Flags stored in CPUTLBEntryFull.slow_flags[x]. + * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x]. + */ +/* Set if TLB entry requires byte swap. */ +#define TLB_BSWAP (1 << 0) +/* Set if TLB entry contains a watchpoint. */ +#define TLB_WATCHPOINT (1 << 1) + +#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT) + +/** + * tlb_hit_page: return true if page aligned @addr is a hit against the + * TLB entry @tlb_addr + * + * @addr: virtual address to test (must be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr) +{ + return addr =3D=3D (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); +} + +/** + * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr + * + * @addr: virtual address to test (need not be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) +{ + return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); +} + +#endif /* !CONFIG_USER_ONLY */ + void cpu_exec_init_all(void); void cpu_exec_step_atomic(CPUState *cpu); =20 --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675599; cv=none; d=zohomail.com; s=zohoarc; b=dw/2v9peQ86rssmVqh0xOV4crd/DNn5DBnR5FwjmKkDieSnmdN3tX5614WK02w3MUClNJvVFXkd45qMEZj5KhcnbcQYLBqWBNWWcBapDqI0VYsFiAs0zwiHTTfKkhIFiQIAPtYjxlwyQk27d4uhPBQ/fANb0s9wZ3qY+V0Txsr0= ARC-Message-Signature: i=1; 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To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 16/34] exec: [CPUTLB] Move cpu_*()/cpu_env() to common header Date: Fri, 19 Jan 2024 15:40:06 +0100 Message-ID: <20240119144024.14289-17-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675600540100005 Content-Type: text/plain; charset="utf-8" Functions are target independent. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- include/exec/cpu-all.h | 25 ------------------------- include/exec/cpu-common.h | 25 +++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 968fbd4d16..4778976c4b 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -295,33 +295,8 @@ CPUArchState *cpu_copy(CPUArchState *env); | CPU_INTERRUPT_TGT_EXT_3 \ | CPU_INTERRUPT_TGT_EXT_4) =20 -/* accel/tcg/cpu-exec.c */ -int cpu_exec(CPUState *cpu); - /* Validate correct placement of CPUArchState. */ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) !=3D 0); QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) !=3D sizeof(CPUState)); =20 -/** - * env_archcpu(env) - * @env: The architecture environment - * - * Return the ArchCPU associated with the environment. - */ -static inline ArchCPU *env_archcpu(CPUArchState *env) -{ - return (void *)env - sizeof(CPUState); -} - -/** - * env_cpu(env) - * @env: The architecture environment - * - * Return the CPUState associated with the environment. - */ -static inline CPUState *env_cpu(CPUArchState *env) -{ - return (void *)env - sizeof(CPUState); -} - #endif /* CPU_ALL_H */ diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index d3c8b2cf55..25e50aaa37 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -347,4 +347,29 @@ G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, u= intptr_t pc); */ #define PAGE_PASSTHROUGH 0x0800 =20 +/* accel/tcg/cpu-exec.c */ +int cpu_exec(CPUState *cpu); + +/** + * env_archcpu(env) + * @env: The architecture environment + * + * Return the ArchCPU associated with the environment. + */ +static inline ArchCPU *env_archcpu(CPUArchState *env) +{ + return (void *)env - sizeof(CPUState); +} + +/** + * env_cpu(env) + * @env: The architecture environment + * + * Return the CPUState associated with the environment. + */ +static inline CPUState *env_cpu(CPUArchState *env) +{ + return (void *)env - sizeof(CPUState); +} + #endif /* CPU_COMMON_H */ --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=na16a3kkbbDiLaCoxLNStnzoqPivBaqVHjAABny5AW8=; b=wBtvCYVIMYuSebIS6/omyghrtp gBXa74s7midl/DiGwBoREI5CYN1FIhogfkWJEtHDFkzrImB01LD4MCQGxMHzGU+JTFGG4q5lU09Bg nDeJW3tVCjrTVSRARXf53+vL8VmQ/H+9npJDlf6TekMahDyZHN4OYVw8dxMtL2v/cL6I=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 17/34] hw/core: [CPUTLB] Move target specifics to end of TCGCPUOps Date: Fri, 19 Jan 2024 15:40:07 +0100 Message-ID: <20240119144024.14289-18-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675535935100003 Content-Type: text/plain; charset="utf-8" TCGCPUOps contains an extra function pointer when included with NEED_CPU_H, these are moved from the middle to the end of the struct. As such offsets to target independent function pointers don't vary in target specific and independent code. [Move target specfic fields to separate struct?] Signed-off-by: Anton Johansson --- include/hw/core/tcg-cpu-ops.h | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 479713a36e..feb849051f 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -49,21 +49,6 @@ struct TCGCPUOps { /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); =20 -#ifdef NEED_CPU_H -#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386) - /** - * @fake_user_interrupt: Callback for 'fake exception' handling. - * - * Simulate 'fake exception' which will be handled outside the - * cpu execution loop (hack for x86 user mode). - */ - void (*fake_user_interrupt)(CPUState *cpu); -#else - /** - * @do_interrupt: Callback for interrupt handling. - */ - void (*do_interrupt)(CPUState *cpu); -#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ #ifdef CONFIG_USER_ONLY /** * record_sigsegv: @@ -171,8 +156,25 @@ struct TCGCPUOps { bool (*io_recompile_replay_branch)(CPUState *cpu, const TranslationBlock *tb); #endif /* !CONFIG_USER_ONLY */ + +#ifdef NEED_CPU_H +#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386) + /** + * @fake_user_interrupt: Callback for 'fake exception' handling. + * + * Simulate 'fake exception' which will be handled outside the + * cpu execution loop (hack for x86 user mode). + */ + void (*fake_user_interrupt)(CPUState *cpu); +#else + /** + * @do_interrupt: Callback for interrupt handling. + */ + void (*do_interrupt)(CPUState *cpu); +#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ #endif /* NEED_CPU_H */ =20 + }; =20 #if defined(CONFIG_USER_ONLY) --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675366; cv=none; d=zohomail.com; s=zohoarc; b=knBNtKADcheyQb8SIfx5sSfPlR8sG9WkRJgoBHEVGe+ObHdqVq+8L1cY68Mova//9d8bZebq07ngG3N88Q97VN+lYxrDrmba3eQkKyEsX9OerSfQWRiSs+3QZMUgG0uFN4NZsUpLoW/ZmJyPzbUa6J59NKlKkq0FIMqZeKMcdzM= ARC-Message-Signature: i=1; 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To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 18/34] accel/stubs: [CPUTLB] Move xen.h stubs to xen-stub.c Date: Fri, 19 Jan 2024 15:40:08 +0100 Message-ID: <20240119144024.14289-19-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675367121100007 Content-Type: text/plain; charset="utf-8" Makes xen.h header independent of softmmu target. Note: CONFIG_XEN_IS_POSSIBLE is only used define stubs in xen.h and optimize xen_enabled(). Required by cpu_physical_memory_set_dirty_range() in ram_addr.h. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- include/sysemu/xen.h | 27 --------------------------- accel/stubs/xen-stub.c | 12 ++++++++++++ 2 files changed, 12 insertions(+), 27 deletions(-) diff --git a/include/sysemu/xen.h b/include/sysemu/xen.h index bc13ad5692..838bb5a003 100644 --- a/include/sysemu/xen.h +++ b/include/sysemu/xen.h @@ -12,16 +12,6 @@ =20 #include "exec/cpu-common.h" =20 -#ifdef NEED_CPU_H -# ifdef CONFIG_XEN -# define CONFIG_XEN_IS_POSSIBLE -# endif -#else -# define CONFIG_XEN_IS_POSSIBLE -#endif - -#ifdef CONFIG_XEN_IS_POSSIBLE - extern bool xen_allowed; =20 #define xen_enabled() (xen_allowed) @@ -32,21 +22,4 @@ void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size, struct MemoryRegion *mr, Error **errp); #endif =20 -#else /* !CONFIG_XEN_IS_POSSIBLE */ - -#define xen_enabled() 0 -#ifndef CONFIG_USER_ONLY -static inline void xen_hvm_modified_memory(ram_addr_t start, ram_addr_t le= ngth) -{ - /* nothing */ -} -static inline void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size, - MemoryRegion *mr, Error **errp) -{ - g_assert_not_reached(); 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To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 19/34] accel/tcg: [CPUTLB] Use TCGContext.addr_type instead of TARGET_LONG_BITS Date: Fri, 19 Jan 2024 15:40:09 +0100 Message-ID: <20240119144024.14289-20-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675505684100006 Content-Type: text/plain; charset="utf-8" [NOTE: We could also use target_long_bits(), which is introduced later] Signed-off-by: Anton Johansson --- include/exec/cpu_ldst.h | 31 ++++++++++++++++--------------- accel/tcg/cputlb.c | 34 ++++++++++++++++++++-------------- 2 files changed, 36 insertions(+), 29 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 24fe322d72..553e0119f9 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -340,7 +340,7 @@ static inline void clear_helper_retaddr(void) =20 #else =20 -#include "tcg/oversized-guest.h" +#include "tcg-target-reg-bits.h" =20 static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry, MMUAccessType access_type) @@ -353,20 +353,21 @@ static inline uint64_t tlb_read_idx(const CPUTLBEntry= *entry, QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=3D MMU_INST_FETCH * sizeof(uint64_t)); =20 -#if TARGET_LONG_BITS =3D=3D 32 - /* Use qatomic_read, in case of addr_write; only care about low bits. = */ - const uint32_t *ptr =3D (uint32_t *)&entry->addr_idx[access_type]; - ptr +=3D HOST_BIG_ENDIAN; - return qatomic_read(ptr); -#else - const uint64_t *ptr =3D &entry->addr_idx[access_type]; -# if TCG_OVERSIZED_GUEST - return *ptr; -# else - /* ofs might correspond to .addr_write, so use qatomic_read */ - return qatomic_read(ptr); -# endif -#endif + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + /* Use qatomic_read, in case of addr_write; only care about low bi= ts. */ + const uint32_t *ptr =3D (uint32_t *)&entry->addr_idx[access_type]; + ptr +=3D HOST_BIG_ENDIAN; + return qatomic_read(ptr); + } else { + const uint64_t *ptr =3D &entry->addr_idx[access_type]; + if (TCG_TARGET_REG_BITS =3D=3D 32) { + /* Oversized guest */ + return *ptr; + } else { + /* ofs might correspond to .addr_write, so use qatomic_read */ + return qatomic_read(ptr); + } + } } =20 static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 449c86301e..967d5da6d4 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -41,7 +41,7 @@ #include "qemu/plugin-memory.h" #endif #include "tcg/tcg-ldst.h" -#include "tcg/oversized-guest.h" +#include "tcg-target-reg-bits.h" =20 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ @@ -815,12 +815,13 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr a= ddr, unsigned bits) { TLBFlushRangeData d; + const unsigned long_bits =3D (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) = ? 32 : 64; =20 /* * If all bits are significant, and len is small, * this devolves to tlb_flush_page. */ - if (bits >=3D TARGET_LONG_BITS && len <=3D TARGET_PAGE_SIZE) { + if (bits >=3D long_bits && len <=3D TARGET_PAGE_SIZE) { tlb_flush_page_by_mmuidx(cpu, addr, idxmap); return; } @@ -858,12 +859,13 @@ void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src= _cpu, { TLBFlushRangeData d; CPUState *dst_cpu; + const unsigned long_bits =3D (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) = ? 32 : 64; =20 /* * If all bits are significant, and len is small, * this devolves to tlb_flush_page. */ - if (bits >=3D TARGET_LONG_BITS && len <=3D TARGET_PAGE_SIZE) { + if (bits >=3D long_bits && len <=3D TARGET_PAGE_SIZE) { tlb_flush_page_by_mmuidx_all_cpus(src_cpu, addr, idxmap); return; } @@ -908,12 +910,13 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUSta= te *src_cpu, { TLBFlushRangeData d, *p; CPUState *dst_cpu; + const unsigned long_bits =3D (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) = ? 32 : 64; =20 /* * If all bits are significant, and len is small, * this devolves to tlb_flush_page. */ - if (bits >=3D TARGET_LONG_BITS && len <=3D TARGET_PAGE_SIZE) { + if (bits >=3D long_bits && len <=3D TARGET_PAGE_SIZE) { tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap); return; } @@ -995,16 +998,19 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry = *tlb_entry, addr &=3D TARGET_PAGE_MASK; addr +=3D tlb_entry->addend; if ((addr - start) < length) { -#if TARGET_LONG_BITS =3D=3D 32 - uint32_t *ptr_write =3D (uint32_t *)&tlb_entry->addr_write; - ptr_write +=3D HOST_BIG_ENDIAN; - qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY); -#elif TCG_OVERSIZED_GUEST - tlb_entry->addr_write |=3D TLB_NOTDIRTY; -#else - qatomic_set(&tlb_entry->addr_write, - tlb_entry->addr_write | TLB_NOTDIRTY); -#endif + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + /* 32-bit */ + uint32_t *ptr_write =3D (uint32_t *)&tlb_entry->addr_write; + ptr_write +=3D HOST_BIG_ENDIAN; + qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY); + } else if (TCG_TARGET_REG_BITS =3D=3D 32) { + /* Oversized guest */ + tlb_entry->addr_write |=3D TLB_NOTDIRTY; + } else { + /* 64-bit */ + qatomic_set(&tlb_entry->addr_write, + tlb_entry->addr_write | TLB_NOTDIRTY); + } } } } --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675503; cv=none; d=zohomail.com; s=zohoarc; b=Rvx1wo2DFMtSLuvQqW20KJzw4CkMngEX+R7H6Z7Ms84yKMQsixxDE8SMTXxe+fJRvp29kgVpySwbSXuSkWc1hgO5hc2g3uAoGJNYN55KQMd8oSLeS5g4UYmBgW1dry3xGLyn7dQTVl3WB/iFwq5RtCiqv8ggglDMeSFBuLLAL8I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675503; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Fri, 19 Jan 2024 09:40:35 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2q-0003uI-M2 for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=YJQzwu19OPpvIidAvu7G/e2Vj48Qe6oY7CMLaKgxcJk=; b=gsJOzcWSu04HVvEh2TvJSsa+7/ pQBHVj/IlD/ihQ9KUpUElPhueBPHYK/dumOoUA7NEYEyMfpTEQ9ZxibRySIp7KrEpo+ZvmIZoqFD7 AN+yJ3JyV6ti8ZUW1KZsBWD59Rk/Ltu0+x0cnfzo1eHutFxjzdDZKbDJcT2k1EORh5Nc=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 20/34] accel/tcg: [CPUTLB] Use TCGContext.guest_mo for memory ordering Date: Fri, 19 Jan 2024 15:40:10 +0100 Message-ID: <20240119144024.14289-21-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675505648100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Anton Johansson --- accel/tcg/internal-target.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 4e36cf858e..3bcd1bbc84 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -9,8 +9,9 @@ #ifndef ACCEL_TCG_INTERNAL_TARGET_H #define ACCEL_TCG_INTERNAL_TARGET_H =20 -#include "exec/exec-all.h" +#include "exec/exec-common.h" #include "exec/translate-all.h" +#include "tcg/tcg.h" =20 /* * Access to the various translations structures need to be serialised @@ -108,12 +109,8 @@ extern bool one_insn_per_tb; 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To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 21/34] accel/tcg: [CPUTLB] Use tcg_ctx->tlb_dyn_max_bits Date: Fri, 19 Jan 2024 15:40:11 +0100 Message-ID: <20240119144024.14289-22-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675284481100001 Content-Type: text/plain; charset="utf-8" CPU_TLB_DYN_MAX_BITS depends on TARGET_VIRT_ADDR_SPACE_BITS on 64-bit hosts, and is not yet target independent. Signed-off-by: Anton Johansson --- accel/tcg/cputlb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 967d5da6d4..42be5b6289 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -172,7 +172,7 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPU= TLBDescFast *fast, rate =3D desc->window_max_entries * 100 / old_size; =20 if (rate > 70) { - new_size =3D MIN(old_size << 1, 1 << CPU_TLB_DYN_MAX_BITS); + new_size =3D MIN(old_size << 1, 1 << tcg_ctx->tlb_dyn_max_bits); } else if (rate < 30 && window_expired) { size_t ceil =3D pow2ceil(desc->window_max_entries); size_t expected_rate =3D desc->window_max_entries * 100 / ceil; --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705675431257936.2147134503261; Fri, 19 Jan 2024 06:43:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQq30-0005tb-Ck; Fri, 19 Jan 2024 09:40:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2y-0005sf-5w for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:40 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2t-0003uY-02 for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; 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charset="utf-8" These macros are only used for softmmu targets and only used in cputlb.c, move definitions there. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- include/exec/cpu-defs.h | 3 --- accel/tcg/cputlb.c | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index e8ccbe4bef..4b369e39b0 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -55,9 +55,6 @@ #include "exec/target_long.h" =20 #if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG) -#define CPU_TLB_DYN_MIN_BITS 6 -#define CPU_TLB_DYN_DEFAULT_BITS 8 - # if HOST_LONG_BITS =3D=3D 32 /* Make sure we do not require a double-word shift for the TLB load */ # define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 42be5b6289..a75a52d141 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -43,6 +43,9 @@ #include "tcg/tcg-ldst.h" #include "tcg-target-reg-bits.h" =20 +#define CPU_TLB_DYN_MIN_BITS 6 +#define CPU_TLB_DYN_DEFAULT_BITS 8 + /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ /* #define DEBUG_TLB_LOG */ --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=rdilRHXdipVzaTbJMyWHjDmlzpXjZtgUBcB3zkXeQlY=; b=rM4cT54P+Z6yYOLD/vUNrxovbV NSHbgbfLD+oQHnbrBsQfPrpS2FPTJmOBdkcs/VHT4nTrrkU2ycmE9eqO1VdufksdOQdl6dbGlDVtm H3O8sSqaezdVJwi9o2RSTRQaTfN9BOZiakWHH484UqGzUQDrjXWyffMchQ3h4PJU6lyg=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 23/34] tcg: [CPUTLB] Add `mo_te` field to TCGContext Date: Fri, 19 Jan 2024 15:40:13 +0100 Message-ID: <20240119144024.14289-24-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675405352100009 Content-Type: text/plain; charset="utf-8" Required by cpu_ldub_code() and friends in cputlb.c to access the MO_TE MemOp in a target-independent way. Signed-off-by: Anton Johansson --- include/tcg/tcg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 7743868dc9..4ca626aeae 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -489,6 +489,7 @@ struct TCGContext { TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ =20 #ifdef CONFIG_SOFTMMU + MemOp mo_te; int page_mask; uint8_t page_bits; uint8_t tlb_dyn_max_bits; --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675540; cv=none; d=zohomail.com; s=zohoarc; b=KDLeKuFKpIAIyzpNhVHoEYROBHrY/kBn2aaFhjxWasWMB+Ta22hkzfg4OsKIWhKze4zLeEIhN6TMaqrfD6HuP3Q+MlhAxF3LMzrn2ylNrRgb4hZSdykKANo+5RslxPJ7JX1zC77XgJwk6P6R57AzgIMfTbsj1kh/1VtZRmZdhSE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675540; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=DqmM9sshPRHIoJYSwzqyyB9gqjD6tM2/IpgeBThs0RI=; b=ftDSWjP77qurt5Gt65bDxGeRc+8UEvKL+YBV9thcm5Qg4zTBy9KZmK46/QO3zg5dxsGD25aWlF+a7t1FCtuGTezEKT5PIl3mR7lFwY03hZTe6lGS1HiigW+tmLjhG/b/69bKOgS7sw5dbU03a4SKWsVyK+IeUsiKBNyDg9sJNjQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705675540935464.00627365733806; Fri, 19 Jan 2024 06:45:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQq31-0005to-3G; Fri, 19 Jan 2024 09:40:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2y-0005sg-5y for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:40 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2v-0003v5-4I for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=DqmM9sshPRHIoJYSwzqyyB9gqjD6tM2/IpgeBThs0RI=; b=kAB7VrmPuleIWsDeB4g3poGKnl Q9ZTdOK4K+6+mRvHDyTHgPu3fPJZTAkteXdhT6sbiGbGqo+tJ3cd9FVf2U7KNiXXrM+BPohFq411U +xL3nTTdOj1f5mQSx9KRF2+6nHQwvEkaHDF2DMlcWSpEDTT8qxZxkQD9GtbX78M1U4AU=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 24/34] accel/tcg: [CPUTLB] Set mo_te in TCGContext Date: Fri, 19 Jan 2024 15:40:14 +0100 Message-ID: <20240119144024.14289-25-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675541982100011 Content-Type: text/plain; charset="utf-8" Initializes mo_te field of TCGContext to the target endian memory order MO_TE, so it can be used within cputlb.c. Signed-off-by: Anton Johansson --- accel/tcg/translate-all.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 8cb6ad3511..9c981d1750 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -47,12 +47,13 @@ #include "exec/translate-all.h" #include "exec/translator.h" #include "exec/tb-flush.h" +#include "exec/log.h" +#include "exec/memop.h" #include "qemu/bitmap.h" #include "qemu/qemu-print.h" #include "qemu/main-loop.h" #include "qemu/cacheinfo.h" #include "qemu/timer.h" -#include "exec/log.h" #include "sysemu/cpus.h" #include "sysemu/cpu-timers.h" #include "sysemu/tcg.h" @@ -342,6 +343,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->gen_tb =3D tb; tcg_ctx->addr_type =3D TARGET_LONG_BITS =3D=3D 32 ? TCG_TYPE_I32 : TCG= _TYPE_I64; #ifdef CONFIG_SOFTMMU + tcg_ctx->mo_te =3D MO_TE; tcg_ctx->page_bits =3D TARGET_PAGE_BITS; tcg_ctx->page_mask =3D TARGET_PAGE_MASK; tcg_ctx->tlb_dyn_max_bits =3D CPU_TLB_DYN_MAX_BITS; --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675366; cv=none; d=zohomail.com; s=zohoarc; b=U5UtNao1Hpw2HG8TxI13sj3F2S0iI/AZaKFAIKTCw5JbBaCJeNktrHxoNJUNRjVmKnEy/rKeUnjKD3ATe0FmALSVUevFC8E3SlFbbfZkV0CR/9lmaIbfinbmSoCOCZIBA5ji31q445nzLk5E5SBbZ2rzLlfLlX5HOWk5J93zrB8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675366; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=ZOKCnodekcL5jtYtIT72SfARPKQf/ff0v9m3k4jhn4c=; b=H3Ehj01TSAmPdaUzgw6sVanQLOBG3rtz4leq2yob9L5SCnKwgH9VX02TfuyirABTvHwiyeKu9nT0BIAQwpjGLQ3hnSKV4ypy1RvO0/3QiqpWAyaC1I0m0oTp9WesnI2zem8FpRfhT2Hxd7L8SGR1+yKwhDqE1vahXuHs0aVuPno= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705675366499492.0306824306697; Fri, 19 Jan 2024 06:42:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQq34-0005xQ-F3; Fri, 19 Jan 2024 09:40:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2z-0005tE-Ex for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:41 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2w-0003vI-BD for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=ZOKCnodekcL5jtYtIT72SfARPKQf/ff0v9m3k4jhn4c=; b=pQXf67VX6mcrwQMcXQ6+JxqdnP AVBj+8WBEyy7WI/FlkXQW6fCPkSCIDQheGb/NvwX93YlVT0A3logYQi7hjs9OmFykKtOjwS3eYx8+ 2j7yqcPZNjVlEsNKaArGQwW0Fy15frzwPpVUugwtpGWQ9kcLgBaZ2BcpFh6i8akXJWM8=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 25/34] accel/tcg: [CPUTLB] Use tcg_ctx->mo_te instead of MO_TE Date: Fri, 19 Jan 2024 15:40:15 +0100 Message-ID: <20240119144024.14289-26-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675367127100008 Content-Type: text/plain; charset="utf-8" Makes *_code() memory access functions target independent. Signed-off-by: Anton Johansson --- accel/tcg/cputlb.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a75a52d141..bfbbfd0fdb 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2988,19 +2988,22 @@ uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr a= ddr) =20 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr) { - MemOpIdx oi =3D make_memop_idx(MO_TEUW, cpu_mmu_index(env, true)); + MemOpIdx oi =3D make_memop_idx(tcg_ctx->mo_te | MO_UW, + cpu_mmu_index(env, true)); return do_ld2_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); } =20 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr) { - MemOpIdx oi =3D make_memop_idx(MO_TEUL, cpu_mmu_index(env, true)); + MemOpIdx oi =3D make_memop_idx(tcg_ctx->mo_te | MO_UL, + cpu_mmu_index(env, true)); return do_ld4_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); } =20 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr) { - MemOpIdx oi =3D make_memop_idx(MO_TEUQ, cpu_mmu_index(env, true)); + MemOpIdx oi =3D make_memop_idx(tcg_ctx->mo_te | MO_UQ, + cpu_mmu_index(env, true)); return do_ld8_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); } =20 --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675598; cv=none; d=zohomail.com; s=zohoarc; b=a8hoE68iHGnL9s9LWqVNsytnwZy+JyoaFCZV1xBCwPiJ99HhxjkltEtuW4CQUNrZQNg5um6KCf+sulQVX3S0SuvWAJzOcYMt+Q6GKKYyekFWvoRYQ7ONTPhOSKvlsptHu2x21b1X5M077HQiB0tZLGehNe8TUV4f7WU+4MrRnt0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675598; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Fri, 19 Jan 2024 09:40:41 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2w-0003vR-BD for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=ALkBXryuWDH1ZwpPT9bKXKuItIExb1fOyUeK84V/X94=; b=f+Bj+DJ1HIUm7u5Zuf5TOBQTYF nDKZQL3qa231IohstFwJPP9jRchzqj5vjZcv7WWLjyI74HupIjcSpCZdzoSNPJ3gofGVUyvn1VxYl zee0rpva+B0tB8s94g5uzHhxAaCj+27BktQhUOIkm7gRHfILInDaIkQ4oXIsB/BZB1KI=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 26/34] Wrap target macros in functions Date: Fri, 19 Jan 2024 15:40:16 +0100 Message-ID: <20240119144024.14289-27-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675600554100006 Content-Type: text/plain; charset="utf-8" Adds wrapper functions around common target specific macros required by accel/tcg. Signed-off-by: Anton Johansson --- include/hw/core/cpu.h | 9 +++++++ cpu-target.c | 62 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 57d100c203..a2d65c1d7a 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -26,6 +26,7 @@ #include "exec/vaddr.h" #include "exec/memattrs.h" #include "exec/tlb-common.h" +#include "exec/memop.h" #include "qapi/qapi-types-run-state.h" #include "qemu/bitmap.h" #include "qemu/rcu_queue.h" @@ -1164,6 +1165,14 @@ void cpu_exec_unrealizefn(CPUState *cpu); * what you are doing! */ bool target_words_bigendian(void); +bool target_supports_mttcg(void); +bool target_has_precise_smc(void); +int target_long_bits(void); +int target_phys_addr_space_bits(void); +uint8_t target_insn_start_words(void); +uint8_t target_default_memory_order(void); +uint8_t target_tlb_dyn_max_bits(void); +MemOp target_endian_memory_order(void); =20 const char *target_name(void); =20 diff --git a/cpu-target.c b/cpu-target.c index 1a8e730bed..6b67af7a51 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -39,10 +39,13 @@ #include "exec/tb-flush.h" #include "exec/translate-all.h" #include "exec/log.h" +#include "exec/cpu-defs.h" #include "hw/core/accel-cpu.h" #include "trace/trace-root.h" #include "qemu/accel.h" #include "qemu/plugin.h" +#include "tcg/tcg-mo.h" +#include "tcg/insn-start-words.h" =20 uintptr_t qemu_host_page_size; intptr_t qemu_host_page_mask; @@ -416,6 +419,65 @@ bool target_words_bigendian(void) return TARGET_BIG_ENDIAN; } =20 +bool target_supports_mttcg(void) +{ +#ifdef TARGET_SUPPORTS_MTTCG +# ifndef TCG_GUEST_DEFAULT_MO +# error "TARGET_SUPPORTS_MTTCG without TCG_GUEST_DEFAULT_MO" +# endif + return true; +#else + return false; +#endif +} + +bool target_has_precise_smc(void) +{ +#ifdef TARGET_HAS_PRECISE_SMC + return true; +#else + return false; +#endif +} + +int target_long_bits(void) +{ + return TARGET_LONG_BITS; +} + +int target_phys_addr_space_bits(void) +{ + return TARGET_PHYS_ADDR_SPACE_BITS; +} + +uint8_t target_insn_start_words(void) +{ + return TARGET_INSN_START_WORDS; +} + +uint8_t target_default_memory_order(void) +{ +#ifdef TCG_GUEST_DEFAULT_MO + return TCG_GUEST_DEFAULT_MO; +#else + return TCG_MO_ALL; +#endif +} + +MemOp target_endian_memory_order(void) +{ + return MO_TE; +} + +uint8_t target_tlb_dyn_max_bits(void) +{ +#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG) + return CPU_TLB_DYN_MAX_BITS; +#else + return 0; +#endif +} + const char *target_name(void) { return TARGET_NAME; --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675485; cv=none; d=zohomail.com; s=zohoarc; b=LdDRpRKXxJE9/QgC/EQe9mMFcn6938ChpzwmA7l9ioSQV0XwYk2u2V1BTnCb60f7NsFat8nb9pc8T9G74qHOsLSZ+00uriNJrC4bSVr1q6H49bolvucl63Fra16kxmQn6cuKN/7VPNcIqQwynC+Xq9TVv9qh4mysz9s1cDqP4+U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675485; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Fri, 19 Jan 2024 09:40:42 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQq2w-0003vW-B0 for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:40:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=r7k10i1SVH85ChTA6Z/gMmAlYkPdspyjFqih1CaFIEM=; b=mV5pRoDJz+iAaydAXG7S7xYx7k qcVGE3O8k/1/ig9cNgDD+5hKT903P1s8e2FIPk7onc1ANXrR9DU6LQpeONvdYC1teQlTOkwXFwheB 2qE+MCoXf19YGbg8v9+nBKq9yub9dUkskXpuIqaqL8HP+iORruvYYSKXeii6ZsVtMO5I=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 27/34] accel/tcg: Make translate-all.c target independent Date: Fri, 19 Jan 2024 15:40:17 +0100 Message-ID: <20240119144024.14289-28-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675485654100003 Content-Type: text/plain; charset="utf-8" Makes translate-all.c independent of softmmu target by switching TARGET_LONG_BITS -> target_long_bits() TARGET_INSN_START_WORDS -> tcg_ctx->insn_start_words, target_insn_start_words(), TCG_GUEST_DEFAULT_MO -> target_default_memory_order() MO_TE -> target_endian_memory_order() Signed-off-by: Anton Johansson --- accel/tcg/translate-all.c | 38 ++++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 9c981d1750..a3ae0c6910 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -65,7 +65,6 @@ #include "internal-common.h" #include "internal-target.h" #include "perf.h" -#include "tcg/insn-start-words.h" =20 TBContext tb_ctx; =20 @@ -106,7 +105,7 @@ static int64_t decode_sleb128(const uint8_t **pp) val |=3D (int64_t)(byte & 0x7f) << shift; shift +=3D 7; } while (byte & 0x80); - if (shift < TARGET_LONG_BITS && (byte & 0x40)) { + if (shift < target_long_bits() && (byte & 0x40)) { val |=3D -(int64_t)1 << shift; } =20 @@ -117,7 +116,7 @@ static int64_t decode_sleb128(const uint8_t **pp) /* Encode the data collected about the instructions while compiling TB. Place the data at BLOCK, and return the number of bytes consumed. =20 - The logical table consists of TARGET_INSN_START_WORDS target_ulong's, + The logical table consists of tcg_ctx->insn_start_words target_ulong's, which come from the target's insn_start data, followed by a uintptr_t which comes from the host pc of the end of the code implementing the in= sn. =20 @@ -128,6 +127,7 @@ static int64_t decode_sleb128(const uint8_t **pp) =20 static int encode_search(TranslationBlock *tb, uint8_t *block) { + const uint8_t insn_start_words =3D tcg_ctx->insn_start_words; uint8_t *highwater =3D tcg_ctx->code_gen_highwater; uint64_t *insn_data =3D tcg_ctx->gen_insn_data; uint16_t *insn_end_off =3D tcg_ctx->gen_insn_end_off; @@ -137,13 +137,13 @@ static int encode_search(TranslationBlock *tb, uint8_= t *block) for (i =3D 0, n =3D tb->icount; i < n; ++i) { uint64_t prev, curr; =20 - for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { + for (j =3D 0; j < insn_start_words; ++j) { if (i =3D=3D 0) { prev =3D (!(tb_cflags(tb) & CF_PCREL) && j =3D=3D 0 ? tb->= pc : 0); } else { - prev =3D insn_data[(i - 1) * TARGET_INSN_START_WORDS + j]; + prev =3D insn_data[(i - 1) * insn_start_words + j]; } - curr =3D insn_data[i * TARGET_INSN_START_WORDS + j]; + curr =3D insn_data[i * insn_start_words + j]; p =3D encode_sleb128(p, curr - prev); } prev =3D (i =3D=3D 0 ? 0 : insn_end_off[i - 1]); @@ -165,6 +165,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc, uint64_t *data) { + const uint8_t insn_start_words =3D tcg_ctx->insn_start_words; uintptr_t iter_pc =3D (uintptr_t)tb->tc.ptr; const uint8_t *p =3D tb->tc.ptr + tb->tc.size; int i, j, num_insns =3D tb->icount; @@ -175,7 +176,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb= , uintptr_t host_pc, return -1; } =20 - memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS); + memset(data, 0, sizeof(uint64_t) * insn_start_words); if (!(tb_cflags(tb) & CF_PCREL)) { data[0] =3D tb->pc; } @@ -185,7 +186,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb= , uintptr_t host_pc, * at which the end of the insn exceeds host_pc. */ for (i =3D 0; i < num_insns; ++i) { - for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { + for (j =3D 0; j < insn_start_words; ++j) { data[j] +=3D decode_sleb128(&p); } iter_pc +=3D decode_sleb128(&p); @@ -203,7 +204,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb= , uintptr_t host_pc, void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t host_pc) { - uint64_t data[TARGET_INSN_START_WORDS]; + uint64_t data[tcg_ctx->insn_start_words]; int insns_left =3D cpu_unwind_data_from_tb(tb, host_pc, data); =20 if (insns_left < 0) { @@ -341,19 +342,15 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } =20 tcg_ctx->gen_tb =3D tb; - tcg_ctx->addr_type =3D TARGET_LONG_BITS =3D=3D 32 ? TCG_TYPE_I32 : TCG= _TYPE_I64; + tcg_ctx->addr_type =3D target_long_bits() =3D=3D 32 ? TCG_TYPE_I32 : T= CG_TYPE_I64; #ifdef CONFIG_SOFTMMU - tcg_ctx->mo_te =3D MO_TE; + tcg_ctx->mo_te =3D target_endian_memory_order(); tcg_ctx->page_bits =3D TARGET_PAGE_BITS; tcg_ctx->page_mask =3D TARGET_PAGE_MASK; - tcg_ctx->tlb_dyn_max_bits =3D CPU_TLB_DYN_MAX_BITS; -#endif - tcg_ctx->insn_start_words =3D TARGET_INSN_START_WORDS; -#ifdef TCG_GUEST_DEFAULT_MO - tcg_ctx->guest_mo =3D TCG_GUEST_DEFAULT_MO; -#else - tcg_ctx->guest_mo =3D TCG_MO_ALL; + tcg_ctx->tlb_dyn_max_bits =3D target_tlb_dyn_max_bits(); #endif + tcg_ctx->insn_start_words =3D target_insn_start_words(); + tcg_ctx->guest_mo =3D target_default_memory_order(); =20 restart_translate: trace_translate_block(tb, pc, tb->tc.ptr); @@ -441,6 +438,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, qemu_log_in_addr_range(pc)) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { + const uint8_t insn_start_words =3D tcg_ctx->insn_start_words; int code_size, data_size; const tcg_target_ulong *rx_data_gen_ptr; size_t chunk_start; @@ -460,7 +458,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, fprintf(logfile, "OUT: [size=3D%d]\n", gen_code_size); fprintf(logfile, " -- guest addr 0x%016" PRIx64 " + tb prologue\n", - tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]= ); + tcg_ctx->gen_insn_data[insn * insn_start_words]); chunk_start =3D tcg_ctx->gen_insn_end_off[insn]; disas(logfile, tb->tc.ptr, chunk_start); =20 @@ -473,7 +471,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, size_t chunk_end =3D tcg_ctx->gen_insn_end_off[insn]; if (chunk_end > chunk_start) { fprintf(logfile, " -- guest addr 0x%016" PRIx64 "\n", - tcg_ctx->gen_insn_data[insn * TARGET_INSN_STAR= T_WORDS]); + tcg_ctx->gen_insn_data[insn * insn_start_words= ]); disas(logfile, tb->tc.ptr + chunk_start, chunk_end - chunk_start); chunk_start =3D chunk_end; --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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charset="utf-8" Switches computation of offsets into CPUState to use that the offset between CPUState and CPUArchState is guaranteed to be sizeof(CPUState). Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/plugin-gen.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index d31c9993ea..ce7635958f 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -43,10 +43,9 @@ * CPU's index into a TCG temp, since the first callback did it already. */ #include "qemu/osdep.h" -#include "cpu.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg-op-common.h" #include "exec/exec-all.h" #include "exec/plugin-gen.h" #include "exec/translator.h" @@ -104,8 +103,8 @@ static void gen_empty_udata_cb(void) TCGv_ptr udata =3D tcg_temp_ebb_new_ptr(); =20 tcg_gen_movi_ptr(udata, 0); - tcg_gen_ld_i32(cpu_index, tcg_env, - -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)= ); + tcg_gen_ld_i32(cpu_index, tcg_env, offsetof(CPUState, cpu_index) - + sizeof(CPUState)); gen_helper_plugin_vcpu_udata_cb(cpu_index, udata); =20 tcg_temp_free_ptr(udata); @@ -138,8 +137,8 @@ static void gen_empty_mem_cb(TCGv_i64 addr, uint32_t in= fo) =20 tcg_gen_movi_i32(meminfo, info); tcg_gen_movi_ptr(udata, 0); - tcg_gen_ld_i32(cpu_index, tcg_env, - -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)= ); + tcg_gen_ld_i32(cpu_index, tcg_env, offsetof(CPUState, cpu_index) - + sizeof(CPUState)); =20 gen_helper_plugin_vcpu_mem_cb(cpu_index, meminfo, addr, udata); =20 @@ -158,7 +157,7 @@ static void gen_empty_mem_helper(void) =20 tcg_gen_movi_ptr(ptr, 0); tcg_gen_st_ptr(ptr, tcg_env, offsetof(CPUState, plugin_mem_cbs) - - offsetof(ArchCPU, env)); + sizeof(CPUState)); tcg_temp_free_ptr(ptr); } =20 @@ -582,7 +581,7 @@ void plugin_gen_disable_mem_helpers(void) return; } tcg_gen_st_ptr(tcg_constant_ptr(NULL), tcg_env, - offsetof(CPUState, plugin_mem_cbs) - offsetof(ArchCPU, = env)); + offsetof(CPUState, plugin_mem_cbs) - sizeof(CPUState)); } =20 static void plugin_gen_tb_udata(const struct qemu_plugin_tb *ptb, --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=Gl36QuzYyvoBWlG81WaphhIIJAHdZ9uea0zXwZMnf8A=; b=wBQZ2AHdAZGtI8qvZrwPNJs1en v7/qruDFh82HC4U/SrDfVLd53y9wKhW7JM9kBi69pzamoYfKiV5xcopcboA8VsSeW5h1Tow7d+wsb wxt/NDKoIaw1YLT2WdhtDmhKUITLZnaIi3A8BLw/Ln/4ftjbc0vMZWgxxRMgovhZksTM=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 29/34] accel/tcg: Make tb-maint.c target indpendent Date: Fri, 19 Jan 2024 15:40:19 +0100 Message-ID: <20240119144024.14289-30-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675338997100003 Content-Type: text/plain; charset="utf-8" Uses target_has_precise_smc() and target_phys_addr_space_bits() to turn ifdefs into runtime branches. Signed-off-by: Anton Johansson --- accel/tcg/tb-maint.c | 47 +++++++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 22 deletions(-) diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index b194f8f065..fdc3a30d0d 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -148,14 +148,6 @@ static PageForEachNext foreach_tb_next(PageForEachNext= tb, } =20 #else -/* - * In system mode we want L1_MAP to be based on ram offsets. - */ -#if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS -# define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS -#else -# define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS -#endif =20 /* Size of the L2 (and L3, etc) page tables. */ #define V_L2_BITS 10 @@ -186,17 +178,28 @@ struct PageDesc { =20 void page_table_config_init(void) { + int target_phys_addr_bits =3D target_phys_addr_space_bits(); + uint32_t l1_map_addr_space_bits; uint32_t v_l1_bits; =20 + /* + * In system mode we want L1_MAP to be based on ram offsets. + */ + if (HOST_LONG_BITS < target_phys_addr_bits) { + l1_map_addr_space_bits =3D HOST_LONG_BITS; + } else { + l1_map_addr_space_bits =3D target_phys_addr_bits; + } + assert(TARGET_PAGE_BITS); /* The bits remaining after N lower levels of page tables. */ - v_l1_bits =3D (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % V_L2_BITS; + v_l1_bits =3D (l1_map_addr_space_bits - TARGET_PAGE_BITS) % V_L2_BITS; if (v_l1_bits < V_L1_MIN_BITS) { v_l1_bits +=3D V_L2_BITS; } =20 v_l1_size =3D 1 << v_l1_bits; - v_l1_shift =3D L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - v_l1_bits; + v_l1_shift =3D l1_map_addr_space_bits - TARGET_PAGE_BITS - v_l1_bits; v_l2_levels =3D v_l1_shift / V_L2_BITS - 1; =20 assert(v_l1_bits <=3D V_L1_MAX_BITS); @@ -1045,14 +1048,15 @@ bool tb_invalidate_phys_page_unwind(tb_page_addr_t = addr, uintptr_t pc) TranslationBlock *tb; PageForEachNext n; tb_page_addr_t last; + const bool has_precise_smc =3D target_has_precise_smc(); =20 /* * Without precise smc semantics, or when outside of a TB, * we can skip to invalidate. */ -#ifndef TARGET_HAS_PRECISE_SMC - pc =3D 0; -#endif + if (!has_precise_smc) { + pc =3D 0; + } if (!pc) { tb_invalidate_phys_page(addr); return false; @@ -1102,10 +1106,13 @@ tb_invalidate_phys_page_range__locked(struct page_c= ollection *pages, { TranslationBlock *tb; PageForEachNext n; -#ifdef TARGET_HAS_PRECISE_SMC + const bool has_precise_smc =3D target_has_precise_smc(); bool current_tb_modified =3D false; - TranslationBlock *current_tb =3D retaddr ? tcg_tb_lookup(retaddr) : NU= LL; -#endif /* TARGET_HAS_PRECISE_SMC */ + TranslationBlock *current_tb =3D NULL; + + if (has_precise_smc && retaddr) { + current_tb =3D tcg_tb_lookup(retaddr); + } =20 /* Range may not cross a page. */ tcg_debug_assert(((start ^ last) & TARGET_PAGE_MASK) =3D=3D 0); @@ -1127,8 +1134,7 @@ tb_invalidate_phys_page_range__locked(struct page_col= lection *pages, tb_last =3D tb_start + (tb_last & ~TARGET_PAGE_MASK); } if (!(tb_last < start || tb_start > last)) { -#ifdef TARGET_HAS_PRECISE_SMC - if (current_tb =3D=3D tb && + if (has_precise_smc && current_tb =3D=3D tb && (tb_cflags(current_tb) & CF_COUNT_MASK) !=3D 1) { /* * If we are modifying the current TB, we must stop @@ -1140,7 +1146,6 @@ tb_invalidate_phys_page_range__locked(struct page_col= lection *pages, current_tb_modified =3D true; cpu_restore_state_from_tb(current_cpu, current_tb, retaddr= ); } -#endif /* TARGET_HAS_PRECISE_SMC */ tb_phys_invalidate__locked(tb); } } @@ -1150,15 +1155,13 @@ tb_invalidate_phys_page_range__locked(struct page_c= ollection *pages, tlb_unprotect_code(start); } =20 -#ifdef TARGET_HAS_PRECISE_SMC - if (current_tb_modified) { + if (has_precise_smc && current_tb_modified) { page_collection_unlock(pages); /* Force execution of one insn next time. */ current_cpu->cflags_next_tb =3D 1 | CF_NOIRQ | curr_cflags(current= _cpu); mmap_unlock(); cpu_loop_exit_noexc(current_cpu); } -#endif } =20 /* --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675777; cv=none; d=zohomail.com; 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charset="utf-8" Uses target_supports_mttcg() and target_long_bits() to turn ifdefs into runtime branches. Signed-off-by: Anton Johansson Acked-by: Richard Henderson --- accel/tcg/tcg-all.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index a40e0aee37..b8e920e3a8 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -28,7 +28,6 @@ #include "exec/replay-core.h" #include "sysemu/cpu-timers.h" #include "tcg/tcg.h" -#include "tcg/oversized-guest.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/accel.h" @@ -67,20 +66,13 @@ DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE, * there is one remaining limitation to check: * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host) */ - static bool default_mttcg_enabled(void) { - if (icount_enabled() || TCG_OVERSIZED_GUEST) { + const bool oversized_guest =3D target_long_bits() > TCG_TARGET_REG_BIT= S; + if (icount_enabled() || oversized_guest) { return false; } -#ifdef TARGET_SUPPORTS_MTTCG -# ifndef TCG_GUEST_DEFAULT_MO -# error "TARGET_SUPPORTS_MTTCG without TCG_GUEST_DEFAULT_MO" -# endif - return true; -#else - return false; -#endif + return target_supports_mttcg(); } =20 static void tcg_accel_instance_init(Object *obj) @@ -137,17 +129,18 @@ static char *tcg_get_thread(Object *obj, Error **errp) static void tcg_set_thread(Object *obj, const char *value, Error **errp) { TCGState *s =3D TCG_STATE(obj); + const bool oversized_guest =3D target_long_bits() > TCG_TARGET_REG_BIT= S; =20 if (strcmp(value, "multi") =3D=3D 0) { - if (TCG_OVERSIZED_GUEST) { + if (oversized_guest) { error_setg(errp, "No MTTCG when guest word size > hosts"); } else if (icount_enabled()) { error_setg(errp, "No MTTCG when icount is enabled"); } else { -#ifndef TARGET_SUPPORTS_MTTCG - warn_report("Guest not yet converted to MTTCG - " - "you may get unexpected results"); -#endif + if (target_supports_mttcg()) { + warn_report("Guest not yet converted to MTTCG - " + "you may get unexpected results"); + } s->mttcg_enabled =3D true; } } else if (strcmp(value, "single") =3D=3D 0) { --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675835230100003 Content-Type: text/plain; charset="utf-8" Only depends on cpu.h. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/tcg-runtime-gvec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index afca89baa1..52f983dd4c 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -19,7 +19,7 @@ =20 #include "qemu/osdep.h" #include "qemu/host-utils.h" -#include "cpu.h" +#include "qemu/bitops.h" #include "exec/helper-proto-common.h" #include "tcg/tcg-gvec-desc.h" =20 --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675751; cv=none; d=zohomail.com; s=zohoarc; b=lDf8Yk7E0zrlkWxhQvHG7qcDilEfuqAvBx3MxpVd6cRYaEVGAvjnjqnG8YRe8G0NfcIwAazkHdK4x2FmEz6alfh4ABsvlJAPW0vQ7qxxbwRS42EouP8eNIgV30pWRI0SxfQqbiqvNtz9iGkIsmvz9edbTU4TgbZdSl8UMzs+Ll8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675751; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=+CCEwq6vBajqXXbTYUNIyxsBrAeiT073vXE6g4CnjnE=; b=aixAXwUqaV5Bh2X10fICVSWkylvyGdkUZAX1DesHeeuPu4Y2w73w3c8yWQaB2Dl+gy3KJd2mZSgajE4lHf3xjIiwo+Zt7YhD69341V622HZLtdksttxEXIquAyjI0KHNTbzwOxGgHGNbrSsNmGeC32hAMqpDGi76WLlOBC6ypJo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705675751586955.7209510604255; Fri, 19 Jan 2024 06:49:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQqB4-0002M4-W1; Fri, 19 Jan 2024 09:49:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQqB3-0002II-1V for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:49:01 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQqB1-00083t-Mn for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:49:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=+CCEwq6vBajqXXbTYUNIyxsBrAeiT073vXE6g4CnjnE=; b=Z4ArHV3O8pLsxu9+oDQWM0ajqS EiETihBzBO/27+6w+vbF93FJnIkdTP5F892B7pSaB9iDnQpi4dsSiG30b9dpKd1Kp57XXWZVGJnEA ZWPq1SOtuTSpBNmT7hv8BQ6xPob46VLESj6YQvNlzwmmdAXvH5RkfOiDVG2Q1qZ6vPsE=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 32/34] accel/tcg: Make tcg-runtime.c target independent Date: Fri, 19 Jan 2024 15:40:22 +0100 Message-ID: <20240119144024.14289-33-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675752975100003 Content-Type: text/plain; charset="utf-8" Only depends on cpu.h. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/tcg-runtime.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 9fa539ad3d..fd78a10fe2 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -23,7 +23,7 @@ */ #include "qemu/osdep.h" #include "qemu/host-utils.h" -#include "cpu.h" +#include "qemu/atomic.h" #include "exec/helper-proto-common.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675764; cv=none; d=zohomail.com; s=zohoarc; b=Cli0Arp9qjPwmSFQ2zdhcNnrYvt6HqJ5A5JYA3fQuouJQYNcXEDOl1x+F9FAwvGBlDNZGBQaoi8C1UIqwIEuyZ6aWlGl5MWPijfRJy/8fAk52Q+y01ILUdJbu2CRJtHwgN6ZjBqNWA/TQxALIUi1Od+X0n04zIqxd4FiJuxlht4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675764; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=X7sNZ16xM/rGRC0Fl2PyYpAxqTIz8x8cc5VBtkT4zbA=; b=HnDvpmTyZ/p/6piWsYjLyoyml6OBM2vxsCOBK+TcunrFJkT/hqwcfg7DlRPAyzXw/JOLF1fxqGIRmXAv3ETN78bVSCjSx6E6UNyEeL33AZd6vmCdLrkB/5kWzsBMJyRSQUjQgIdIrX+lr5ZlM7GY7OLiuCPFpfgIEz5RLok8qnM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705675764869285.04149754532364; Fri, 19 Jan 2024 06:49:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQqB0-0002Hp-TK; Fri, 19 Jan 2024 09:48:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQqAx-0002HQ-N5 for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:48:55 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQqAw-00083G-Ba for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:48:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=X7sNZ16xM/rGRC0Fl2PyYpAxqTIz8x8cc5VBtkT4zbA=; b=kE/YliNO7Clq+UOCIpcOyc7hFd XVoFqk6dFMbUabehokuVYbyGvzU3XhH4pa+Fu/xH51JoY1PbWn2nm7fa2rlwDbwZHt07MpHfXS85F 1bxcFwFoyZjmoqfDgGgDDIxWC5khH4vAutG6zuLyR42k0iwoJE+qMVenAoNpJogjE24g=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 33/34] accel/tcg: Make translator.c (partially) target independent Date: Fri, 19 Jan 2024 15:40:23 +0100 Message-ID: <20240119144024.14289-34-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675767097100003 Content-Type: text/plain; charset="utf-8" Make CPUState offset calculations target independent by using that CPUState and CPUArchState are statically guaranteed to lie next to each other in memory. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/translator.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 65219b52eb..43303577d7 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -19,8 +19,8 @@ static void gen_io_start(void) { tcg_gen_st_i32(tcg_constant_i32(1), tcg_env, - offsetof(ArchCPU, parent_obj.neg.can_do_io) - - offsetof(ArchCPU, env)); + offsetof(CPUState, neg.can_do_io) - + sizeof(CPUState)); } =20 bool translator_io_start(DisasContextBase *db) @@ -53,8 +53,8 @@ static TCGOp *gen_tb_start(uint32_t cflags) TCGOp *icount_start_insn =3D NULL; =20 tcg_gen_ld_i32(count, tcg_env, - offsetof(ArchCPU, parent_obj.neg.icount_decr.u32) - - offsetof(ArchCPU, env)); + offsetof(CPUState, neg.icount_decr.u32) - + sizeof(CPUState)); =20 if (cflags & CF_USE_ICOUNT) { /* @@ -82,8 +82,8 @@ static TCGOp *gen_tb_start(uint32_t cflags) =20 if (cflags & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, tcg_env, - offsetof(ArchCPU, parent_obj.neg.icount_decr.u16.= low) - - offsetof(ArchCPU, env)); + offsetof(CPUState, neg.icount_decr.u16.low) - + sizeof(CPUState)); /* * cpu->can_do_io is cleared automatically here at the beginning of * each translation block. The cost is minimal and only paid for @@ -92,8 +92,8 @@ static TCGOp *gen_tb_start(uint32_t cflags) * go with gen_io_start(). */ tcg_gen_st_i32(tcg_constant_i32(0), tcg_env, - offsetof(ArchCPU, parent_obj.neg.can_do_io) - - offsetof(ArchCPU, env)); + offsetof(CPUState, neg.can_do_io) - + sizeof(CPUState)); } =20 return icount_start_insn; --=20 2.43.0 From nobody Tue Nov 26 16:23:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705675761; cv=none; d=zohomail.com; s=zohoarc; b=DbP1603icK31znCslFalE0Z5IKHdM/KvLh9fGjof1ORDDb1ckB0Sjm/L/wldjYaWeK3qpoujnG+j5o6wI7tS4LkPm7htJbFxxPOglYvAsYLkF+JVOOIkuR3tADndJ0BJNuhsCwzAPIRexE/WgjQKksbwY9Ti3lRCZEiSSOP3f7U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705675761; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=QKCN+pjZ4XQPs3wyUDnH+MXvsD7/sLfzvDEV9EBbK2s=; b=G8F8euFapS/aBJrBseMcxmJY+E/npD143sS/JFSDkLbNmRSm9F9BW/krQeDWL7Znogdw8cQqGK8jnvBv5+hP//Mi0Bnd+530q+yvRyFR+Y4JQqgl8N3A5hpyxjLR0VqB/1/WJWVUNHH/OF3k9dgGA0rzUBRgJi0ccXOpg5uB/Ho= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17056757612171004.3068674294935; Fri, 19 Jan 2024 06:49:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQqAx-0002HD-At; Fri, 19 Jan 2024 09:48:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQqAu-0002Gl-Cx for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:48:54 -0500 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQqAq-0007me-3d for qemu-devel@nongnu.org; Fri, 19 Jan 2024 09:48:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=QKCN+pjZ4XQPs3wyUDnH+MXvsD7/sLfzvDEV9EBbK2s=; b=je/YjabjUjA20YRkWW7y4+ZTxX i2zAQ9NXwE7wfXIvtzq19eEGqJokubfsFC96soiMEvie6Vb2m6aF3+6YGy8YvRQ0oZnHByjEEhmMb qpshBgPOqednmHLBWsQ3IvBnvw5PMpt7eJ4i1koyikhLT8pMgx7h27LCfkHMRh5V5Iyo=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, philmd@linaro.org Subject: [RFC PATCH 34/34] accel/tcg: Compile (a few files) once for system-mode Date: Fri, 19 Jan 2024 15:40:24 +0100 Message-ID: <20240119144024.14289-35-anjo@rev.ng> In-Reply-To: <20240119144024.14289-1-anjo@rev.ng> References: <20240119144024.14289-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1705675763034100003 Content-Type: text/plain; charset="utf-8" Build a common static library for a few softmmu files. Signed-off-by: Anton Johansson --- accel/tcg/meson.build | 57 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 45 insertions(+), 12 deletions(-) diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 8783edd06e..420050bdbf 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -1,28 +1,61 @@ -tcg_ss =3D ss.source_set() +tcg_specific_ss =3D ss.source_set() +tcg_user_ss =3D ss.source_set() common_ss.add(when: 'CONFIG_TCG', if_true: files( 'cpu-exec-common.c', )) -tcg_ss.add(files( - 'tcg-all.c', +common_ss.add(when: libdw, if_true: files('debuginfo.c')) + +tcg_specific_ss.add(files( 'cpu-exec.c', + 'translator.c', +)) + +tcg_user_ss.add(files( + 'user-exec.c', + 'translate-all.c', 'tb-maint.c', 'tcg-runtime-gvec.c', 'tcg-runtime.c', - 'translate-all.c', - 'translator.c', + 'tcg-all.c', )) -tcg_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c')) -tcg_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files('user-exec-stub.c')) if get_option('plugins') - tcg_ss.add(files('plugin-gen.c')) + tcg_user_ss.add(files('plugin-gen.c')) endif -tcg_ss.add(when: libdw, if_true: files('debuginfo.c')) -tcg_ss.add(when: 'CONFIG_LINUX', if_true: files('perf.c')) -specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) +tcg_specific_ss.add_all(when: 'CONFIG_USER_ONLY', if_true: tcg_user_ss) +tcg_specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files( + 'user-exec-stub.c' +)) +tcg_specific_ss.add(when: 'CONFIG_LINUX', if_true: files('perf.c')) +specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) =20 -specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( +have_tcg =3D get_option('tcg').allowed() +tcg_softmmu_ss =3D ss.source_set() +tcg_softmmu_ss.add(files( 'cputlb.c', + 'translate-all.c', + 'tb-maint.c', + 'tcg-runtime-gvec.c', + 'tcg-runtime.c', + 'tcg-all.c', )) +if get_option('plugins') + tcg_softmmu_ss.add(files('plugin-gen.c')) +endif +tcg_softmmu_ss =3D tcg_softmmu_ss.apply(config_targetos, strict: false) + +libacceltcg_softmmu =3D static_library('acceltcg_softmmu', + tcg_softmmu_ss.sources() + genh, + name_suffix: 'fa', + c_args: '-DCONFIG_SOFTMMU', + build_by_default: have_system and + have_tcg) + +if not get_option('tcg').allowed() + subdir_done() +endif +tcg_softmmu =3D declare_dependency(link_with: libacceltcg_softmmu, + dependencies: tcg_softmmu_ss.dependencies= ()) +system_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: tcg_softmmu) =20 system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'icount-common.c', --=20 2.43.0