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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id l34-20020a05600c1d2200b0040e89ade84bsm8335292wms.4.2024.01.19.03.35.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:35:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705664131; x=1706268931; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JMrQlur1rdNDznxBbxffE0eHdXnWue3lFnhNe5G+YeM=; b=oRZli/WQCod48AruckfvcALEqBX1COn+q0g4lucifHW0/bmTH0gqDrtsq8S3qvfYeA oLvqpJN/xZP1D7QTWwpXObtVytj6p4J7SCkx6ZJnj96GZTJfoy7L/eitDmtwxR58tANa 8WMUh4xs/chUleOH+F5scW5V5hPLDefu+1d9lF8Psnpb6XkiQJX7rKYEH9dRkO6dMh2W +eGkymz6nVTA0X9CvjHNkVwoIdZPf71AEJHkPQk55ZfUBTOLJcRgv8dFntqOVRO++GPC oFP74sNKJp2PzuNvP4dxNke9RMTfUnDZZFejfMYAL7zYg9sOe3EzPOuFUZ7IXflo5N5H bSFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705664131; x=1706268931; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JMrQlur1rdNDznxBbxffE0eHdXnWue3lFnhNe5G+YeM=; b=YxzIwYJbdh3qQKwtKMiPoGOWwrQJItri2RwJJIGBD5hCRbersZLnEY3Tmyqz10+98D HEtalV565aTClQpm1AL3t/HW9/hnc1mRx1JqdIfA0H/wna1qBDBdJGRTBuRyEGq4PNQ4 1Jba8wySybekaAI6syWkSKycVQDuMzlKtOeVUNsh2Cvo5sX25GzXvoVvGPOXA1hHmpIK sJhVxSa9Pc1ArMBsrRQXhUnwpYSVYOhx0DY8erFfZSiC6dZ4xRyVv69pd8hdSXeP+qTb i/MOSMQfKthy8CzUE30QMC5Oz42VNN1cJP2ueXHXQPH7hDyuLzXyVruu5KLdg/qJv8TZ M4NA== X-Gm-Message-State: AOJu0YynCOh9fHXgoZtmv4fLz9VOsvCmAEiPdp58rTKdHmUFuEQ9G1wu U1e6QxhnGaDoMuGn+KrjjK7mccecBVd31g/oxcSB3rKacxMtjgToFMqVbIrQDyaTi3ENar2OQWA 4obsEhw== X-Google-Smtp-Source: AGHT+IHXwLEr/a6UENRrYaD362ImuRSNy+JwCzoG2DcOb6zwj1LR21EyCD7qzjXtJQaIOZf9zvtMLQ== X-Received: by 2002:a7b:cc82:0:b0:40e:657c:5c88 with SMTP id p2-20020a7bcc82000000b0040e657c5c88mr1414364wma.28.1705664131605; Fri, 19 Jan 2024 03:35:31 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Max Filippov , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 05/36] target/xtensa: use generic instruction breakpoint infrastructure Date: Fri, 19 Jan 2024 12:34:34 +0100 Message-ID: <20240119113507.31951-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1705664665010100003 From: Max Filippov Don't embed ibreak exception generation into TB and don't invalidate TB on ibreak address change. Add CPUBreakpoint pointers to xtensa CPUArchState, use cpu_breakpoint_insert/cpu_breakpoint_remove_by_ref to manage ibreak breakpoints and provide TCGCPUOps::debug_check_breakpoint callback that recognizes valid instruction breakpoints. Signed-off-by: Max Filippov Reviewed-by: Richard Henderson Message-ID: <20231130171920.3798954-2-jcmvbkbc@gmail.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/xtensa/cpu.h | 4 ++++ target/xtensa/cpu.c | 1 + target/xtensa/dbg_helper.c | 46 +++++++++++++++++++++++++------------- target/xtensa/helper.c | 12 ++++++++++ target/xtensa/translate.c | 17 -------------- 5 files changed, 47 insertions(+), 33 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index d9c49a35fa..4b033ee924 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -229,6 +229,7 @@ enum { #define MAX_NCCOMPARE 3 #define MAX_TLB_WAY_SIZE 8 #define MAX_NDBREAK 2 +#define MAX_NIBREAK 2 #define MAX_NMEMORY 4 #define MAX_MPU_FOREGROUND_SEGMENTS 32 =20 @@ -547,6 +548,8 @@ struct CPUArchState { =20 /* Watchpoints for DBREAK registers */ struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; + /* Breakpoints for IBREAK registers */ + struct CPUBreakpoint *cpu_breakpoint[MAX_NIBREAK]; }; =20 /** @@ -590,6 +593,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t reta= ddr); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +bool xtensa_debug_check_breakpoint(CPUState *cs); #endif void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); void xtensa_count_regs(const XtensaConfig *config, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 93e782a6e0..99c0ca130f 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -233,6 +233,7 @@ static const struct TCGCPUOps xtensa_tcg_ops =3D { .do_interrupt =3D xtensa_cpu_do_interrupt, .do_transaction_failed =3D xtensa_cpu_do_transaction_failed, .do_unaligned_access =3D xtensa_cpu_do_unaligned_access, + .debug_check_breakpoint =3D xtensa_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ }; =20 diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index 3e0c9e8e8b..497dafca71 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -33,27 +33,21 @@ #include "exec/exec-all.h" #include "exec/address-spaces.h" =20 -static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) -{ - uint32_t paddr; - uint32_t page_size; - unsigned access; - int ret =3D xtensa_get_physical_addr(env, false, vaddr, 2, 0, - &paddr, &page_size, &access); - if (ret =3D=3D 0) { - tb_invalidate_phys_addr(&address_space_memory, paddr, - MEMTXATTRS_UNSPECIFIED); - } -} - void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) { + CPUState *cs =3D env_cpu(env); uint32_t change =3D v ^ env->sregs[IBREAKENABLE]; unsigned i; =20 for (i =3D 0; i < env->config->nibreak; ++i) { if (change & (1 << i)) { - tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); + if (v & (1 << i)) { + cpu_breakpoint_insert(cs, env->sregs[IBREAKA + i], + BP_CPU, &env->cpu_breakpoint[i]); + } else { + cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[i]); + env->cpu_breakpoint[i] =3D NULL; + } } } env->sregs[IBREAKENABLE] =3D v & ((1 << env->config->nibreak) - 1); @@ -62,12 +56,32 @@ void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint= 32_t v) void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) { if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != =3D v) { - tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); - tb_invalidate_virtual_addr(env, v); + CPUState *cs =3D env_cpu(env); + + cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[i]); + cpu_breakpoint_insert(cs, v, BP_CPU, &env->cpu_breakpoint[i]); } env->sregs[IBREAKA + i] =3D v; } =20 +bool xtensa_debug_check_breakpoint(CPUState *cs) +{ + XtensaCPU *cpu =3D XTENSA_CPU(cs); + CPUXtensaState *env =3D &cpu->env; + unsigned int i; + + if (xtensa_get_cintlevel(env) >=3D env->config->debug_level) { + return false; + } + for (i =3D 0; i < env->config->nibreak; ++i) { + if (env->sregs[IBREAKENABLE] & (1 << i) && + env->sregs[IBREAKA + i] =3D=3D env->pc) { + return true; + } + } + return false; +} + static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, uint32_t dbreakc) { diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f6632df646..a9f8907083 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -231,6 +231,18 @@ void xtensa_breakpoint_handler(CPUState *cs) } cpu_loop_exit_noexc(cs); } + } else { + if (cpu_breakpoint_test(cs, env->pc, BP_GDB) + || !cpu_breakpoint_test(cs, env->pc, BP_CPU)) { + return; + } + if (env->sregs[ICOUNT] =3D=3D 0xffffffff && + xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { + debug_exception_env(env, DEBUGCAUSE_IC); + } else { + debug_exception_env(env, DEBUGCAUSE_IB); + } + cpu_loop_exit_noexc(cs); } } =20 diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index de89940599..87947236ca 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1123,19 +1123,6 @@ static inline unsigned xtensa_insn_len(CPUXtensaStat= e *env, DisasContext *dc) return xtensa_op0_insn_len(dc, b0); } =20 -static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc) -{ - unsigned i; - - for (i =3D 0; i < dc->config->nibreak; ++i) { - if ((env->sregs[IBREAKENABLE] & (1 << i)) && - env->sregs[IBREAKA + i] =3D=3D dc->pc) { - gen_debug_exception(dc, DEBUGCAUSE_IB); - break; - } - } -} - static void xtensa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) { @@ -1205,10 +1192,6 @@ static void xtensa_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cpu) gen_set_label(label); } =20 - if (dc->debug) { - gen_ibreak_check(env, dc); - } - disas_xtensa_insn(env, dc); =20 if (dc->icount) { --=20 2.41.0