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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id n13-20020a5d51cd000000b0033673ddd81csm6238840wrv.112.2024.01.19.03.37.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:37:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705664248; x=1706269048; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ODpPk4V4L74xrCSwXIUijjl6fJH0n8xXoj2+PFNQbhs=; b=eIXZ1Tks3W8nIRyoK4sHzQw0RHEZji/9FUeQC8Qsy/N4NAp9hCQOp/w05MccHJ+bZo g8TnlT/q8GFE+LwuEWlQAPYX+svvvoa1iohVpBTIgiqMOfTbY93S3NnYLPJX2Av8/pUF W1GRN/b5qkuGXmlzBE+zo927o7ij/RfxmjX8dnXfia0NDa0NuCcJtcb6qMOTWPfMUx1y cJ+92ucdBkVXxKoSZUNSEeSvoWBVSJrYRn0oB+1KrpH44Pl2R54Ecdg1XqQGVfiNGS5R Xzg5wIvP6KSX9cwZ2dFz5JoAWJoJ9h4pfXQUsq/1dirfqxaYGdAUfDH6ThhvUKV2IcW2 JEpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705664248; x=1706269048; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ODpPk4V4L74xrCSwXIUijjl6fJH0n8xXoj2+PFNQbhs=; b=cTPcVpKfyhpEn7EFFEJiD/+GJAO9Otv0BZcQjWTZ58UksJby4m9eanSGXDWVvq1msY vYztOGMnCQnRW9tSliRtelWlTPoLhcjj/aOCMp2Ttkg8Bc13uPcuvrgBFbe1lH8/5BBq CN1jHFS5CRQ5wA3AX6EKO8f2iGQP/6XQl309tFihZpV8/Vy9dqghL2+LYKRxsm+0NEk4 xv7zaSqEkRdkAxzOhQgnKtICFz+TJItr51FYuPLijM1jqJKvJ59GoTZzJ6EBByxksSz/ /WTXb2FlcKuFEfBMsccu3Xl7POOZcdEc4MF6zEczK5NXpZCfVYk0j32d0zWdoGlQPTQR HwDQ== X-Gm-Message-State: AOJu0Yyh2k9x1a2GwYwl+k1LhQkhlY28FKdzKCRtK7wAGpVOR/ypbPmP c6LBf5ncHm5lcuFxpc/zjXrQqpehIahekKRXcAzDGvuZ/xQArDrKOEHVZ+vIDHaY0/L7i/j8j0l iLDI+/g== X-Google-Smtp-Source: AGHT+IEIrX/z6IwaxDIYnTkkVa92cOwMdnkJU9aX6lQnqOf1mTPLbyTPg1auGFz61Q1hUZ14flsswQ== X-Received: by 2002:a5d:698b:0:b0:336:8b2f:2ae5 with SMTP id g11-20020a5d698b000000b003368b2f2ae5mr589450wru.24.1705664248288; Fri, 19 Jan 2024 03:37:28 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Mark Cave-Ayland , Guenter Roeck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Fam Zheng Subject: [PULL 31/36] hw/scsi/esp-pci: synchronise setting of DMA_STAT_DONE with ESP completion interrupt Date: Fri, 19 Jan 2024 12:35:00 +0100 Message-ID: <20240119113507.31951-32-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1705664636891100001 From: Mark Cave-Ayland The setting of DMA_STAT_DONE at the end of a DMA transfer can be configured= to generate an interrupt, however the Linux driver manually checks for DMA_STA= T_DONE being set and if it is, considers that a DMA transfer has completed. If DMA_STAT_DONE is set but the ESP device isn't indicating an interrupt th= en the Linux driver considers this to be a spurious interrupt. However this can occur in QEMU as there is a delay between the end of DMA transfer where DMA_STAT_DONE is set, and the ESP device raising its completion interrupt. This appears to be an incorrect assumption in the Linux driver as the ESP a= nd PCI DMA interrupt sources are separate (and may not be raised exactly together), however we can work around this by synchronising the setting of DMA_STAT_DONE at the end of a DMA transfer with the ESP completion interrup= t. In conjunction with the previous commit Linux is now able to correctly boot from an am53c974 PCI SCSI device on the hppa C3700 machine without emitting "iget: checksum invalid" and "Spurious irq, sreg=3D10" errors. Signed-off-by: Mark Cave-Ayland Reviewed-by: Guenter Roeck Tested-by: Guenter Roeck Message-ID: <20240112131529.515642-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/scsi/esp-pci.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c index 15dc3c004d..875a49199d 100644 --- a/hw/scsi/esp-pci.c +++ b/hw/scsi/esp-pci.c @@ -93,6 +93,18 @@ static void esp_irq_handler(void *opaque, int irq_num, i= nt level) =20 if (level) { pci->dma_regs[DMA_STAT] |=3D DMA_STAT_SCSIINT; + + /* + * If raising the ESP IRQ to indicate end of DMA transfer, set + * DMA_STAT_DONE at the same time. In theory this should be done in + * esp_pci_dma_memory_rw(), however there is a delay between setti= ng + * DMA_STAT_DONE and the ESP IRQ arriving which is visible to the + * guest that can cause confusion e.g. Linux + */ + if ((pci->dma_regs[DMA_CMD] & DMA_CMD_MASK) =3D=3D 0x3 && + pci->dma_regs[DMA_WBC] =3D=3D 0) { + pci->dma_regs[DMA_STAT] |=3D DMA_STAT_DONE; + } } else { pci->dma_regs[DMA_STAT] &=3D ~DMA_STAT_SCSIINT; } @@ -306,9 +318,6 @@ static void esp_pci_dma_memory_rw(PCIESPState *pci, uin= t8_t *buf, int len, /* update status registers */ pci->dma_regs[DMA_WBC] -=3D len; pci->dma_regs[DMA_WAC] +=3D len; - if (pci->dma_regs[DMA_WBC] =3D=3D 0) { - pci->dma_regs[DMA_STAT] |=3D DMA_STAT_DONE; - } } =20 static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len) @@ -363,24 +372,13 @@ static const VMStateDescription vmstate_esp_pci_scsi = =3D { } }; =20 -static void esp_pci_command_complete(SCSIRequest *req, size_t resid) -{ - ESPState *s =3D req->hba_private; - PCIESPState *pci =3D container_of(s, PCIESPState, esp); - - esp_command_complete(req, resid); - pci->dma_regs[DMA_WBC] =3D 0; - pci->dma_regs[DMA_STAT] |=3D DMA_STAT_DONE; - esp_pci_update_irq(pci); -} - static const struct SCSIBusInfo esp_pci_scsi_info =3D { .tcq =3D false, .max_target =3D ESP_MAX_DEVS, .max_lun =3D 7, =20 .transfer_data =3D esp_transfer_data, - .complete =3D esp_pci_command_complete, + .complete =3D esp_command_complete, .cancel =3D esp_request_cancelled, }; =20 --=20 2.41.0