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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id f6-20020a05600c4e8600b0040d6ffae526sm32950428wmq.39.2024.01.19.03.37.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:37:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705664244; x=1706269044; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OAd+hsmqGnC7BEM4hV/k6DWbPNlhhbttEWZwCPVCQ9Y=; b=JZOD6ZrJ0ydcaxCQf3yxDshDG3ULMLE1iRC7gRnE0gPuLc1PBgetJr/8RwOXoneFuE cTr/olVC9WRn8mM95mwXM3mpoj1EY0H8tbfznb7j02AawSpQf0HYPDwysMrpLYN+jiZ4 U3xaKchKyTKdRIBPuKH7rzZNtEBJGGsEVuCm6GLG8oQyPf+QVRx+QY70lUdlOKY/iypN qKsn+i+5BJMCil4TR0gDCfqqpvcZrvEKY2fLBRduG8bK6YwcqR2Yi/25+80SjPF/Yy2n Q1dcFWpVVkoDNkzfgRgFZ8z1gaSg3JUk9cMF450Q+OlV4cRmya9VqJ5zJJAC66oS9hci Tcrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705664244; x=1706269044; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OAd+hsmqGnC7BEM4hV/k6DWbPNlhhbttEWZwCPVCQ9Y=; b=DG64PYSJ3Qeet0owGuY8XtTEQIl/ngCozcG0VUHG3V8U58IBc+/3+tW3IiA6bSwI84 DintM+NqfBtY9h2+y4YoSd7PcxrfN0n88gyYdINkcajOBotnvsFVsBZ8Xv6nUoTc+Txv ay/FUGcvvFwSnqyA/lMTam0azauBrUPHTi7EgDTPxpGIO2ZaILY1UGsV+nYOWGrs687q GHN+UuKCVJ4RUI8T2AW+tqujxfTH/eKlTwk2IYxpmyrOZpIWxqJHOVl9S+dfgD3+1sPr EAXC8Al7kgwNYGLq1uwJoSXAB10DRrIgQZzRnr7vcaESLeYQRgiOIoUmhNy4DEp6f5MV eh0w== X-Gm-Message-State: AOJu0YzLYhx0VwwNrXC7N3b7bNXxv9nMvIKOT9DuPbhcIcL/VBMQf2GC R7+U1Ky/YsAFCG26s2bEPDgU3mBjGbdnoFmMo2Ho5LDhyrbHR/J41Va3WYRtyKOkqdczTneBXCF nNmHbsw== X-Google-Smtp-Source: AGHT+IGMDAP70U/XWC2BDJOVuyM0qbZRpEV866bp7+zl1QT7cGWhh+JVskkaK0dz8hJJoVpnkafhMA== X-Received: by 2002:a7b:c3c7:0:b0:40e:5280:2ebc with SMTP id t7-20020a7bc3c7000000b0040e52802ebcmr1254778wmj.152.1705664243768; Fri, 19 Jan 2024 03:37:23 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Mark Cave-Ayland , Guenter Roeck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Fam Zheng Subject: [PULL 30/36] hw/scsi/esp-pci: generate PCI interrupt from separate ESP and PCI sources Date: Fri, 19 Jan 2024 12:34:59 +0100 Message-ID: <20240119113507.31951-31-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1705664510161100001 From: Mark Cave-Ayland The am53c974/dc390 PCI interrupt has two separate sources: the first is fro= m the internal ESP device, and the second is from the PCI DMA transfer logic. Update the ESP interrupt handler so that it sets DMA_STAT_SCSIINT rather th= an driving the PCI IRQ directly, and introduce a new esp_pci_update_irq() func= tion to generate the correct PCI IRQ level. In particular this fixes spurious in= terrupts being generated by setting DMA_STAT_DONE at the end of a transfer if DMA_CM= D_INTE_D isn't set in the DMA_CMD register. Signed-off-by: Mark Cave-Ayland Reviewed-by: Guenter Roeck Tested-by: Guenter Roeck Message-ID: <20240112131529.515642-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/scsi/esp-pci.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c index 7117725371..15dc3c004d 100644 --- a/hw/scsi/esp-pci.c +++ b/hw/scsi/esp-pci.c @@ -77,6 +77,29 @@ struct PCIESPState { ESPState esp; }; =20 +static void esp_pci_update_irq(PCIESPState *pci) +{ + int scsi_level =3D !!(pci->dma_regs[DMA_STAT] & DMA_STAT_SCSIINT); + int dma_level =3D (pci->dma_regs[DMA_CMD] & DMA_CMD_INTE_D) ? + !!(pci->dma_regs[DMA_STAT] & DMA_STAT_DONE) : 0; + int level =3D scsi_level || dma_level; + + pci_set_irq(PCI_DEVICE(pci), level); +} + +static void esp_irq_handler(void *opaque, int irq_num, int level) +{ + PCIESPState *pci =3D PCI_ESP(opaque); + + if (level) { + pci->dma_regs[DMA_STAT] |=3D DMA_STAT_SCSIINT; + } else { + pci->dma_regs[DMA_STAT] &=3D ~DMA_STAT_SCSIINT; + } + + esp_pci_update_irq(pci); +} + static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val) { ESPState *s =3D &pci->esp; @@ -151,6 +174,7 @@ static void esp_pci_dma_write(PCIESPState *pci, uint32_= t saddr, uint32_t val) /* clear some bits on write */ uint32_t mask =3D DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_D= ONE; pci->dma_regs[DMA_STAT] &=3D ~(val & mask); + esp_pci_update_irq(pci); } break; default: @@ -161,17 +185,14 @@ static void esp_pci_dma_write(PCIESPState *pci, uint3= 2_t saddr, uint32_t val) =20 static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr) { - ESPState *s =3D &pci->esp; uint32_t val; =20 val =3D pci->dma_regs[saddr]; if (saddr =3D=3D DMA_STAT) { - if (s->rregs[ESP_RSTAT] & STAT_INT) { - val |=3D DMA_STAT_SCSIINT; - } if (!(pci->sbac & SBAC_STATUS)) { pci->dma_regs[DMA_STAT] &=3D ~(DMA_STAT_ERROR | DMA_STAT_ABORT= | DMA_STAT_DONE); + esp_pci_update_irq(pci); } } =20 @@ -350,6 +371,7 @@ static void esp_pci_command_complete(SCSIRequest *req, = size_t resid) esp_command_complete(req, resid); pci->dma_regs[DMA_WBC] =3D 0; pci->dma_regs[DMA_STAT] |=3D DMA_STAT_DONE; + esp_pci_update_irq(pci); } =20 static const struct SCSIBusInfo esp_pci_scsi_info =3D { @@ -386,7 +408,7 @@ static void esp_pci_scsi_realize(PCIDevice *dev, Error = **errp) "esp-io", 0x80); =20 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io); - s->irq =3D pci_allocate_irq(dev); + s->irq =3D qemu_allocate_irq(esp_irq_handler, pci, 0); =20 scsi_bus_init(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info); } --=20 2.41.0