From nobody Tue Nov 26 16:20:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=126.com ARC-Seal: i=1; a=rsa-sha256; t=1705673085; cv=none; d=zohomail.com; s=zohoarc; b=aJiK1/HQk7JSOKKHgQ5rnf6U4d/fHmlsMJDtrciwG4POdJ3NbXSzT7tq22zQbLo/vq36wH8gh/uY2Y5hzxl4EOtyIQSUJtk2dXIRf/FchrDnGIFMRGTIRy4yVwQcvujdBkl2ZxKedwkzEdj72Gh6HWMBXkjqFp0DjRlihDnuj/Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705673085; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TjhDT4UHFmeijIXUxU99iOjtLtwZOPs1edx/bLXnLUg=; b=Hg1MkYAznCELEQ6WxCHqJdmdrlu5Ytb0RSls57Gsxc7PxP0XlZLR2ztJiHrDmvgjlehmifK4bJo5CizzFqyGTjhEVsA+OIfbd5EnfjVwdcOMdX61XygGO22G/71E3GUitIOsrEP/9FL+omXp9UpaiALw8dcFp7O0jjVxmVZnuUE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705673085396794.4677481539744; Fri, 19 Jan 2024 06:04:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQpTD-0002z4-4A; Fri, 19 Jan 2024 09:03:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQgx3-0000cS-HQ for qemu-devel@nongnu.org; Thu, 18 Jan 2024 23:57:57 -0500 Received: from m16.mail.126.com ([220.197.31.6]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQgwz-0007PS-0J for qemu-devel@nongnu.org; Thu, 18 Jan 2024 23:57:57 -0500 Received: from owl-server.corp.qihoo.net (unknown [218.30.116.113]) by gzga-smtp-mta-g0-3 (Coremail) with SMTP id _____wD3f4IIAapl_faxAQ--.14017S2; Fri, 19 Jan 2024 12:56:41 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=126.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=TjhDT 4UHFmeijIXUxU99iOjtLtwZOPs1edx/bLXnLUg=; b=Bavp8C6ZjroVCkldXpgrb ZMpmRmF8f808OoIQYLGUsSSSdS+vsWsoY9QFvXYho1AR8omQ/iisEWGrnoQyxs8+ RbnR+9h7d+/O5qKVUoQcCR+ttxZZbRVpORTQJOmvhJ8X8M1qH3mTlppR2N0gDXGe 7Io+524uDoKQbAkrxL9EVI= From: owl129@126.com To: qemu-devel@nongnu.org Cc: philmd@linaro.org, owl Subject: [PATCH] This patch implements several Octeon +/II instructions. Date: Fri, 19 Jan 2024 04:56:27 +0000 Message-Id: <20240119045626.9698-1-owl129@126.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3f4IIAapl_faxAQ--.14017S2 X-Coremail-Antispam: 1Uf129KBjvJXoW3Kw1UCF48Gr1DZFWUJF18Zrb_yoWDKFW8pr 10yF18uF48XF17Xr92y3WY9Fs8JF1xAayUK3sIya1rKF48JFs8XwnFqrWYyrW7WF9agr1a yFs8AFWDuFy5t3JanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zi2-e7UUUUU= X-Originating-IP: [218.30.116.113] X-CM-SenderInfo: przoijaz6rjloofrz/1tbiEAFqV2VLZhGbpgABsJ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=220.197.31.6; envelope-from=owl129@126.com; helo=m16.mail.126.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 19 Jan 2024 09:03:38 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @126.com) X-ZM-MESSAGEID: 1705673086655100003 Content-Type: text/plain; charset="utf-8" From: owl Octeon+=20 - SAA=20 - SAAD Octeon2 - LAI - LAID - LAD - LADD - LAS - LASD - LAC - LACD - LAA - LAAD - LAW - LAWD - LWX - LHX - LDX - LBUX - LWUX - LHUX - LBX Signed-off-by: owl --- target/mips/tcg/octeon.decode | 35 ++++ target/mips/tcg/octeon_translate.c | 281 +++++++++++++++++++++++++++++ 2 files changed, 316 insertions(+) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode index 0c787cb498..980ed619d0 100644 --- a/target/mips/tcg/octeon.decode +++ b/target/mips/tcg/octeon.decode @@ -39,3 +39,38 @@ CINS 011100 ..... ..... ..... ..... 11001 . @bit= field POP 011100 rs:5 00000 rd:5 00000 10110 dw:1 SEQNE 011100 rs:5 rt:5 rd:5 00000 10101 ne:1 SEQNEI 011100 rs:5 rt:5 imm:s10 10111 ne:1 + + +# SAA rt, (base) +# SAAD rt, (base) +SAA 011100 base:5 rt:5 00000 00000 011000 +SAAD 011100 base:5 rt:5 00000 00000 011001 + +LAI 011100 ..... ..... ..... 00010 011111 @r3 +LAID 011100 ..... ..... ..... 00011 011111 @r3 +LAD 011100 ..... ..... ..... 00110 011111 @r3 +LADD 011100 ..... ..... ..... 00111 011111 @r3 +LAS 011100 ..... ..... ..... 01010 011111 @r3 +LASD 011100 ..... ..... ..... 01011 011111 @r3 +LAC 011100 ..... ..... ..... 01110 011111 @r3 +LACD 011100 ..... ..... ..... 01111 011111 @r3 +LAA 011100 ..... ..... ..... 10010 011111 @r3 +LAAD 011100 ..... ..... ..... 10011 011111 @r3 +LAW 011100 ..... ..... ..... 10110 011111 @r3 +LAWD 011100 ..... ..... ..... 10111 011111 @r3 + + +# LWX +# LHX +# LDX +# LBUX +# LWUX +# LHUX +# LBX +LWX 011111 ..... ..... ..... 00000 001010 @r3 +LHX 011111 ..... ..... ..... 00100 001010 @r3 +LDX 011111 ..... ..... ..... 01000 001010 @r3 +LBUX 011111 ..... ..... ..... 00110 001010 @r3 +LWUX 011111 ..... ..... ..... 10000 001010 @r3 +LHUX 011111 ..... ..... ..... 10100 001010 @r3 +LBX 011111 ..... ..... ..... 10110 001010 @r3 \ No newline at end of file diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_tr= anslate.c index e25c4cbaa0..e9ec372ad3 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -174,3 +174,284 @@ static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNE= I *a) } return true; } + +/* + * Octeon+ + * https://sourceware.org/legacy-ml/binutils/2011-11/msg00085.html + */ +static bool trans_SAA(DisasContext *ctx, arg_SAA *a) +{ + TCGv t0 =3D tcg_temp_new(); + tcg_gen_qemu_ld_tl(t0, cpu_gpr[a->base], ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + tcg_gen_add_tl(t0, t0, cpu_gpr[a->rt]); + + tcg_gen_qemu_st_tl(t0, cpu_gpr[a->base], ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + return true; +} + +static bool trans_SAAD(DisasContext *ctx, arg_SAAD *a) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_tl(t0, cpu_gpr[a->base], ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); + tcg_gen_add_tl(t0, t0, cpu_gpr[a->rt]); + + tcg_gen_qemu_st_tl(t0, cpu_gpr[a->base], ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); + return true; +} + +/* + * Octeon2 + * https://chromium.googlesource.com/chromiumos/third_party/gdb/+/refs/h= eads/master/opcodes/mips-opc.c + * https://github.com/MarvellEmbeddedProcessors/Octeon-Toolchain + * https://bugs.kde.org/show_bug.cgi?id=3D326444 + * https://gcc.gnu.org/legacy-ml/gcc-patches/2011-12/msg01134.html + */ +static bool trans_LAI(DisasContext *ctx, arg_LAI *a) +{ + TCGv t0 =3D tcg_temp_new(); + tcg_gen_qemu_ld_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + gen_store_gpr(t0, a->rd); + tcg_gen_addi_tl(t0, t0, 1); + + tcg_gen_qemu_st_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + return true; +} + +static bool trans_LAID(DisasContext *ctx, arg_LAID *a) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); + gen_store_gpr(t0, a->rd); + tcg_gen_addi_tl(t0, t0, 1); + + tcg_gen_qemu_st_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); + return true; +} + +static bool trans_LAD(DisasContext *ctx, arg_LAD *a) +{ + TCGv t0 =3D tcg_temp_new(); + tcg_gen_qemu_ld_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + gen_store_gpr(t0, a->rd); + tcg_gen_subi_tl(t0, t0, 1); + + tcg_gen_qemu_st_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + return true; +} + +static bool trans_LADD(DisasContext *ctx, arg_LADD *a) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); + gen_store_gpr(t0, a->rd); + tcg_gen_subi_tl(t0, t0, 1); + + tcg_gen_qemu_st_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); + return true; +} +/* Load Atomic Set Word - LAS; Cavium OCTEON2 */ +static bool trans_LAS(DisasContext *ctx, arg_LAS *a) +{ + TCGv t0 =3D tcg_temp_new(); + tcg_gen_qemu_ld_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + gen_store_gpr(t0, a->rd); + tcg_gen_movi_tl(t0, 0xffffffff); + + tcg_gen_qemu_st_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + + return true; +} +/* Load Atomic Set Doubleword - LASD; Cavium OCTEON2 */ +static bool trans_LASD(DisasContext *ctx, arg_LASD *a) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); + gen_store_gpr(t0, a->rd); + tcg_gen_movi_tl(t0, 0xffffffffffffffffULL); + + tcg_gen_qemu_st_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); + return true; +} +/* Load Atomic Clear Word - LAC; Cavium OCTEON2 */ +static bool trans_LAC(DisasContext *ctx, arg_LAC *a) +{ + TCGv t0 =3D tcg_temp_new(); + tcg_gen_qemu_ld_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + gen_store_gpr(t0, a->rd); + tcg_gen_movi_tl(t0, 0); + + tcg_gen_qemu_st_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + return true; +} +/* Load Atomic Clear Doubleword - LACD; Cavium OCTEON2 */ +static bool trans_LACD(DisasContext *ctx, arg_LACD *a) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); + gen_store_gpr(t0, a->rd); + tcg_gen_movi_tl(t0, 0xffffffffffffffffULL); + + tcg_gen_qemu_st_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); + return true; +} + +/* Load Atomic Add Word - LAA; Cavium OCTEON2 */ +static bool trans_LAA(DisasContext *ctx, arg_LAA *a) +{ + TCGv t0 =3D tcg_temp_new(); + tcg_gen_qemu_ld_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + gen_store_gpr(t0, a->rd); + tcg_gen_add_tl(t0, t0, cpu_gpr[a->rt]); + + tcg_gen_qemu_st_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + return true; +} + +/* Load Atomic Add Doubleword - LAAD; Cavium OCTEON2 */ +static bool trans_LAAD(DisasContext *ctx, arg_LAAD *a) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); + gen_store_gpr(t0, a->rd); + tcg_gen_add_tl(t0, t0, cpu_gpr[a->rt]); + + tcg_gen_qemu_st_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); + return true; +} +/* Load Atomic Swap Word - LAW; Cavium OCTEON2 */ +static bool trans_LAW(DisasContext *ctx, arg_LAW *a) +{ + TCGv t0 =3D tcg_temp_new(); + tcg_gen_qemu_ld_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + gen_store_gpr(t0, a->rd); + tcg_gen_mov_tl(t0, cpu_gpr[a->rt]); + + tcg_gen_qemu_st_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + return true; +} + +static bool trans_LAWD(DisasContext *ctx, arg_LAWD *a) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); + gen_store_gpr(t0, a->rd); + tcg_gen_mov_tl(t0, cpu_gpr[a->rt]); + + tcg_gen_qemu_st_tl(t0, cpu_gpr[a->rs], ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); + return true; +} + + +static bool trans_LWX(DisasContext *ctx, arg_LWX *a) +{ + TCGv t0 =3D tcg_temp_new(); + gen_op_addr_add(ctx, t0, cpu_gpr[a->rs], cpu_gpr[a->rt]); + + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL | + ctx->default_tcg_memop_mask); + + /* on mips64, 32 extend to 64 */ + tcg_gen_ext32s_tl(cpu_gpr[a->rd], t0); + return true; +} + +static bool trans_LHX(DisasContext *ctx, arg_LHX *a) +{ + TCGv t0 =3D tcg_temp_new(); + gen_op_addr_add(ctx, t0, cpu_gpr[a->rs], cpu_gpr[a->rt]); + + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW | + ctx->default_tcg_memop_mask); + + /* 16 extend to 32/64 */ + tcg_gen_ext16s_tl(cpu_gpr[a->rd], t0); + return true; +} + +static bool trans_LDX(DisasContext *ctx, arg_LDX *a) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + gen_op_addr_add(ctx, t0, cpu_gpr[a->rs], cpu_gpr[a->rt]); + + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESQ | + ctx->default_tcg_memop_mask); + /* not extend */ + gen_store_gpr(t0, a->rd); + return true; +} + +static bool trans_LBUX(DisasContext *ctx, arg_LBUX *a) +{ + TCGv t0 =3D tcg_temp_new(); + gen_op_addr_add(ctx, t0, cpu_gpr[a->rs], cpu_gpr[a->rt]); + + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB | + ctx->default_tcg_memop_mask); + + tcg_gen_ext8u_tl(cpu_gpr[a->rd], t0); + return true; +} + +static bool trans_LWUX(DisasContext *ctx, arg_LWUX *a) +{ + TCGv t0 =3D tcg_temp_new(); + gen_op_addr_add(ctx, t0, cpu_gpr[a->rs], cpu_gpr[a->rt]); + + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + + tcg_gen_ext32u_tl(cpu_gpr[a->rd], t0); + return true; +} + +static bool trans_LHUX(DisasContext *ctx, arg_LHUX *a) +{ + TCGv t0 =3D tcg_temp_new(); + gen_op_addr_add(ctx, t0, cpu_gpr[a->rs], cpu_gpr[a->rt]); + + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUW | + ctx->default_tcg_memop_mask); + + tcg_gen_ext16u_tl(cpu_gpr[a->rd], t0); + return true; +} + +static bool trans_LBX(DisasContext *ctx, arg_LBX *a) +{ + TCGv t0 =3D tcg_temp_new(); + gen_op_addr_add(ctx, t0, cpu_gpr[a->rs], cpu_gpr[a->rt]); + + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB | + ctx->default_tcg_memop_mask); + + tcg_gen_ext8s_tl(cpu_gpr[a->rd], t0); + return true; +} --=20 2.34.1