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[124.171.76.150]) by smtp.gmail.com with ESMTPSA id ky12-20020a170902f98c00b001d4c98c7439sm1527067plb.276.2024.01.18.07.25.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jan 2024 07:25:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1705591536; x=1706196336; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SsVO3XzE6qK2xy1kN50Qjep3b+zCKGJ+P5EuOLNL/uY=; b=UnWugjg1xeATJ2kmdkB/svGpvEB+YujooS2GYJ6X+PmYXzHntR9EWFrQf9Wg4GKs5g EizXB9zD36KeAD4vuuJGooMjkkbtFIntXZe6X1ore3QLXvbjQWiYOoBzx4jXF5IPO2CL Ubs/xgmu2EMWRD324smkDMuKIQ+q4CFC4z//nJhe9tqMdksLbVGja/GfS+eyPBlToU9S cbFFH51DwO1nAbrMN2iL0ubgSq5FQ9RKJCL962hsAa37MDSrnhp6rdpYEVimf9oGFg/a 3Q+WrL2e9XZSnLuJKZRnNVrKcTnJCnMVxPBLSWiMnmkihBRWaKaqHlsOqzjHyq/7z6dA O7IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705591536; x=1706196336; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SsVO3XzE6qK2xy1kN50Qjep3b+zCKGJ+P5EuOLNL/uY=; b=H4WlBIxyLGQjP2JptYjgOG5fDDTgSFBpunCSbi5arh0CNiYRcnJjUj0kdbiqV6lnp1 1mIj/L5sVO80qW6kJOjqlsZ0E76tPnD7TcfquD+vOupFbMjX/NDlOnVUequnxMALLWJU guow1Z54ieJKZjqdM2fGBwCgDWVDOiM6Ck3YHEPnf1qOIy3Qq3DeueutJyF62+mmzdi3 OkkkJ1tyDw2srqwJ+qUq2XcJJGGi28B7B8nbt/bMdQPwSwQzJ7S8pen/CJmmlPGdoyJL pCvSAKZzOvvwr3QBd3HqiXyvXg17VJx0JOa+I26vEBR3EwO9BbpE/+B73tyuMr0bd9aJ 7nCA== X-Gm-Message-State: AOJu0Yzlah3zN1S9vCr5+DQEgC0elUuCxI6qlORt0z2nnVucQPe3/+OT ppCHSOY7wS3N+0v7CsQGK+T5pZxYSXghj+dbAq1KIgxBrIu3ucm4T6OsEOQW X-Google-Smtp-Source: AGHT+IG6Dy78rwUnFQU/4Hn+kTuEb8xmsbskvrA/UtQ8VwuwIpE0ndqYwY5vNv2LzHvXeQzjZ5/CGA== X-Received: by 2002:a17:902:d505:b0:1d7:6ba:1246 with SMTP id b5-20020a170902d50500b001d706ba1246mr1062549plg.65.1705591536292; Thu, 18 Jan 2024 07:25:36 -0800 (PST) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , Daniel Henrique Barboza , David Gibson , Harsh Prateek Bora , qemu-devel@nongnu.org Subject: [PATCH v3 1/2] target/ppc: Make checkstop actually stop the system Date: Fri, 19 Jan 2024 01:25:22 +1000 Message-ID: <20240118152523.178576-2-npiggin@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240118152523.178576-1-npiggin@gmail.com> References: <20240118152523.178576-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=npiggin@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1705591606451100005 Content-Type: text/plain; charset="utf-8" checkstop state does not halt the system, interrupts continue to be serviced, and other CPUs run. Stop the machine with qemu_system_guest_panicked. Change the logging not to print separately to stderr because a checkstop is a guest error (or perhaps a simulated machine error) rather than a QEMU error. CPU registers are dumped. Signed-off-by: Nicholas Piggin --- Since v1: - Fix loop exit so it stops on the checkstop-causing instruction, rather th= an after it. Since v2: - Use qemu_system_guest_panicked rather than vm_stop (Richard) - Move away from printing to stderr (Zoltan) - Reduce changes to log messages. --- target/ppc/excp_helper.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 1db6aaf7ee..022adc36c5 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -19,6 +19,8 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "qemu/log.h" +#include "sysemu/sysemu.h" +#include "sysemu/runstate.h" #include "cpu.h" #include "exec/exec-all.h" #include "internal.h" @@ -427,20 +429,29 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu, t= arget_ulong vector, static void powerpc_mcheck_checkstop(CPUPPCState *env) { CPUState *cs =3D env_cpu(env); + FILE *f; =20 if (FIELD_EX64(env->msr, MSR, ME)) { return; } =20 - /* Machine check exception is not enabled. Enter checkstop state. */ - fprintf(stderr, "Machine check while not allowed. " - "Entering checkstop state\n"); - if (qemu_log_separate()) { - qemu_log("Machine check while not allowed. " - "Entering checkstop state\n"); + /* + * This stops the machine and logs CPU state without killing QEMU + * (like cpu_abort()) so the machine can still be debugged (because + * it is often a guest error). + */ + + f =3D qemu_log_trylock(); + if (f) { + fprintf(f, "Entering checkstop state: " + "machine check with MSR[ME]=3D0\n"); + cpu_dump_state(cs, f, CPU_DUMP_FPU | CPU_DUMP_CCOP); + qemu_log_unlock(f); } - cs->halted =3D 1; - cpu_interrupt_exittb(cs); + + qemu_system_guest_panicked(NULL); + + cpu_loop_exit_noexc(cs); } =20 static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) --=20 2.42.0 From nobody Sat Sep 21 02:38:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1705591605; cv=none; d=zohomail.com; s=zohoarc; b=CO0WnQpTOxgqXOoS9e2MPj7WobgRXp3JSsZeSGBPI2485h6LKzrBU3ESw7MjKwdQWhmGJlK3kPgKpOOnxzY6yrw6ZnhDgkvhh56aOL29ZeHowcWg9EcBCdlfJcRUHsdzuqIbbcD7x/oQI1D8EV234lXH6ioSohkTWqhl8r0RaE8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705591605; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6IKauuoZqyf7alvPQalZahhh/PZKUoEbA2ItZI3GCZY=; b=AFhmK3eDSkY9LqlYy0jWHHNyV8QOQ+3BTS3Ri8xOivhmVzkuNJVcDHI1JqilfB8diLAN85JZiPdzy7iCSPGJRFBW+QAn8LSitjsgucG6JMmpOrzZ9AyyZ3Nqi9JborLFBUJTn/FDVCtcNMaNUQ1fAgSug3Uy2jc3k5jttMSAIig= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705591605157200.69166375061423; Thu, 18 Jan 2024 07:26:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQUH5-000125-Vv; Thu, 18 Jan 2024 10:25:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQUH4-000114-8w; Thu, 18 Jan 2024 10:25:46 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rQUH1-00074u-2y; Thu, 18 Jan 2024 10:25:46 -0500 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1d54b765414so86314155ad.0; Thu, 18 Jan 2024 07:25:42 -0800 (PST) Received: from wheely.local0.net (124-171-76-150.tpgi.com.au. [124.171.76.150]) by smtp.gmail.com with ESMTPSA id ky12-20020a170902f98c00b001d4c98c7439sm1527067plb.276.2024.01.18.07.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jan 2024 07:25:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1705591541; x=1706196341; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6IKauuoZqyf7alvPQalZahhh/PZKUoEbA2ItZI3GCZY=; b=drHQL9K1FnLTPWX/UMOv7Nf14004smfSiHGB1/GFFxiOVzbocD13fDUaqbu3fttPBS IXoUNzTfKcp2tPyqX00KwMn0pCCSM55roNZh7g3KYhEc3/0xj8XNxPRqI34rMBqO164/ 8Q54VqLm6BFuP5bDabEDfqkCx33hxREBzcXJCzJPsFOhd3Tr/eNK969MDkz7ye40M+2r 0NpE+xxQxtZ8QXb6T8YHW9zzoancE5vBBSS1iFXtKhv57CFvX0uy55+UqqpVVoiHlGnK 3KZgf/55EPvmt10o/j+oanjaarYnBdEsSRUhZxqvhTYcmojsfazFWvVoYSxBd+w+027T GzaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705591541; x=1706196341; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6IKauuoZqyf7alvPQalZahhh/PZKUoEbA2ItZI3GCZY=; b=vdyVXXcuFC4rFae3oidRoIDr3RgPAX3DSiwKnTy4XEr4rJH/nae8203eVk9Vx97dLy xmN62e6palFnKUiviNYGGs1WjrFP1OeYUIQHRcPB6NnhthxpNtYAPaNgcOnxf6WUsCET 94beS1nnQypfCzPEhc3BSeTt9e0A/ECgszB2wodI90ZX42EOucx8wIxeOIS6WRhmwwTF n6XFVlVfv6s3pwa73ufNmXEY8DtmBpxY+LWLLSHdQIOtH0IiozdCO5ZtBhEPCv7rPEjo xofYX6Y7AS+4Fo7HOHwEgiCzN1JKIWcNlKnnVVO2XsYnbAhkhvQ60p02NAMGZGr0mhKx NPKQ== X-Gm-Message-State: AOJu0Yz8/VsdSbHX5ezqdf4zAlihB+nf6kr2KzfWScs6gt40F14s2elG We39KOC55lRy2jdHD2LwhbI1xkmWLubjvomSmCW7DS2y1oHp/vn2+b3k0DqB X-Google-Smtp-Source: AGHT+IFb1STuZt38HFU6YQ6OOdjIBuiVitsWYfaC96aojqSJ5FmgEVrfKTKsI4w1FPDLEm9APipkiw== X-Received: by 2002:a17:902:cecf:b0:1d4:5268:27ed with SMTP id d15-20020a170902cecf00b001d4526827edmr1153056plg.21.1705591540849; Thu, 18 Jan 2024 07:25:40 -0800 (PST) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , Daniel Henrique Barboza , David Gibson , Harsh Prateek Bora , qemu-devel@nongnu.org Subject: [PATCH v3 2/2] target/ppc: Implement attn instruction on BookS 64-bit processors Date: Fri, 19 Jan 2024 01:25:23 +1000 Message-ID: <20240118152523.178576-3-npiggin@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240118152523.178576-1-npiggin@gmail.com> References: <20240118152523.178576-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1705591606519100009 Content-Type: text/plain; charset="utf-8" attn is an implementation-specific instruction that on POWER (and G5/ 970) can be enabled with a HID bit (disabled =3D illegal), and executing it causes the host processor to stop and the service processor to be notified. Generally used for debugging. Implement attn and make it checkstop the system, which should be good enough for QEMU debugging. Signed-off-by: Nicholas Piggin --- Since v1: - New patch that also uses checkstop function Since v2: - Include support for 970. - Add class attn enable check, similar to check_pow. --- target/ppc/cpu.h | 16 +++++++- target/ppc/helper.h | 1 + target/ppc/cpu_init.c | 82 +++++++++++++++++++++++++++++++++++++--- target/ppc/excp_helper.c | 59 +++++++++++++++++++---------- target/ppc/translate.c | 11 ++++++ roms/skiboot | 2 +- 6 files changed, 143 insertions(+), 28 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 376aee652f..0c6d3e7722 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1384,6 +1384,9 @@ struct CPUArchState { /* Power management */ int (*check_pow)(CPUPPCState *env); =20 + /* attn instruction enable */ + int (*check_attn)(CPUPPCState *env); + #if !defined(CONFIG_USER_ONLY) void *load_info; /* holds boot loading state */ #endif @@ -1532,6 +1535,7 @@ struct PowerPCCPUClass { int n_host_threads; void (*init_proc)(CPUPPCState *env); int (*check_pow)(CPUPPCState *env); + int (*check_attn)(CPUPPCState *env); }; =20 ObjectClass *ppc_cpu_class_by_name(const char *name); @@ -2324,6 +2328,8 @@ void ppc_compat_add_property(Object *obj, const char = *name, #define HID0_NAP (1 << 22) /* pre-2.06 */ #define HID0_HILE PPC_BIT(19) /* POWER8 */ #define HID0_POWER9_HILE PPC_BIT(4) +#define HID0_ENABLE_ATTN PPC_BIT(31) /* POWER8 */ +#define HID0_POWER9_ENABLE_ATTN PPC_BIT(3) =20 /*************************************************************************= ****/ /* PowerPC Instructions types definitions = */ @@ -2520,6 +2526,8 @@ enum { PPC2_MEM_LWSYNC =3D 0x0000000000200000ULL, /* ISA 2.06 BCD assist instructions = */ PPC2_BCDA_ISA206 =3D 0x0000000000400000ULL, + /* attn instruction found in IBM POWER (including 970) = */ + PPC2_ATTN =3D 0x0000000000800000ULL, =20 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX= | \ PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ @@ -2529,7 +2537,7 @@ enum { PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \ - PPC2_BCDA_ISA206) + PPC2_BCDA_ISA206 | PPC2_ATTN) }; =20 /*************************************************************************= ****/ @@ -3028,6 +3036,12 @@ static inline int check_pow_nocheck(CPUPPCState *env) return 1; } =20 +/* attn enable check = */ +static inline int check_attn_none(CPUPPCState *env) +{ + return 0; +} + /*************************************************************************= ****/ /* PowerPC implementations definitions = */ =20 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index cb1b5345fb..cbd94ea51f 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -828,5 +828,6 @@ DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, e= nv) #if defined(TARGET_PPC64) DEF_HELPER_1(clrbhrb, void, env) DEF_HELPER_FLAGS_2(mfbhrbe, TCG_CALL_NO_WG, i64, env, i32) +DEF_HELPER_1(attn, noreturn, env) #endif #endif diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index d42996bbb0..bf84c5c20f 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2119,6 +2119,26 @@ static int check_pow_hid0_74xx(CPUPPCState *env) return 0; } =20 +#if defined(TARGET_PPC64) +static int check_attn_hid0(CPUPPCState *env) +{ + if (env->spr[SPR_HID0] & HID0_ENABLE_ATTN) { + return 1; + } + + return 0; +} + +static int check_attn_hid0_power9(CPUPPCState *env) +{ + if (env->spr[SPR_HID0] & HID0_POWER9_ENABLE_ATTN) { + return 1; + } + + return 0; +} +#endif + static void init_proc_405(CPUPPCState *env) { register_40x_sprs(env); @@ -2150,6 +2170,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 405"; pcc->init_proc =3D init_proc_405; pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_DCR | PPC_WRTEE | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | @@ -2222,6 +2243,7 @@ POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 440 EP"; pcc->init_proc =3D init_proc_440EP; pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -2260,6 +2282,7 @@ POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 460 EX"; pcc->init_proc =3D init_proc_440EP; pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -2320,6 +2343,7 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 440 GP"; pcc->init_proc =3D init_proc_440GP; pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | PPC_CACHE | PPC_CACHE_ICBI | @@ -2394,6 +2418,7 @@ POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 440x5"; pcc->init_proc =3D init_proc_440x5; pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_DCR | PPC_WRTEE | PPC_RFMCI | PPC_CACHE | PPC_CACHE_ICBI | @@ -2429,6 +2454,7 @@ POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *dat= a) dc->desc =3D "PowerPC 440x5 with double precision FPU"; pcc->init_proc =3D init_proc_440x5; pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_STFIWX | @@ -2477,6 +2503,7 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) dc->desc =3D "Freescale 5xx cores (aka RCPU)"; pcc->init_proc =3D init_proc_MPC5xx; pcc->check_pow =3D check_pow_none; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MEM_EIEIO | PPC_MEM_SYNC | PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | @@ -2519,6 +2546,7 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) dc->desc =3D "Freescale 8xx cores (aka PowerQUICC)"; pcc->init_proc =3D init_proc_MPC8xx; pcc->check_pow =3D check_pow_none; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MEM_EIEIO | PPC_MEM_SYNC | PPC_CACHE_ICBI | PPC_MFTB; @@ -2569,6 +2597,7 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC G2"; pcc->init_proc =3D init_proc_G2; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_STFIWX | @@ -2607,6 +2636,7 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC G2LE"; pcc->init_proc =3D init_proc_G2; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_STFIWX | @@ -2753,6 +2783,7 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) dc->desc =3D "e200 core"; pcc->init_proc =3D init_proc_e200; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; /* * XXX: unimplemented instructions: * dcblc @@ -3046,6 +3077,7 @@ POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) dc->desc =3D "e500v1 core"; pcc->init_proc =3D init_proc_e500v1; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_SPE | PPC_SPE_SINGLE | PPC_WRTEE | PPC_RFDI | @@ -3089,6 +3121,7 @@ POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) dc->desc =3D "e500v2 core"; pcc->init_proc =3D init_proc_e500v2; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | PPC_WRTEE | PPC_RFDI | @@ -3132,6 +3165,7 @@ POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) dc->desc =3D "e500mc core"; pcc->init_proc =3D init_proc_e500mc; pcc->check_pow =3D check_pow_none; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | PPC_WRTEE | PPC_RFDI | PPC_RFMCI | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | @@ -3178,6 +3212,7 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) dc->desc =3D "e5500 core"; pcc->init_proc =3D init_proc_e5500; pcc->check_pow =3D check_pow_none; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | PPC_WRTEE | PPC_RFDI | PPC_RFMCI | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | @@ -3226,6 +3261,7 @@ POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) dc->desc =3D "e6500 core"; pcc->init_proc =3D init_proc_e6500; pcc->check_pow =3D check_pow_none; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | PPC_WRTEE | PPC_RFDI | PPC_RFMCI | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | @@ -3288,6 +3324,7 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 603"; pcc->init_proc =3D init_proc_603; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3327,6 +3364,7 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 603e"; pcc->init_proc =3D init_proc_603; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3372,6 +3410,7 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) dc->desc =3D "e300 core"; pcc->init_proc =3D init_proc_e300; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_STFIWX | @@ -3427,6 +3466,7 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 604"; pcc->init_proc =3D init_proc_604; pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3472,6 +3512,7 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 604E"; pcc->init_proc =3D init_proc_604E; pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3528,6 +3569,7 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 740"; pcc->init_proc =3D init_proc_740; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3593,6 +3635,7 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 750"; pcc->init_proc =3D init_proc_750; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3739,6 +3782,7 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 750 CL"; pcc->init_proc =3D init_proc_750cl; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; /* * XXX: not implemented: * cache lock instructions: @@ -3846,6 +3890,7 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 750CX"; pcc->init_proc =3D init_proc_750cx; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3918,6 +3963,7 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 750FX"; pcc->init_proc =3D init_proc_750fx; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3990,6 +4036,7 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 750GX"; pcc->init_proc =3D init_proc_750gx; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -4049,6 +4096,7 @@ POWERPC_FAMILY(745)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 745"; pcc->init_proc =3D init_proc_745; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -4094,6 +4142,7 @@ POWERPC_FAMILY(755)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 755"; pcc->init_proc =3D init_proc_755; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -4160,6 +4209,7 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 7400 (aka G4)"; pcc->init_proc =3D init_proc_7400; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -4239,6 +4289,7 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 7410 (aka G4)"; pcc->init_proc =3D init_proc_7410; pcc->check_pow =3D check_pow_hid0; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -4339,6 +4390,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 7440 (aka G4)"; pcc->init_proc =3D init_proc_7440; pcc->check_pow =3D check_pow_hid0_74xx; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -4461,6 +4513,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 7450 (aka G4)"; pcc->init_proc =3D init_proc_7450; pcc->check_pow =3D check_pow_hid0_74xx; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -4590,6 +4643,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 7445 (aka G4)"; pcc->init_proc =3D init_proc_7445; pcc->check_pow =3D check_pow_hid0_74xx; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -4721,6 +4775,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 7455 (aka G4)"; pcc->init_proc =3D init_proc_7455; pcc->check_pow =3D check_pow_hid0_74xx; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -4872,6 +4927,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 7457 (aka G4)"; pcc->init_proc =3D init_proc_7457; pcc->check_pow =3D check_pow_hid0_74xx; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -5006,6 +5062,7 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC e600"; pcc->init_proc =3D init_proc_e600; pcc->check_pow =3D check_pow_hid0_74xx; + pcc->check_attn =3D check_attn_none; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -5917,6 +5974,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data) dc->desc =3D "PowerPC 970"; pcc->init_proc =3D init_proc_970; pcc->check_pow =3D check_pow_970; + pcc->check_attn =3D check_attn_hid0; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -5926,7 +5984,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data) PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_64B | PPC_ALTIVEC | PPC_SEGMENT_64B | PPC_SLBI; - pcc->insns_flags2 =3D PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; + pcc->insns_flags2 =3D PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC | PPC2_ATTN; pcc->msr_mask =3D (1ull << MSR_SF) | (1ull << MSR_VR) | (1ull << MSR_POW) | @@ -5992,6 +6050,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) dc->desc =3D "POWER5+"; pcc->init_proc =3D init_proc_power5plus; pcc->check_pow =3D check_pow_970; + pcc->check_attn =3D check_attn_hid0; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -6003,7 +6062,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) PPC_64B | PPC_POPCNTB | PPC_SEGMENT_64B | PPC_SLBI; - pcc->insns_flags2 =3D PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; + pcc->insns_flags2 =3D PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC | PPC2_ATTN; pcc->msr_mask =3D (1ull << MSR_SF) | (1ull << MSR_VR) | (1ull << MSR_POW) | @@ -6100,6 +6159,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->pcr_supported =3D PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER7; pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_hid0; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -6117,7 +6177,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | - PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA20= 6; + PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA20= 6 | + PPC2_ATTN; pcc->msr_mask =3D (1ull << MSR_SF) | (1ull << MSR_VR) | (1ull << MSR_VSX) | @@ -6262,6 +6323,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->pcr_supported =3D PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_= 2_05; pcc->init_proc =3D init_proc_POWER8; pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_hid0; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -6282,7 +6344,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | - PPC2_BCDA_ISA206; + PPC2_BCDA_ISA206 | PPC2_ATTN; pcc->msr_mask =3D (1ull << MSR_SF) | (1ull << MSR_HV) | (1ull << MSR_TM) | @@ -6458,6 +6520,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER9; pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_hid0_power9; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -6478,7 +6541,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWS= YNC | - PPC2_BCDA_ISA206; + PPC2_BCDA_ISA206 | PPC2_ATTN; pcc->msr_mask =3D (1ull << MSR_SF) | (1ull << MSR_HV) | (1ull << MSR_TM) | @@ -6637,6 +6700,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER10; pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_hid0_power9; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -6657,7 +6721,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | - PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; + PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206 | PPC2_ATTN; pcc->msr_mask =3D (1ull << MSR_SF) | (1ull << MSR_HV) | (1ull << MSR_TM) | @@ -6878,6 +6942,11 @@ static void init_ppc_proc(PowerPCCPU *cpu) warn_report("no power management check handler registered." " Attempt QEMU to crash very soon !"); } + + if (env->check_attn =3D=3D NULL) { + warn_report("no attn check handler registered." + " Attempt QEMU to crash very soon !"); + } } =20 =20 @@ -7340,6 +7409,7 @@ static void ppc_cpu_instance_init(Object *obj) env->flags =3D pcc->flags; env->bfd_mach =3D pcc->bfd_mach; env->check_pow =3D pcc->check_pow; + env->check_attn =3D pcc->check_attn; =20 /* * Mark HV mode as supported if the CPU has an MSR_HV bit in the diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 022adc36c5..58fd08729a 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -188,7 +188,45 @@ static void ppc_excp_debug_sw_tlb(CPUPPCState *env, in= t excp) env->error_code); } =20 +/* + * This stops the machine and logs CPU state without killing QEMU (like + * cpu_abort()) because it is often a guest error as opposed to a QEMU err= or, + * so the machine can still be debugged. + */ +static G_NORETURN void powerpc_checkstop(CPUPPCState *env, const char *rea= son) +{ + CPUState *cs =3D env_cpu(env); + FILE *f; + + /* + * This stops the machine and logs CPU state without killing QEMU + * (like cpu_abort()) so the machine can still be debugged (because + * it is often a guest error). + */ + + f =3D qemu_log_trylock(); + if (f) { + fprintf(f, "Entering checkstop state: %s\n", reason); + cpu_dump_state(cs, f, CPU_DUMP_FPU | CPU_DUMP_CCOP); + qemu_log_unlock(f); + } + + qemu_system_guest_panicked(NULL); + + cpu_loop_exit_noexc(cs); +} + #if defined(TARGET_PPC64) +void helper_attn(CPUPPCState *env) +{ + if ((*env->check_attn)(env)) { + powerpc_checkstop(env, "host executed attn"); + } else { + raise_exception_err(env, POWERPC_EXCP_HV_EMU, + POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); + } +} + static int powerpc_reset_wakeup(CPUPPCState *env, int excp, target_ulong *= msr) { /* We no longer are in a PM state */ @@ -428,30 +466,11 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu, t= arget_ulong vector, =20 static void powerpc_mcheck_checkstop(CPUPPCState *env) { - CPUState *cs =3D env_cpu(env); - FILE *f; - if (FIELD_EX64(env->msr, MSR, ME)) { return; } =20 - /* - * This stops the machine and logs CPU state without killing QEMU - * (like cpu_abort()) so the machine can still be debugged (because - * it is often a guest error). - */ - - f =3D qemu_log_trylock(); - if (f) { - fprintf(f, "Entering checkstop state: " - "machine check with MSR[ME]=3D0\n"); - cpu_dump_state(cs, f, CPU_DUMP_FPU | CPU_DUMP_CCOP); - qemu_log_unlock(f); - } - - qemu_system_guest_panicked(NULL); - - cpu_loop_exit_noexc(cs); + powerpc_checkstop(env, "machine check with MSR[ME]=3D0"); } =20 static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index bdd39c89e0..80c10b9bae 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6633,6 +6633,16 @@ static void gen_dform3D(DisasContext *ctx) } =20 #if defined(TARGET_PPC64) +/* attn */ +static void gen_attn(DisasContext *ctx) +{ +#if defined(CONFIG_USER_ONLY) + GEN_PRIV(ctx); +#else + gen_helper_attn(tcg_env); +#endif +} + /* brd */ static void gen_brd(DisasContext *ctx) { @@ -6664,6 +6674,7 @@ static void gen_brh(DisasContext *ctx) =20 static opcode_t opcodes[] =3D { #if defined(TARGET_PPC64) +GEN_HANDLER_E(attn, 0x00, 0x00, 0x08, 0xFFFFFDFF, PPC_NONE, PPC2_ATTN), GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), diff --git a/roms/skiboot b/roms/skiboot index dbd5de6624..24a7eb3596 160000 --- a/roms/skiboot +++ b/roms/skiboot @@ -1 +1 @@ -Subproject commit dbd5de6624d7466bb67d1eb4e57bc3a8e2ad9e87 +Subproject commit 24a7eb35966d93455520bc2debdd7954314b638b --=20 2.42.0